CN202838092U - Rack server based on loongson central processing unit (CPU) and north bridge chip SR5690 - Google Patents
Rack server based on loongson central processing unit (CPU) and north bridge chip SR5690 Download PDFInfo
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- CN202838092U CN202838092U CN 201220250255 CN201220250255U CN202838092U CN 202838092 U CN202838092 U CN 202838092U CN 201220250255 CN201220250255 CN 201220250255 CN 201220250255 U CN201220250255 U CN 201220250255U CN 202838092 U CN202838092 U CN 202838092U
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- 238000012544 monitoring process Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 2
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- 238000009529 body temperature measurement Methods 0.000 description 1
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Abstract
The utility model provides a rack server based on a loongson central processing unit (CPU) and a north bridge chip SR5690. The rack server based on the loongson CPU and the north bridge chip SR5690 comprises a power source arranged in a case, a main board, and peripheral interfaces arranged on a front panel and a rear panel of the case. The main board is provided with the loongson CPU, the north bridge chip SR5690, a south bridge chip SP5100, an internal memory, a network card, a display card and a management control unit. The loongson CPU is connected with the north bridge chip SR5690 through a HyperTransport (HT) bus. The north bridge chip is connected with the south bridge chip SP5100 through an A-Link bus. The south bridge chip is connected with the display card through a peripheral component interconnect (PCI) bus. The north bridge chip is connected with the network card through a peripheral component interface express (PCIE) bus. The management control unit transmits data through a network card interface arranged on the rear panel of the case. The rack server utilizes the combination of the loongson CPU and the north bridge chip SR5690 and the south bridge chip SP5100, and finds a good solution to solve the problem of application of the loongson CPU.
Description
Technical Field
The utility model belongs to the server field, concretely relates to rack server based on godson CPU and north bridge chip SR 5690.
Background
Currently known Loongson No. 3 series CPUs include 4-core 3A, 8-core 3B, 8-core, or 16-core 3C CPUs. The loongson 3A CPU is already in mass production, and the other two CPUs are still in the stage of developing the sample wafers.
The appearance of the Loongson No. 3 series CPU breaks the embarrassing situation of no core in the field of Chinese high-performance servers, and brings a new height to the IT industry of China. However, the next serious problem is the industrialization of the CPU, and if the problem of poor industrialization is solved, the loongson CPU is still a CPU which cannot be used and is only conceptual, and can only stay in a laboratory. As the loongson No. 3 series CPU has short time to come out, various matched application schemes are to be further improved. How to find the chip adapting to the Loongson CPU and solve the application technology of the Loongson CPU in the server is an important precondition for the Loongson CPU to be widely applied in the server market. Therefore, there is an urgent need for those skilled in the art to develop a loongson CPU-based rack server.
SUMMERY OF THE UTILITY MODEL
Since the advent of Loongson CPUs, there have been few application schemes. Therefore, the utility model provides a frame server based on godson CPU, it provides a fine solution for godson CPU's practicality.
The utility model discloses a following technical scheme realizes:
a rack server based on a Loongson CPU and a north bridge chip SR5690 comprises a power supply, a mainboard and peripheral interfaces, wherein the power supply and the mainboard are arranged in a case, the peripheral interfaces are arranged on a front panel and a rear panel of the case, and the mainboard is provided with the Loongson CPU, the north bridge chip SR5690, a south bridge chip SP5100, a memory, a network card, a display card and a management control unit; the Loongson CPU is connected with a north bridge chip SR5690 through an HT bus, the north bridge chip is connected with a south bridge chip SP5100 through an A-Link bus, the south bridge chip is connected with a display card through a PCI bus, the north bridge chip is connected with a network card through a PCIE bus, and the management control unit transmits data through a network card interface arranged on a rear panel of the chassis.
Furthermore, the number of the Loongson CPUs is two, namely one Loongson CPU is a main CPU, the other Loongson CPU is a slave CPU, and the two Loongson CPUs are connected through an HT bus to form a symmetrical multiprocessing architecture.
Further, the north bridge SR5690 is connected to two PCIE16X slots and one PCIE8X slot through a PCIE bus.
Further, the management control unit employs an AST2050 chip.
Furthermore, a temperature acquisition unit and a fan are arranged on the main board, the temperature acquisition unit transmits acquired temperature data to the management control unit, and the management control unit controls the rotating speed of the fan according to the temperature data.
Furthermore, a voltage acquisition circuit and an up-down control circuit are arranged on the mainboard, the voltage acquisition circuit is connected with the management control unit, and the up-down control circuit is respectively connected with the management control unit and a power on-off button of the front panel of the case.
Further, the peripheral interface arranged on the front panel of the chassis comprises a USB interface I, a hard disk interface and a button, the USB interface I and the hard disk interface are respectively connected with the south bridge chip SP5100, and the button is connected with an electrical control circuit on the motherboard.
Further, the peripheral interface arranged on the rear panel of the chassis comprises a graphics card interface, a mouse interface, a keyboard interface, a serial port, a USB interface II and a network card interface, wherein the graphics card interface is connected with the graphics card, the mouse interface, the keyboard interface and the serial port are respectively connected with the south bridge chip SP5100 through I/O chips, the USB interface II is connected with the south bridge chip SP5100, and the network card interface is connected with the network card.
Furthermore, the network card adopts an intel82576 chip with two gigabit ports; the display card adopts a VGA display card.
The beneficial effects of the utility model reside in that:
1) the rack server adopts a combined structure of the Loongson CPU + the north bridge SR5690+ the south bridge SP5100, and a good approach is found for solving the application of the Loongson CPU.
2) The Loongson CPU of the rack server adopts an SMP (symmetric multiprocessing) architecture, and the architecture is also suitable for the case of a single CPU. The Loongson 3A CPU rack server of this patent has the ability of high IO bandwidth. The rack server supports 2 gigabit networks, 2 PCIE16X slots, and 1 PCIE8X slot. The 3 PCIE slots can be inserted with standard PCIE cards with different purposes, and the application range of the Loongson rack server is expanded.
3) The rack server is responsible for monitoring the temperature, the voltage and the rotating speed of a fan of the rack server through a management control unit (BMC), transmitting the temperature, the voltage and the rotating speed of the fan to a remote user control end through a management hundred-mega Ethernet and receiving the control of a remote user; the management control unit (BMC) can also enable the rack server to be seamlessly integrated into a management system of the X86 cluster which is managed by the BMC, so that the heterogeneity of the cluster is achieved, and the management of users is facilitated; meanwhile, the temperature monitoring, voltage monitoring, startup and shutdown functions and the alarming function are realized, and the safe operation of the server is automatically guaranteed.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of the rack server based on a Loongson CPU and a north bridge chip SR5690 of the present invention.
Detailed Description
The rack server of the present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, the rack server of this embodiment includes a power supply, a main board disposed in a chassis, and peripheral interfaces disposed on a front panel and a rear panel of the chassis;
the mainboard is provided with a Loongson CPU, a north bridge chip SR5690, a south bridge chip SP5100, a memory, a network card, a display card and a management control unit; the Loongson CPU is connected with a north bridge chip SR5690 through an HT bus, the north bridge chip is connected with a south bridge chip SP5100 through an A-Link bus, the south bridge chip is connected with a display card through a PCI bus, the north bridge chip is connected with a network card through a PCIE bus, and the management control unit transmits data through a network card interface arranged on a rear panel of the chassis.
The Loongson CPU in the rack server is not only suitable for a Loongson 3A CPU, but also suitable for a Loongson 3B CPU and a Loongson 3C CPU. Because the Loongson 3A CPU and the Loongson 3B CPU are pin-to-pin compatible (the pin-to-pin compatibility means that the number, definition and size of two types of IC signal pins are completely the same and can be simply replaced), the Loongson 3A CPU can be directly replaced into the Loongson 3B CPU on the Loongson 3A CPU rack server to be normally used. The Loongson 3C CPU is a next-generation product of the Loongson 3ACPU and the Loongson 3B CPU, is compatible with the functions of the Loongson 3A CPU, and is also suitable for the Loongson 3 CCPU.
The following describes the rack server of the present invention in detail by taking the loongson 3A CPU as an example:
as shown in fig. 1, the rack server mainly includes two major parts: a basic function part and a management monitoring part.
The basic functional part comprises the following components:
1) 2 Loongson 3A CPUs, forming an SMP (symmetric Multi-Processing) architecture, one of which is a master CPU (host) and the other is a slave CPU (slave). HT0bus of the master CPU is connected with HT0bus of the slave CPU, and HT1bus of the master CPU is connected with AMD chips. AMD chipsets refer to Northbridge SR5690, southbridge SP 5100.
This patent also covers the case of only one CPU, i.e. the slave CPU is removed and only the host CPU is available.
Two different configuration situations of the SMP architecture and the single CPU can be flexibly converted: without installing the slave CPU, the SMP architecture becomes a single CPU configuration by disabling the HT0 of the main CPU at the BIOS level.
2) Memory device
The Loongson CPU supports 8 DDR2 memories or DDR3 memories, each CPU supports 4 memories, and the capacity of each memory can reach 4 GB. The Loongson 3A CPU is provided with 2 memory controllers, and each memory controller is connected with 2 memories.
3）AMD chipsets
AMD chipsets comprise a north bridge chip SR5690 and a south bridge chip SP5100, and the SR5690 is connected with HT1bus of a Loongson 3A host CPU through HT bus. SR5690 and SP5100 are connected through A-Link bus (protocol developed by PCIE4X in AMD).
The PCI-E bus of SR5690 has 42lanes (42X), wherein one PCIE16X is led to 1 PCIE16X slot, another PCIE16X is led to another PCIE16X slot, one PCIE4X is led to another PCIE8X slot, and 1 PCIE4X is connected with the intel corporation 82576 network card chip to generate 2 kilomega ports.
4) USB port
From the south bridge SP5100, 4 USB ports are led out, of which 2 USB ports are led into the front panel and the other 2 USB ports are led into the rear panel. The design has increased the number of USB mouth on the one hand, and on the other hand has made things convenient for user diversified operation demand.
5) Network interface card (gigabit Ethernet)
The network card utilizes an Intel82576 chip from Intel corporation to create a gigabit ethernet network. The north bridge SR5690 is led out 1 PCIE4X to be connected with intel82576 network card IC of intel company to generate 2 kilomega ports.
The design of the double gigabit network enhances the IO throughput capacity of the blade, and when one gigabit network port is broken, the other network port can be continuously used, so that the redundancy of the system is enhanced.
6) PCIE slot
This rack server has 3 PCIE slots in total:
1 PCIE16X slots;
1 PCIE16X slots
1 PCIE8X slots, and the connected signal is a PCIE4X signal, so the design is still for using a PCIE8 card;
the PCIE slot is designed uniquely, so that the applicable range of the PCIE card of the Loongson rack server is greatly expanded. Although the signal connected to the PCIE8X slot is one PCIE4X of SR5690, the PCIE8X slot is adopted in the mechanism size, so that the card of PCIE8X can be smoothly reduced to be used by PCIE4X, and the purpose of using the PCIE8X card is achieved.
PCIE bus has the characteristic of being able to reduce bandwidth usage, for example, PCIE16X can be reduced to 8X, 4X, 2X, 1X for use. The design of PCIE slots takes advantage of this feature.
7) Display card
The video card in this example is a VGA video card, which is connected to the VGA port on the rear panel as shown in fig. 1, and video signals are generated by VGA ICs connected to the south bridge SP5100PCI bus.
8) Heat dissipation system
There are 6 fans located in the area of the Loongson rack server near the front panel, with the wind direction flowing from the front panel to the back panel. Every 2 fans are in one group and placed in front and back.
The two Loongson CPUs, SR5690 and SP5100 are respectively provided with a heat radiating fin with the size suitable for the Loongson CPUs, SR5690 and SP 5100.
9) External interface (including external interface respectively arranged on the front and back panel of the cabinet)
A. The peripheral interface arranged on the front panel of the case comprises a USB interface I, a hard disk interface and a button. The USB interface I and the hard disk interface are respectively connected with the south bridge chip SP5100, and the button is connected with an upper and lower electric control circuit on the mainboard. Wherein,
6 SATA buses are led out from the south bridge chip SP5100 to a hard Disk interface of a front panel of the rack server, 6 SATA hard disks can be supported and realized in a hot plugging mode, and the RAI (Redundant Array of Independent disks) function is realized. The user can plug and play in the running process of the blade, and the operation is very convenient and flexible.
And the button is used for carrying out the operation of turning on and off the rack server.
B. The peripheral interfaces arranged on the rear panel of the case comprise a display card interface, a mouse interface, a keyboard interface, a serial port, a USB interface II and a network card interface. The display card interface is connected with the display card, the mouse interface, the keyboard interface and the serial port are respectively connected with the south bridge chip SP5100 through the I/O chip, the USB interface II is connected with the south bridge chip SP5100, and the network card interface is connected with the network card.
The management monitoring part comprises the following components:
1) temperature acquisition unit
The temperature acquisition unit is realized by arranging 6 temperature acquisition points on the main board. The distribution principle of the 6 temperature acquisition points is as follows: 2 test points T1 and T2 are arranged at the air inlet, and the principle is that the air inlet is close to the front panel as much as possible and the air inlet temperature is reflected on the two sides of the panel as truly as possible; 2 test points T5 and T6 are arranged at the air outlet of the blade, the test points are as close to the rear panel as possible, and two sides of the panel are respectively provided with one test point, so that the problem of air outlet can be reflected in principle; the largest heat-dissipating device on the board, namely 2 temperature measuring points T3 and T4 are arranged at the edge of the CPU and used for monitoring and early warning the overheating state of the CPU.
The data of these temperature measurement points are collected by a BMC (baseboard management controller) chip (using an AST2050 chip from advanced corporation), and then output to any authorized user end on the Internet through a management hundred mega network interface. The BMC IC judges whether the temperature is abnormal, controls the fan to rotate in an accelerating mode to cool down if the temperature is abnormal, and also can reduce the speed of the fan to save electric energy if the temperature is low.
2) Voltage acquisition circuit
The voltage of a power system (power system) on a rack server is introduced into BMC (baseboard management controller) for monitoring, and then the voltage is output to any authorized user end on the internet through a hundred million network management port.
3) Up-down control circuit
The power button is set on the front panel of the case, the power or shutdown command sent by the power button is transmitted to the power-on and power-off control circuit of the mainboard, and then the corresponding power or shutdown action is executed.
Another way to start and shut down is by the BMC. The BMC leads out corresponding control signal lines to the power-on and power-off control circuit of the mainboard. The user controls the BMC through managing a hundred-mega Ethernet (management RJ 45' in figure 1), and then the BMC controls the power-on and power-off control circuit of the mainboard to perform corresponding execution actions.
4) Fan control
The speed measuring signal line and the speed control signal line of the 6 fans are introduced into the BMC, the BMC can detect the rotating speeds of the 6 fans, and the rotating speeds of the fans are controlled in real time according to the detected temperatures of all temperature measuring points. If the temperature is too high, the BMC controls the fan to rotate in an accelerating mode to cool, and if the temperature is low, the BMC can also decelerate the fan to save electric energy.
5) Management control unit
The management control unit in this example adopts a BMC (baseboard management controller) chip, which is the core of the management monitoring part, and is responsible for monitoring the temperature, voltage, and rotational speed of the fan of the rack server, transmitting the temperature, voltage, and rotational speed to the remote user control end through the management hundred mega ethernet, and receiving the control of the remote user.
The Loongson 3A rack server adopts BMC IC which is AST2050 chip of advanced company, and it follows standard IPMI (Intelligent Platform Management Interface) protocol, so that the Loongson 3A rack server can be seamlessly merged into a Management system of X86 cluster which is managed by BMC, and the Management of users is facilitated.
IPMI is an open standard hardware management interface specification that defines a specific method for embedded management subsystems to communicate. IPMI information is communicated via a Baseboard Management Controller (BMC). Using low-level hardware intelligence management, rather than using an operating system for management, has two major advantages: first, this configuration allows out-of-band server management; second, the operating system does not have to be burdened with the task of transferring system state data.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the same, and the present invention is described in detail with reference to the above embodiments, and those skilled in the art should understand that: modifications and equivalents of the embodiments of the invention may occur to those skilled in the art, and such modifications and variations are intended to be included within the scope of the claims appended hereto.
Claims (9)
1. The utility model provides a rack server based on godson CPU and north bridge chip SR5690, is including setting up power, mainboard in the quick-witted case and setting up the peripheral hardware interface before the quick-witted case, on the rear panel, its characterized in that: the mainboard is provided with a Loongson CPU, a north bridge chip SR5690, a south bridge chip SP5100, a memory, a network card, a display card and a management control unit; the Loongson CPU is connected with a north bridge chip SR5690 through an HT bus, the north bridge chip is connected with a south bridge chip SP5100 through an A-Link bus, the south bridge chip is connected with a display card through a PCI bus, the north bridge chip is connected with a network card through a PCIE bus, and the management control unit transmits data through a network card interface arranged on a rear panel of the chassis.
2. The rack server of claim 1, wherein: the number of the Loongson CPUs is two, namely one Loongson CPU is a main CPU, the other Loongson CPU is a slave CPU, and the two Loongson CPUs are connected through an HT bus to form a symmetrical multiprocessing architecture.
3. The rack server of claim 1, wherein: the north bridge chip SR5690 is connected with two PCIE16X slots and one PCIE8X slot through a PCIE bus.
4. The rack server of claim 1, wherein: the management control unit adopts an AST2050 chip.
5. The rack server of claim 1, wherein: the temperature acquisition unit transmits acquired temperature data to the management control unit, and the management control unit controls the rotating speed of the fan according to the temperature data.
6. The rack server of claim 1, wherein: the main board is provided with a voltage acquisition circuit and an up-down control circuit, the voltage acquisition circuit is connected with the management control unit, and the up-down control circuit is respectively connected with the management control unit and the startup and shutdown button of the front panel of the case.
7. The rack server of claim 1, wherein: the peripheral interface arranged on the front panel of the case comprises a USB interface I, a hard disk interface and a button, wherein the USB interface I and the hard disk interface are respectively connected with the south bridge chip SP5100, and the button is connected with an upper and lower electric control circuit on the mainboard.
8. The rack server of claim 1, wherein: the peripheral interface arranged on the rear panel of the case comprises a graphics card interface, a mouse interface, a keyboard interface, a serial port, a USB interface II and a network card interface, wherein the graphics card interface is connected with the graphics card, the mouse interface, the keyboard interface and the serial port are respectively connected with a south bridge chip SP5100 through I/O chips, the USB interface II is connected with the south bridge chip SP5100, and the network card interface is connected with the network card.
9. The rack server of claim 1 or 8, wherein: the network card adopts an intel82576 chip with two gigabit network ports; the display card adopts a VGA display card.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220250255 CN202838092U (en) | 2012-05-30 | 2012-05-30 | Rack server based on loongson central processing unit (CPU) and north bridge chip SR5690 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220250255 CN202838092U (en) | 2012-05-30 | 2012-05-30 | Rack server based on loongson central processing unit (CPU) and north bridge chip SR5690 |
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| Publication Number | Publication Date |
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| CN202838092U true CN202838092U (en) | 2013-03-27 |
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| CN 201220250255 Expired - Lifetime CN202838092U (en) | 2012-05-30 | 2012-05-30 | Rack server based on loongson central processing unit (CPU) and north bridge chip SR5690 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104009874A (en) * | 2014-06-12 | 2014-08-27 | 浪潮电子信息产业股份有限公司 | Method for achieving I210 and I350 double gigabit network with managing function of main board |
| CN112699999A (en) * | 2020-12-23 | 2021-04-23 | 南京路特软件有限公司 | Intelligent inference equipment based on PCIE slot |
-
2012
- 2012-05-30 CN CN 201220250255 patent/CN202838092U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104009874A (en) * | 2014-06-12 | 2014-08-27 | 浪潮电子信息产业股份有限公司 | Method for achieving I210 and I350 double gigabit network with managing function of main board |
| CN112699999A (en) * | 2020-12-23 | 2021-04-23 | 南京路特软件有限公司 | Intelligent inference equipment based on PCIE slot |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C53 | Correction of patent of invention or patent application | ||
| CB03 | Change of inventor or designer information |
Inventor after: Wang Songyu Inventor after: Zheng Chenming Inventor after: Shao Zongyou Inventor after: Sha Chaoqun Inventor after: Li Fengwang Inventor before: Zheng Chenming Inventor before: Shao Zongyou Inventor before: Sha Chaoqun Inventor before: Li Fengwang |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: ZHENG CHENMING SHAO ZONGYOU SHA CHAOQUN LI FENGWANG TO: WANG SONGYU ZHENG CHENMING SHAO ZONGYOU SHA CHAOQUN LI FENGWANG |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130327 |