The utility model content
Problem to be solved in the utility model provides a kind of super low-power consumption RC oscillator simple in structure, and reduces the impact that output frequency is subjected to temperature and supply voltage, and then produces comparatively accurately frequency of oscillation.
The utility model is realized by following technical proposals.
A kind of interior super low-power consumption RC oscillator that the utility model is related comprises: the bias current generation module that links to each other successively, RC oscillation module and waveform-shaping module.Described bias current generation module, the mode by bootstrapping produce one with nmos pass transistor threshold voltage, bias current that resistance R is relevant; Described RC oscillation module produces cycle sawtooth waveforms and recurrent pulses, and the turnover voltage of periodicity sawtooth waveforms and the proportional routine correlation properties of electric current that the bias current generation module provides; Described waveform-shaping module carries out shaping to the recurrent pulses that the RC oscillation module produces, and generates the clock signal of 50% duty ratio.
Further, described bias current generation module comprises: a PMOS transistor MP1, the 2nd PMOS transistor MP2, the first nmos pass transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3 and resistance R.
A described PMOS transistor MP1, its source class meets power vd D, and grid binding place net7 leaks level and connects the leakage level of the first nmos pass transistor MN1, the source class of the second nmos pass transistor MN2 and the grid of the 3rd nmos pass transistor MN3;
The source class of described the 2nd PMOS transistor MP2 meets power vd D, and grid and leakage level are received the 7th node n et7 in the lump;
The source class ground connection VSS of described the first nmos pass transistor MN1, the A end of grid connecting resistance R leaks level and connects the grid of the 3rd nmos pass transistor MN3, the source class of the second nmos pass transistor MN2 and the leakage level of a PMOS transistor MP1;
The leakage level of described the second nmos pass transistor MN2 and grid are received the 7th node n et7 in the lump, and the source class of the second nmos pass transistor MN2 is received the leakage level of a PMOS transistor MP1, the leakage level of the first nmos pass transistor MN1 and the grid of the 3rd nmos pass transistor MN3;
The A end of the source class connecting resistance R of described the 3rd nmos pass transistor MN3 and the grid of the first nmos pass transistor MN1, the leakage level of the 3rd nmos pass transistor MN3 meets the 7th node n et7, and the grid of the 3rd nmos pass transistor MN3 connects the leakage level of a PMOS transistor MP1, the leakage level of the first nmos pass transistor MN1 and the source class of the second nmos pass transistor MN2.
Further, described RC oscillation module comprises: the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the 5th PMOS transistor MP5, the 6th PMOS transistor MP6, the 7th PMOS transistor MP7, the 4th nmos pass transistor MN4, the 5th nmos pass transistor MN5, the 6th nmos pass transistor MN6, the 7th nmos pass transistor MN7, the first capacitor C
1With the second capacitor C
2
The source class of described the 3rd PMOS transistor MP3 meets power vd D, and grid meets the 7th node n et7, leaks level and meets the 5th node n et5;
The source class of described the 4th PMOS transistor MP4 meets power vd D, and grid meets the 7th node n et7, leaks level and connects the source class of the 6th PMOS transistor MP6 and the source class of the 7th PMOS transistor MP7;
The source class of described the 5th PMOS transistor MP5 meets power vd D, and grid meets the 7th node n et7, leaks level and meets the 6th node n et6;
The grid of described the 6th PMOS transistor MP6 meets the first node n et1, leaks level and meets the 3rd node n et3, and the source class of the 6th PMOS transistor MP6 connects the leakage level of source class and the 4th PMOS transistor MP4 of the 7th PMOS transistor MP7;
The grid of described the 7th PMOS transistor MP7 meets the second node n et2, leaks level and meets the 4th node n et4, and the source class of the 7th PMOS transistor MP7 connects the leakage level of source class and the 4th PMOS transistor MP4 of the 6th PMOS transistor MP6;
The source class ground connection VSS of described the 4th nmos pass transistor MN4, grid meets the 3rd node n et3, leaks level and meets the 5th node n et5;
The source class ground connection VSS of described the 5th nmos pass transistor MN5 leaks level and meets the 3rd node n et3, and grid meets the first node n et1;
The source class ground connection VSS of described the 6th nmos pass transistor MN6 leaks level and meets the 4th node n et4, and grid meets the second node n et2;
The source class ground connection VSS of described the 7th nmos pass transistor MN7, grid binding place net4 leaks level and meets the 6th node n et6;
Described the first capacitor C
1Positive plate meet the 3rd node n et3, negative plate ground connection VSS;
Described the second capacitor C
2Positive plate meet the 4th node n et4, negative plate ground connection VSS.
Further, described waveform-shaping module comprises: the first NAND gate nand1, the second NAND gate nand2, the first inverter inv1, the second inverter inv2 and the 3rd inverter inv3;
Described the 5th node n et5 connects the A input of the first NAND gate nand1, and described the 6th node n et6 connects the B input of the second NAND gate nand2;
The output Y of described the second NAND gate nand2 connects the B input of the first NAND gate nand1 and the input of the 3rd inverter inv3, and the nand1 of the first NAND gate output Y connects the A input of nand2 of the second NAND gate and the input of the first inverter inv1;
The output of the first inverter inv1 meets the second inverter inv2 by the second node n et2, and the second inverter inv2 is by the first node n et1 output;
Described the 3rd inverter inv3 is by the output VOUT square-wave signal of LCK node output RC oscillator.
The beneficial effects of the utility model are: simple, the used device of circuit structure is few, power consumption is extremely low, precision is high, output frequency is subjected to power supply and temperature effect is little, original frequency is easily regulated.
Embodiment
As shown in Figure 1, be the concrete connected mode of circuit of the present invention, RC oscillator in this sheet comprises the bias current generation module 10 that links to each other successively, RC oscillation module 20 and waveform-shaping module 30, and the below describes respectively the structure annexation of three modules.
Bias current generation module 10 comprises: a PMOS transistor MP1, the 2nd PMOS transistor MP2, the first nmos pass transistor MN1, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3 and resistance R;
The grid of the grid of the one PMOS transistor MP1, the 2nd PMOS transistor MP2 and leak the leakage level of level, the second nmos pass transistor MN2 and grid, they have defined the 7th node n et7 jointly.The source class of the one PMOS transistor MP1 meets power vd D, the grid binding place net7 of the one PMOS transistor MP1, the leakage level of a PMOS transistor MP1 connects the leakage level of the first nmos pass transistor MN1, the source class of the second nmos pass transistor MN2 and the grid of the 3rd nmos pass transistor MN3;
The source class of the 2nd PMOS transistor MP2 meets power vd D, and the grid of the 2nd PMOS transistor MP2 and leakage level are received the 7th node n et7 in the lump;
The source class ground connection VSS of the first nmos pass transistor MN1, the A end of the grid connecting resistance R of the first nmos pass transistor MN1, the leakage level of the first nmos pass transistor MN1 connects the leakage level of source class and the PMOS transistor MP1 of the grid of the 3rd nmos pass transistor MN3, the second nmos pass transistor MN2;
The leakage level of the second nmos pass transistor MN2 and grid are received the 7th node n et7 in the lump, and the source class of the second nmos pass transistor MN2 is received the leakage level of a PMOS transistor MP1, the leakage level of the first nmos pass transistor MN1 and the grid of the 3rd nmos pass transistor MN3;
The A end of the source class connecting resistance R of the 3rd nmos pass transistor MN3 and the grid of the first nmos pass transistor MN1, the leakage level of the 3rd nmos pass transistor MN3 meets the 7th node n et7, and the grid of the 3rd nmos pass transistor MN3 connects the leakage level of a PMOS transistor MP1, the leakage level of the first nmos pass transistor MN1 and the source class of the second nmos pass transistor MN2.
The bias current generation module, the gate source voltage of the first nmos pass transistor (MN1) by wherein and resistance (R) produce a bias current i in the mode of bootstrapping
a
RC oscillation module 20 comprises: the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the 5th PMOS transistor MP5, the 6th PMOS transistor MP6, the 7th PMOS transistor MP7, the 4th nmos pass transistor MN4, the 5th nmos pass transistor MN5, the 6th nmos pass transistor MN6, the 7th nmos pass transistor MN7, the first capacitor C
1With the second capacitor C
2
The leakage level of the leakage level of the 3rd PMOS transistor MP3 and the 4th nmos pass transistor MN4 has defined the 5th node n et5 jointly.The leakage level of the leakage level of the 5th PMOS transistor MP5 and the 7th nmos pass transistor MN7 has defined the 6th node n et6 jointly.The grid of the 6th PMOS transistor MP6 and the grid of the 5th nmos pass transistor MN5 have defined the first node n et1 jointly.The grid of the 7th PMOS transistor MP7 and the grid of the 6th nmos pass transistor MN6 have defined the second node n et2 jointly.The leakage level of the leakage level of the 6th PMOS transistor MP6, the 5th nmos pass transistor MN5, the grid of the 4th nmos pass transistor MN4, the first capacitor C
1Positive plate jointly defined node net3.The leakage level of the leakage level of the 7th PMOS transistor MP7, the 6th nmos pass transistor MN6, the grid of the 7th nmos pass transistor MN7, the second capacitor C
2Positive plate jointly defined the 4th node n et4.
The source class of the 3rd PMOS transistor MP3 meets power vd D, and grid meets the 7th node n et7, leaks level and meets the 5th node n et5;
The source class of the 4th PMOS transistor MP4 meets power vd D, and the grid of the 4th PMOS transistor MP4 meets the 7th node n et7, and the leakage level of the 4th PMOS transistor MP4 connects the source class of the 6th PMOS transistor MP6 and the source class of the 7th PMOS transistor MP7;
The source class of the 5th PMOS transistor MP5 meets power vd D, and the grid of the 5th PMOS transistor MP5 meets the 7th node n et7, and the leakage level of the 5th PMOS transistor MP5 meets the 6th node n et6;
The grid of the 6th PMOS transistor MP6 meets the first node n et1, and the leakage level of the 6th PMOS transistor MP6 meets the 3rd node n et3, and the source class of the 6th PMOS transistor MP6 connects the leakage level of source class and the 4th PMOS transistor MP4 of the 7th PMOS transistor (MP7);
The grid of the 7th PMOS transistor MP7 meets the second node n et2, and the leakage level of the 7th PMOS transistor MP7 meets the 4th node n et4, and the source class of the 7th PMOS transistor MP7 connects the leakage level of source class and the 4th PMOS transistor MP4 of the 6th PMOS transistor MP6;
The source class ground connection VSS of the 4th nmos pass transistor MN4, the grid of the 4th nmos pass transistor MN4 meets the 3rd node n et3, and the leakage level of the 4th nmos pass transistor MN4 meets the 5th node n et5;
The source class ground connection VSS of the 5th nmos pass transistor MN5, the leakage level of the 5th nmos pass transistor MN5 meets the 3rd node n et3, and the grid of the 5th nmos pass transistor MN5 meets the first node n et1;
The source class ground connection VSS of the 6th nmos pass transistor MN6, the leakage level of the 6th nmos pass transistor MN6 meets the 4th node n et4, and the grid of the 6th nmos pass transistor MN6 meets the second node n et2;
The source class ground connection VSS of the 7th nmos pass transistor MN7, the grid binding place net4 of the 7th nmos pass transistor MN7, the leakage level of the 7th nmos pass transistor MN7 meets the 6th node n et6;
The first capacitor C
1Positive plate meet the 3rd node n et3, negative plate ground connection VSS; Described the second capacitor C
2Positive plate meet the 4th node n et4, negative plate ground connection VSS.
The RC oscillation module produces periodically sawtooth waveforms at the 3rd node n et3 and the 4th node n et4 place, produces recurrent pulses at the 5th node n et5 and the 6th net6 place.
Waveform-shaping module 30 comprises: the first NAND gate nand1, the second NAND gate nand2, the first inverter inv1, the second inverter inv2 and the 3rd inverter inv3;
The 5th node n et5 connects the A input of the first NAND gate nand1, and described the 6th node n et6 connects the B input of the second NAND gate nand2;
The output Y of the second NAND gate nand2 connects the B input of the first NAND gate nand1 and the input of the 3rd inverter inv3, and the nand1 of the first NAND gate output Y connects the A input of nand2 of the second NAND gate and the input of the first inverter inv1;
The output of the first inverter inv1 meets the second inverter inv2 by the second node n et2, and the second inverter inv2 is by the first node n et1 output;
The 3rd inverter inv3 is by the output VOUT square-wave signal of LCK node output RC oscillator.
The output of the 3rd inverter inv3 has defined the output VOUT of RC oscillator.Waveform-shaping module produces recurrent pulses with the 5th node n et5 and the 6th node n et6 place, and the exhibition that is converted to is empty than the square-wave signal that is 50%.
Below will specifically describe the operation principle of circuit.
The first nmos pass transistor MN1 of bias current generation module 10 and resistance R produce a bias current i by the mode of bootstrapping
a, this structure bootstrap current benchmark that is otherwise known as.i
aSize and the threshold voltage vt h of the first nmos pass transistor MN1
MN1Relevant with resistance R, i
aCurrent expression be:
Because the electric current that the first nmos pass transistor MN1 flows through is minimum, so can think the gate source voltage Vgs of the first nmos pass transistor MN1
MN1Be approximately equal to its threshold voltage vt h
MN1, then:
Vgs
MN1≈Vth
MN1
i
aCurrent expression can be modified to:
The breadth length ratio of a PMOS transistor PM1, the 2nd PMOS transistor PM2, the 3rd PMOS transistor PM3, the 4th PMOS transistor PM4, the 5th PMOS transistor PM5 is consistent in the schematic diagram of RC oscillator, then:
i
a=i
b=i
c=i
d=i
e
The 6th PMOS transistor PM6 and the 5th nmos pass transistor NM5 are as the first capacitor C
1Charge and discharge switch, the first node n et1 is as discharging and recharging control end, the first capacitor C when the voltage V_net1 of the first node n et1 is low level
1Charging, the first capacitor C when the voltage V_net1 of first node net1 is high level
1Discharge.The 7th PMOS transistor PM7 and the 6th nmos pass transistor NM6 are as the second capacitor C
2Charge and discharge switch, the second node n et2 is as discharging and recharging control end, the second capacitor C when the voltage V_net2 of the second node n et2 is low level
2Charging, the second capacitor C when the voltage V_net2 of the second node n et2 is high level
2Discharge.Because the voltage-phase of the first node n et1 and the second node n et2 is just in time opposite, then the first capacitor C
1With the second capacitor C
2Hocket and discharge and recharge.
When the voltage V_net2 of the second node n et2 was high level, the voltage V_net1 of the first node n et1 was low level, at this moment the first capacitor C
1Charging, the second capacitor C
2The charging path is turned off and top crown ground connection.The first capacitor C
1The top crown i.e. voltage V_net3 of the 3rd node n et3 begins to rise from 0V, rises to the threshold voltage vt h of the 4th nmos pass transistor MN4 when V_net3 voltage
MN4When neighbouring, the 4th nmos pass transistor MN4 conducting, the voltage V_net5 of the 5th node n et5 can be pulled to low level, because the second capacitor C
2The charging path is turned off and top crown ground connection, and then the current potential of the voltage V_net6 of the 6th node n et6 is high level.In waveform-shaping module, the first not gate nand1 and the second NAND gate nand2 consist of the RC trigger that a low-voltage triggers.V_net6 is high level, when V_net5 by high level during to low transition, the current potential V_net2 of the second node n et2 can be set to low level, the current potential V_net1 of the first node n et1 can be set to high level, so the first capacitor C
1Charging process finishes, and top crown discharges over the ground, simultaneously the second capacitor C
2Enter charging process.The first capacitor C within the extremely short time
1Finish discharge, the first capacitor C
1Top crown voltage V_net3 is pulled to low level, and the current potential V_net5 of the 5th node n et5 is high level by low transition within the extremely short time.
The first capacitor C
1Charging process finishes, the second capacitor C
2Begin charging, this moment, the current potential of V_net2 was low level, and the current potential of V_net1 is high level.The second capacitor C
2Begin charging by 0V, rise to the threshold voltage vt h of the 7th nmos pass transistor MN7 when the voltage of V_net4
MN7When neighbouring, the 7th nmos pass transistor MN7 conducting, the voltage V_net6 of the 6th node n et6 can be pulled to low level.Because the second capacitor C
1The charging path is turned off and top crown ground connection, and then the current potential of the voltage V_net5 of the 5th node n et5 is high level.
In waveform-shaping module, V_net5 is high level, when V_net6 by high level during to low transition, the voltage V_net2 of the second node n et2 can be set to high level, the voltage V_net1 of the first node n et1 can be set to low level.So the second capacitor C
2Charging process finishes, and top crown discharges over the ground, simultaneously the first capacitor C
1Again enter charging process.The first capacitor C within the extremely short time
2Finish discharge, the first capacitor C
2Top crown voltage V_net4 is pulled to low level, and the voltage V_net6 of the 6th node n et6 is high level by low transition within the extreme time.
The voltage waveform V_net4 of the voltage waveform V_net3 of the 3rd node n et3 and the 4th node n et4 is the periodicity sawtooth waveforms in the RC oscillation module, and the voltage waveform V_net6 of the voltage waveform V_net5 of the 5th node net5 and the 6th node net6 is cyclic pulse signal.The waveform of V_net3, V_net4, V_net35, V_net6 is seen Fig. 2.
The first capacitor C in the RC oscillation module
1With the second capacitor C
2Alternately charging has formed periodically sawtooth waveforms and recurrent pulses, and waveform-shaping module carries out shaping to the recurrent pulses that the RC oscillation module produces, and generates the CLK clock signal of 50% duty ratio.The voltage waveform V_net1 of the first node n et1, the voltage waveform V_net2 of the second node n et2, the voltage waveform of CLK is seen Fig. 2.
The breadth length ratio of the first nmos pass transistor MN1, the 4th nmos pass transistor MN4, the 7th nmos pass transistor MN7 is identical, again because the electric current that flows through of the first nmos pass transistor MN1 is minimum, so can think the gate source voltage Vgs of the first nmos pass transistor MN1
MN1Be approximately equal to its threshold voltage vt h
MN1, then:
Vgs
MN1=Vth
MN1=Vth
MN4=Vth
MN7
The first capacitor C
1With the second capacitor C
2Appearance be worth identical the 4th PMOS pipe PM4 and provide charging current i as current source for these two electric capacity
dThe first capacitor C
1The time of the sawtooth waveform that charging produces is T
1, the second capacitor C
2The time of the sawtooth waveform that charging produces is T
2, then:
The first capacitor C
1Fill the first capacitor C
1With the second capacitor C
2Capacitor's capacity equate:
C
1=C
2
In the RC oscillation module, the turnover voltage of sawtooth waveforms is the threshold voltage vt h of the 4th nmos pass transistor MN4
MN4, capacitor C
1Charging current i
dBe Vgs
MN1/ R, i
dWith Vth
MN4Show the direct proportion correlation properties, therefore calculating T
1Expression formula in the molecule amount relevant with the proportional example of denominator divided out T
1Final expression formula only with resistance R and capacitor C
1Relevant.
The one-period of output clock CLK is by a T
1With a T
2Form, and the first capacitor C
1With the second capacitor C
2The appearance value be again identical, then:
T
1=T
2
The first capacitor C
1With the second capacitor C
2Alternately charging, and T
1And T
2Equate that then the duty ratio of the voltage V_net1 of node n et1 is that the duty ratio of 50%, CLK is similarly 50%.The cycle of CLK is:
T=T
1+T
2=2RC
1
The frequency of CLK is:
The output frequency f of CLK and independent of power voltage only with resistance R and capacitor C
1Relevant.The temperature coefficient of CLK and resistance R and capacitor C
1Relevant, electric capacity has extremely low temperature coefficient in the integrated circuit technology, and the topmost factor that therefore affects RC oscillator output frequency temperature coefficient is exactly the temperature coefficient of resistance.For the low-temperature coefficient characteristic that realizes output frequency can realize by two kinds of approach: (one) can directly use this resistance if technique provides the resistance of low-temperature coefficient.(2) if technique does not provide low-temperature coefficient resistance, then can be by negative temperature coefficient resister and positive temperature coefficient resistor be connected to realize equivalent low-temperature coefficient characteristic.Because the RC oscillator original frequency deviation that production technology causes can be calibrated by resistance R is trimmed.The related interior super low-power consumption RC oscillator of sheet of the utility model is verified by flow, and large-scale production.For the output frequency below the 500k, oscillator power consumption can be controlled in the 2uA, if use proper resistor, in-25-75 ℃ temperature range, under the condition of mains fluctuations ± 20%, the frequency shift (FS) that supply voltage and temperature cause jointly can be controlled in ± 2% in.
The above only is the utility model preferred embodiment; so it is not to limit scope of the present utility model; the personnel of any book palpus the technology; within not breaking away from spirit and scope of the present utility model; can do on this basis further improvement and variation, because the scope that claims were defined that protection range of the present utility model is worked as with the application is as the criterion.