CN202713522U - Optical transmitter and receiver chip structure using reverse direction clock synchronization networking - Google Patents
Optical transmitter and receiver chip structure using reverse direction clock synchronization networking Download PDFInfo
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- CN202713522U CN202713522U CN 201220274785 CN201220274785U CN202713522U CN 202713522 U CN202713522 U CN 202713522U CN 201220274785 CN201220274785 CN 201220274785 CN 201220274785 U CN201220274785 U CN 201220274785U CN 202713522 U CN202713522 U CN 202713522U
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Abstract
The utility model provides an optical transmitter and receiver chip structure using reverse direction clock synchronization networking, being able to realize clock synchronization among a plurality of chips so as to realize gathering of the data among the plurality of chips, to guarantee the digital sampling of the digital gathering, and to make signal transmission complete. The optical transmitter and receiver chip structure using reverse direction clock synchronization networking comprises a digital to analog converter, an analog to digital converter, a digital logic module, a deserializer, and a clock signal module. The optical transmitter and receiver chip structure using reverse direction clock synchronization networking is characterized by also including a clock recovery circuit, a local/remote clock selector switch, and a serializer, wherein the output end of the digital to analog converter is externally connected with an analog video output; an analog video input is connected with the input end of the analog-to-digital converter; the output end of the analog-to-digital converter is connected with the input end of the digital logic module; the output end of the digital logic module is connected with the input end of the serializer; and the output end of the serializer is externally connected with an optical fiber module through a data line.
Description
Technical field
The utility model relates to the technical field of structures of optical transceiver, is specially a kind of optical transceiver chip structure that utilizes reverse clock synchronous networking.
Background technology
Digital video fiber optic transmitter is because its transmission data volume is large, and the characteristics without transmitting loss and delay obtain a wide range of applications in protection and monitor field in recent years.
On the other hand, integrated circuit technique has obtained faster development in recent years along with the progress of technique.Take deep-submicron CMOS process as the basis, the ic core chip technology can be integrated with the major function of video optical multiplexer at present, and the digital video fiber optic transmitter take this integrated chip as the basis is all having greater advantage than traditional product aspect power consumption, the volume.
Existing Digital Optical Terminal chipset structure is seen Fig. 1, draw and explanation in order to simplify, what draw here is the single channel digital video fiber optic transmitter, 2 ~ 16 tunnel situation can appear in the practical application, but basic principle is consistent, it comprises the transmitting terminal chip, the receiving terminal chip, the transmitting terminal chip connects the receiving terminal chip by optical fiber, the transmitting terminal chip comprises analog to digital converter, CPLD/ or FPGA, deserializer, send optic module, local clock, the data input of transmitting terminal is through analog to digital converter, CPLD/ or FPGA, import the transmission optic module after the deserializer into, transmitting terminal connect analog to digital converter, CPLD/ or FPGA, the input end of clock of deserializer connects respectively local clock, data are finally delivered to the optic module of receiving terminal chip via optical fiber transmission by sending optic module, the local clock maintenance of receiving terminal chip is consistent with the frequency of the local clock of transmitting terminal chip, thereby receiving circuit relies on the clock frequency identical with tranmitting data register, synchrodata receives, and finish recovery and the processing of data, the receiving terminal chip specifically comprises optic module, deserializer, CPLD/ or FPGA, digital to analog converter, local clock, the optic module of receiving terminal chip is accepted to pass successively to deserializer after the data, CPLD/ or FPGA, digital to analog converter, digital to analog converter leads to the data input of receiving terminal, and the local clock of receiving terminal chip connects respectively deserializer, CPLD/ or FPGA, the clock input interface of digital to analog converter.
Said chip group structure is when processing single point-to-point transmission, because both sides' local clock frequency can be consistent substantially, in the situation that certain error rate, basic guarantee data send and receive end synchronously, but be accompanied by the extensive use of digital video fiber optic transmitter in safety monitoring, generally be the corresponding receiving terminals of a plurality of transmitting terminals now, a pair of digital video fiber optic transmitter must take an optical fiber, its data traffic is much smaller than fiber capacity, the traffic of simple optical fiber is dwindled greatly, when the simultaneously corresponding receiving terminal of a plurality of transmitting terminals, need to draw separately an optical fiber from each transmitting terminal and lead to receiving terminal, and the existing line number of fibers can't satisfy a large amount of digital video fiber optic transmitters to the demand of optical fiber.
Along with the extensive use of digital video fiber optic transmitter in safety monitoring, the point-to-point transmission exposed day by day under the conventional video optical transceiver framework goes out the not high shortcoming of its fiber resource utilance:
On the one hand, a pair of digital video fiber optic transmitter takies an optical fiber, and its data traffic is much smaller than the optical fiber heap(ed) capacity.The accurate definition vision signal of normal road sign code check is less than 150Mbps, and fiber capacity commonly used is that they are more than ten times in the Gbps magnitude;
On the other hand, often running into optical fibre frame during engineering is used is set as high, or because various restrictions can't be constructed (as: can not allow railway end operation constructs), can only rent existing line, and the existing line number of fibers can't satisfy a large amount of digital video fiber optic transmitters to the demand of optical fiber.
Engineering merchant is forced to seeking solution, is as shown in Figure 2 common " many to list " schemes, that is: a plurality of transmitting terminals are shared an optical fiber to single receiving terminal.Thereby effectively utilize fiber resource, reduce the demand of erecting optical cables.Abovely a plurality of transmitting terminal data are pooled to a process on the optical fiber just are called " converging ".
In order to achieve the above object, just must change traditional point-to-point transmission means, generally can adopt at present following two kinds of methods to finish aggregation feature:
1) uses wavelength-division multiplex technique, utilize complicated and expensive wavelength division multiplex device, realize converging and transmitting of multichannel data at single fiber optic cable.Be actually in the optics aspect and realize signal gathering;
2) adopt various circuit arrangements to realize converging of optical transceiver signal, that is: settling signal converges in signal of telecommunication category.This method can be subdivided into the Digital and analog solution again:
A) analogy method is by converting signal to analog quantity, and then is converted to digital quantity, and realizes signal gathering.The shortcoming of this method is that signal has than lossy in conversion, and needs extra digital-to-analogue/modulus switching device, has increased cost;
B) in contrast to simulation and converge, the zero loss that can reach signal of Digital convergence, the extra digital circuit cost that increases is very low, substantially can ignore.But the major obstacle of at present Digital convergence realization is the synchronous of unlike signal source: take Fig. 2 as example, although the crystal oscillator nominal of four transmitting terminal uses is consistent, owing to being separately local clock and discrete device, clock frequency there are differences.Lose code and error code phenomenon in the Digital convergence process, thereby impact transmits Signal integrity.This situation is difficult to carry out digital sample when causing under the existing scheme transmitting terminal convergence, so the data that converge each transmitting terminal with present framework in numeric field are still had any problem.
Summary of the invention
For the problems referred to above, the utility model provides a kind of optical transceiver chip structure that utilizes reverse clock synchronous networking, and it can carry out clock synchronous at a plurality of chip chambers, thereby can realize converging of data between multi-chip, guarantee the digital sample of Digital convergence, so that transmit signal integrity.
A kind of optical transceiver chip structure that utilizes reverse clock synchronous networking, its technical scheme is such: it comprises digital to analog converter, analog to digital converter, digital logic module, deserializer, the clock signal module, it is characterized in that: it also comprises clock recovery circuitry, this locality/far-end clock selecting switch, parallel-to-serial converter, the external analog video output of the output of described digital to analog converter, the analog video input connects the input of described analog to digital converter, the output of described analog to digital converter connects the input of described digital logic module, described digital logic module output connects the input of described parallel-to-serial converter, the output of described parallel-to-serial converter is by the external optic module of data wire, outside described optic module connects the input of described deserializer by data wire, the output of described deserializer connects another input of described digital logic module, another output of described digital logic module connects the input of described digital to analog converter, described clock signal module is connected with described this locality/far-end clock selecting switch, two selecting sides of described this locality/far-end clock selecting switch are: the described clock recovery circuitry of chip internal, outside local clock, the clock signal data communication device of described optic module is crossed data wire and is connected described clock recovery module.
It is further characterized in that: described digital logic module is specially CPLD/ or FPGA.
After adopting said structure, the optical transceiver chip structure possesses data send and receive function simultaneously, guarantees that optical transceiver transmitting terminal and receiving terminal use same chips, simplifies the optical transceiver system capable design; Compare such variation guarantees keeping optical transceiver system capable transmitting terminal and receiving terminal to use respectively beyond the conventional operation mode of local clock with traditional optical transceiver framework, the technical program also can access the local clock signal at receiving terminal, and send to the optical transceiver transmitting terminal of far-end by optical fiber, by clock recovery circuitry clock recovery is out supplied data acquisition in the chip at transmitting terminal, follow-up digital processing and transtation mission circuit use, and receive thereby reached in the digital video fiber optic transmitter network, transmitting terminal, and potential a plurality of transmitting terminals, the common purpose of using same clock sampling and transmitting data.In its actual use, can input high/low level or I by chip pin
2The mode of C bus control bit comes choice for use local clock or inner clock recovery circuitry to recover the far-end clock, thereby can work in the mode of tradition or the technical program description respectively, to satisfy different clients' demand; To sum up, this chip structure can carry out clock synchronous by clock recovery circuitry at a plurality of chip chambers, thereby can realize converging of data between multi-chip, guarantees the digital sample of Digital convergence, so that transmit signal integrity.
Description of drawings
Fig. 1 is existing Digital Optical Terminal chipset structural representation block diagram;
Fig. 2 is the networking structure schematic diagram of the corresponding receiving terminal of four transmitting terminals;
Fig. 3 is structural representation block diagram of the present utility model;
Fig. 4 is the structured flowchart of the concrete specific embodiment one of using of the utility model;
Fig. 5 is the structured flowchart of the concrete specific embodiment two of using of the utility model;
Fig. 6 is the structured flowchart of the concrete specific embodiment three of using of the utility model.
Embodiment
A kind of optical transceiver chip structure that utilizes reverse clock synchronous networking, see Fig. 3: it comprises digital to analog converter, analog to digital converter, digital logic module, deserializer, the clock signal module, it also comprises clock recovery circuitry, this locality/far-end clock selecting switch, parallel-to-serial converter, the external analog video output of the output of digital to analog converter, the input of analog video input connection mode number converter, the output of analog to digital converter connects the input of digital logic module, the digital logic module output connects the input of parallel-to-serial converter, the output of parallel-to-serial converter is by the external optic module of data wire, the external fiber module connects the input of deserializer by data wire, the output of deserializer connects another input of digital logic module, the input of another output linking number weighted-voltage D/A converter of digital logic module, the clock signal module is connected with this locality/far-end clock selecting switch, two selecting sides of this locality/far-end clock selecting switch are: the clock recovery circuitry of chip internal, outside local clock, the clock signal data communication device of optic module are crossed data wire and are connected clock recovery module.Digital logic module is specially CPLD/ or FPGA.
Concrete Application Example one:
See Fig. 4, four corresponding receiving terminals of transmitting terminal: the pool side is arranged separately, the data communication device of four transmitting terminals is crossed the short distance optical fiber transmission and is delivered to the pool side, the pool side connects receiving terminal by single-path optical fiber, wherein chip structure of the present utility model is all adopted in four transmitting terminals, a pool side, this locality of the clock signal module of four transmitting terminals/far-end clock selecting switch connects the local clock of the outside of its correspondence, and this locality of the clock signal module of a pool side/far-end clock selecting switch connects the clock recovery circuitry of its chip internal.
Concrete Application Example two:
See Fig. 5, four corresponding receiving terminals of transmitting terminal: the pool side is integrated in one of them transmitting terminal, four transmitting terminals all adopt chip structure of the present utility model, wherein three not the transmitting terminal of integrated pool side connect respectively the transmitting terminal of integrated pool side, the transmitting terminal that has the pool side function concurrently is connected to receiving terminal by single-path optical fiber, three not this locality of the clock signal module of the transmitting terminal of integrated pool side/far-end clock selecting switch connect the local clock of the outside of its correspondence, this locality of the transmitting terminal of integrated pool side its clock signaling module when existing as the pool side/far-end clock selecting switch connects the clock recovery circuitry of its chip internal; This locality of the transmitting terminal of integrated pool side its clock signaling module when existing as transmitting terminal/far-end clock selecting switch connects the local clock of the outside of its correspondence.
Concrete Application Example three:
See Fig. 6, three corresponding receiving terminals of transmitting terminal: the output of three transmitting terminals is connected serially to the input of next transmitting terminal separately by single-path optical fiber, the output of the 3rd transmitting terminal connects receiving terminal by single-path optical fiber, this locality of the clock signal module of first transmitting terminal/far-end clock selecting switch connects the local clock of the outside of its correspondence, second, the 3rd transmitting terminal be the double function of doing the pool side all, therefore this locality of its clock signaling module when existing as the pool side/far-end clock selecting switch connects the clock recovery circuitry of its chip internal, this locality of its clock signaling module when existing as transmitting terminal/far-end clock selecting switch connects the local clock of the outside of its correspondence.
Above three concrete Application Examples all only need by the single-path optical fiber networking, and quantities is little, receiving terminal in three concrete Application Examples adopts chip structure of the present utility model, and this locality of its clock signaling module/far-end clock selecting switch connects the clock recovery circuitry of its chip internal.
Wherein, the Chinese implication of CPLD/ or FPGA: CPLD is CPLD; FPGA is field programmable gate array.
Claims (2)
1. optical transceiver chip structure that utilizes reverse clock synchronous networking, it comprises digital to analog converter, analog to digital converter, digital logic module, deserializer, the clock signal module, it is characterized in that: it also comprises clock recovery circuitry, this locality/far-end clock selecting switch, parallel-to-serial converter, the external analog video output of the output of described digital to analog converter, the analog video input connects the input of described analog to digital converter, the output of described analog to digital converter connects the input of described digital logic module, described digital logic module output connects the input of described parallel-to-serial converter, the output of described parallel-to-serial converter is by the external optic module of data wire, outside described optic module connects the input of described deserializer by data wire, the output of described deserializer connects another input of described digital logic module, another output of described digital logic module connects the input of described digital to analog converter, described clock signal module is connected with described this locality/far-end clock selecting switch, two selecting sides of described this locality/far-end clock selecting switch are: the described clock recovery circuitry of chip internal, outside local clock, the clock signal data communication device of described optic module is crossed data wire and is connected described clock recovery module.
2. a kind of optical transceiver chip structure that utilizes reverse clock synchronous networking according to claim 1, it is characterized in that: described digital logic module is specially CPLD/ or FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220274785 CN202713522U (en) | 2012-06-12 | 2012-06-12 | Optical transmitter and receiver chip structure using reverse direction clock synchronization networking |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220274785 CN202713522U (en) | 2012-06-12 | 2012-06-12 | Optical transmitter and receiver chip structure using reverse direction clock synchronization networking |
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| CN202713522U true CN202713522U (en) | 2013-01-30 |
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| CN 201220274785 Withdrawn - After Issue CN202713522U (en) | 2012-06-12 | 2012-06-12 | Optical transmitter and receiver chip structure using reverse direction clock synchronization networking |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102740062A (en) * | 2012-06-12 | 2012-10-17 | 无锡思泰迪半导体有限公司 | Optical transmitter and receiver chip structure for synchronously networking by using reverse clock |
-
2012
- 2012-06-12 CN CN 201220274785 patent/CN202713522U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102740062A (en) * | 2012-06-12 | 2012-10-17 | 无锡思泰迪半导体有限公司 | Optical transmitter and receiver chip structure for synchronously networking by using reverse clock |
| CN102740062B (en) * | 2012-06-12 | 2014-09-03 | 无锡思泰迪半导体有限公司 | Optical transmitter and receiver chip structure for synchronously networking by using reverse clock |
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| C14 | Grant of patent or utility model | ||
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| AV01 | Patent right actively abandoned |
Granted publication date: 20130130 Effective date of abandoning: 20140903 |
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| RGAV | Abandon patent right to avoid regrant |