CN202661759U - 一种像素结构、双栅像素结构及显示装置 - Google Patents

一种像素结构、双栅像素结构及显示装置 Download PDF

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CN202661759U
CN202661759U CN2012202246426U CN201220224642U CN202661759U CN 202661759 U CN202661759 U CN 202661759U CN 2012202246426 U CN2012202246426 U CN 2012202246426U CN 201220224642 U CN201220224642 U CN 201220224642U CN 202661759 U CN202661759 U CN 202661759U
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pixel electrode
lower floor
dot structure
electrode
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王世君
薛海林
车春城
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BOE Technology Group Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本实用新型公开了一种像素结构、双栅像素结构及显示装置，方案为：采用上下两层像素电极层来与公共电压线形成存储电容，增大像素电极层与公共电压线之间的交叠面积，其中下层像素电极和公共电压线之间只有栅极绝缘层，上层像素电极和公共电压线之间只有绝缘层，两层像素电极和公共电压线之间的距离减小，由于像素电极和公共电压线之间的中间层厚度减小且交叠面积增加，因而可以增大存储电容。在存储电容的容量一定的情况下，采用本实用新型的技术方案，可以减小公共电压线的宽度，从而有效的增加开口率。

Description

一种像素结构、双栅像素结构及显示装置
技术领域
本实用新型涉及显示技术，尤其涉及一种像素结构、双栅(Dual Gate)像素结构及显示装置。 
背景技术
液晶显示器中有一个很重要的性能指标就是亮度，而决定亮度最重要的因素就是开口率，开口率是指一个像素的有效透光区域占整个像素全部面积的比例。 
目前手机产品的分辨率越来越高，像素尺寸(Pixel pitch)越来越小，扭曲向列(Twisted Nematic，TN)型产品的开口率成为了一个瓶颈，而且TN型产品为防止闪烁(flicker)的产生，必须保证存储电容Cst的大小，因此开口率受到了很大的限制，而对于双栅液晶面板来说，开口率则更低。 
图1为传统的TN型液晶面板的像素结构示意图，其中像素电极7与公共电压线8(Vcom)之间有绝缘层5(PVX)和栅极绝缘层6(GI)两层绝缘层，为保证存储电容Cst必须有较大的正对面积，这样需要将公共电压线8(Vcom)的面积做的比较大，然而公共电压线8(Vcom)的面积增大后，会使开口率降低。 
实用新型内容
有鉴于此，本实用新型的主要目的在于提供一种像素结构、双栅像素结构及显示装置，用于解决传统的双栅像素结构的开口率低的技术问题。 
为达到上述目的，本实用新型的技术方案是这样实现的： 
一种像素结构，包括： 
栅极； 
下层像素电极，与栅极位于同一层； 
栅极绝缘层，覆盖于栅极和下层像素电极之上； 
源极； 
漏极； 
绝缘层，覆盖于源极和漏极之上； 
上层像素电极，与漏极和下层像素电极电性相连； 
半导体层，位于栅极绝缘层之上，位于源极、漏极之下，连接源极和漏极； 
公共电压线，位于上层像素电极与下层像素电极之间，上层像素电极和下层像素电极与所述公共电压线形成存储电容Cst。 
较佳地，所述上层像素电极与所述下层像素电极的正对面积相同。 
较佳地，所述上层像素电极与所述下层像素电极通过过孔电性相连。 
较佳地，所述公共电压线在垂直方向上与所述上层像素电极和所述下层像素电极的部分面积交叠。 
较佳地，所述公共电压线与所述源极和所述漏极由同一层金属层形成。 
较佳地，所述上层像素电极与所述公共电压线之间只有绝缘层；所述下层像素电极与所述公共电压线之间只有栅极绝缘层。 
一种双栅像素结构，该双栅像素结构中的每个像素结构由任一上述的两个像素结构构成。 
一种显示装置，该显示装置包括任一上述的像素结构。 
本实用新型采用上下两层像素电极层来与公共电压线形成存储电容，增大像素电极层与公共电压线之间的交叠面积，其中下层像素电极和公共电压线之间只有栅极绝缘层，上层像素电极和公共电压线之间只有绝缘层，两层像素电极和公共电压线之间的距离减小，由于像素电极和公共电压线之间的中间层厚度减小且交叠面积增加，因而可以增大存储电容。在存储电容的容量一定的情况下，采用本实用新型的技术方案，可以减小公共电压线的宽度，从而有效的增加开口率。 
附图说明
图1为传统扭曲向列型双栅像素结构示意图； 
图2为采用本实用新型实施例提供的像素结构的液晶面板的俯视图； 
图3为本实用新型实施例提供的沿图2的切割线AB切割后的像素结构示意图； 
图4为本实用新型实施例提供的沿图2的切割线CD切割后的像素结构示意图； 
1-栅极；2-源极；3-漏极；4-半导体层；5-绝缘层； 
6-栅极绝缘层；7-像素电极；7A-下层像素电极；7B-上层像素电极； 
8-公共电压线；9-过孔；10-数据线；11A、11B-子像素。 
具体实施方式
为使本实用新型的目的、技术方案和优点更加清楚明白，以下举实施例并参照附图，对本实用新型进一步详细说明。 
图2为采用本实用新型实施例提供的双栅像素结构的液晶面板的俯视图，从图2可以看出，每个子像素单元的上下两层像素电极通过过孔9连接，两个子像素单元11A和11B的像素电极分别与公共电压线8交叠，一行子像素阵列需要由两行栅线来驱动，例如在栅线1A和栅线1B之间的一行像素需要由栅线1A和栅线1B同时驱动，一条数据线10与两列子像素单元连接。 
图3为本实用新型实施例提供的沿图2的切割线AB切割后的像素结构示意图，该像素结构包括： 
栅极1，位于最底层； 
下层像素电极7A，与栅极1位于同一层； 
栅极绝缘层6，覆盖于栅极1和下层像素电极7A之上； 
源极2； 
漏极3，与源极2处于同一层； 
绝缘层5，覆盖于源极2和漏极3之上； 
上层像素电极7B，与漏极3和下层像素电极7A电性相连。 
半导体层4，位于栅极绝缘层6之上，位于源极2、漏极3之下，连接源极2和漏极3，在源极2和漏极3之间的半导体层上覆盖绝缘层5； 
公共电压线8，位于上层像素电极7B与下层像素电极7A之间，中间填充绝缘材料，以保证上下两层像素电极与公共电压线8共同形成存储电容Cst。 
在本实用新型优选实施例中，所述上层像素电极7B与所述下层像素电极7A的正对面积相同，所述上层像素电极7B与所述下层像素电极7A通过过孔9电性相连。当然，所述上层像素电极7B与所述下层像素电极7A可以部分面积交叠，以保证上下两层像素电极与公共电压线8共同形成存储电容Cst。所述公共电压线8与所述源极2和所述漏极3分别位于所述过孔9的两侧，所述公共电压线8在垂直方向上与所述上层像素电极7B和所述下层像素电极7A的部分面积交叠，所述上层像素电极7B和所述下层像素电极7A与所述公共电压线8形成存储电容Cst。当然，也可以是所述上层像素电极7B和/或所述下层像素电极7A的面积覆盖全部的公共电压线8面积，以共同形成存储电容Cst。与现有技术相比，由于是由上下两层像素电极与公共电压线8共同形成存储电容Cst，增加了交叠面积，因此可以增大存储电容Cst。 
在本实用新型优选实施例中，所述公共电压线8与所述源极2和所述漏极3由同一层金属层形成。 
在本实用新型优选实施例中，所述上层像素电极7B与所述公共电压线8之间只有绝缘层5；所述下层像素电极7A与所述公共电压线8之间只有栅极绝缘层6。与现有技术相比，由于上下层像素电极与公共电压线8之间只有一层绝缘层，因此减小了距离，从而可以增大存储电容Cst。 
基于上述设计，在存储电容Cst的容量一定的情况下，本实用新型的技术方案可以通过减小公共电压线8(Vcom)的宽度的方式，有效的增加开口率。 
在本实用新型一优选实施例中，所述上下层像素电极的材质为铟锡氧化物。本领域一般技术人员可以理解，除使用铟锡氧化物作为像素电极外，还可使用其他可导电的透过率高的材料作为像素电极(透过率至少在97％以上)，本实用 新型不再一一举例说明。 
图4为本实用新型实施例提供的沿图2的切割线CD切割后的像素结构示意图，从该结构示意图中可以看出，位于两个子像素电极之间有两条栅线，即由图4的像素结构构成面板中，每行子像素通过两条栅线驱动。 
本实用新型实施例还相应给出了本实用新型实施例所提供的像素结构的掩膜生产流程，共分为以下五个掩膜处理步骤： 
第一步：进行栅极1的掩膜处理过程； 
第二步：进行下层像素电极层7A的掩膜处理过程； 
第三步：沉积栅极绝缘层6后，采用同一金属层通过一次掩膜处理过程生成源极2、漏极3及公共电压线8； 
第四步：进行绝缘层5的掩膜处理过程； 
第五步：进行上层像素电极层7B的掩膜处理过程。 
其中，下层像素电极层7A和上层像素电极层7B可以共用同一掩膜处理工艺，与传统液晶面板的四次掩膜工艺相比在成本上并没有增加。 
以上所述，仅为本实用新型的较佳实施例而已，并非用于限定本实用新型的保护范围。 

Claims (8)

1.一种像素结构，其特征在于，包括：
栅极；
下层像素电极，与栅极位于同一层；
栅极绝缘层，覆盖于栅极和下层像素电极之上；
源极；
漏极；
绝缘层，覆盖于源极和漏极之上；
上层像素电极，与漏极和下层像素电极电性相连；
半导体层，位于栅极绝缘层之上，位于源极、漏极之下，连接源极和漏极；
公共电压线，位于上层像素电极与下层像素电极之间，上层像素电极和下层像素电极与所述公共电压线形成存储电容Cst。
2.根据权利要求1所述的像素结构，其特征在于，
所述上层像素电极与所述下层像素电极的正对面积相同。
3.根据权利要求2所述的像素结构，其特征在于，
所述上层像素电极与所述下层像素电极通过过孔电性相连。
4.根据权利要求3所述的像素结构，其特征在于，
所述公共电压线在垂直方向上与所述上层像素电极和所述下层像素电极的部分面积交叠。
5.根据权利要求4所述的像素结构，其特征在于，
所述公共电压线与所述源极和所述漏极由同一层金属层形成。
6.根据权利要求4所述的像素结构，其特征在于，
所述上层像素电极与所述公共电压线之间只有绝缘层；
所述下层像素电极与所述公共电压线之间只有栅极绝缘层。
7.一种双栅像素结构，其特征在于，该双栅像素结构中的每个像素结构由如权利要求1至6中任一所述的两个像素结构构成。
8.一种显示装置，其特征在于，该显示装置包括如权利要求1至7中任一项所述的像素结构。
CN2012202246426U 2012-05-17 2012-05-17 一种像素结构、双栅像素结构及显示装置 Expired - Lifetime CN202661759U (zh)

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WO2013170657A1 (zh) * 2012-05-17 2013-11-21 北京京东方光电科技有限公司 像素结构、双栅像素结构及显示装置
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