CN202652187U - Micropower medium-speed digital signal isolating circuit - Google Patents
Micropower medium-speed digital signal isolating circuit Download PDFInfo
- Publication number
- CN202652187U CN202652187U CN 201220262556 CN201220262556U CN202652187U CN 202652187 U CN202652187 U CN 202652187U CN 201220262556 CN201220262556 CN 201220262556 CN 201220262556 U CN201220262556 U CN 201220262556U CN 202652187 U CN202652187 U CN 202652187U
- Authority
- CN
- China
- Prior art keywords
- output
- resistance
- optocoupler
- connects
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The utility model provides a micropower medium-speed digital signal isolating circuit. The micropower medium-speed digital signal isolating circuit comprises the following components of: a differential circuit, wherein a first input end of the differential circuit receives input signals, and a second input end of the differential circuit is connected with a power supply; a first optocoupler, wherein a positive input of the first optocoupler is connected to a first output end of the differential circuit, and a negative input end of the first optocoupler is connected to a second output end of the differential circuit; a second optocoupler, wherein a positive input end of the second optocoupler is connected to the second output end of the differential circuit, and a negative input end of the second optocoupler is connected to the first output end of the differential circuit; and a bistable trigger, wherein a first input end of the bistable trigger is connected to an output end of the first optocoupler, and a second input end of the bistable trigger is connected to an output end of the second optocoupler. The micropower medium-speed digital signal isolating circuit of the utility model has the advantages of simple circuit, low cost, almost no power consumption in a direct current or low frequency state, extremely low power consumption in a medium frequency state, fast speed and small waveform distortion.
Description
Technical field
The utility model relates to speed digital signal buffer circuit in a kind of little power consumption.
Background technology
For safety and anti-interference, in industry spot, instrument and meter, Medical Devices, often need to carrying out the electricity isolation between the different circuit, to carry out the transmission of digital signal between the circuit of isolation simultaneously.The most frequently used digital signal partition method has the photoelectrical coupler custom circuit, Fig. 1 shows a kind of buffer circuit of the prior art, it transmits dead level, when input signal Vi is low, LED conducting in the photoelectrical coupler 107, after the photosensitive tube Q1 of receiving terminal received, it was low making output Vo, at this moment has electric current to flow through in resistance R 1 and the resistance R 2 always; When input signal Vi is high, not conducting of LED in the photoelectrical coupler 107, the photosensitive tube Q1 no signal of receiving terminal, make output Vo for high, the shortcoming of this circuit structure is that power consumption (for example＞10mA), because the time delay of turn-on and turn-off is different, causes waveform that distortion is arranged greatly, duty ratio changes, and transmission rate is not high.
The photoelectrical coupler of superelevation current transfer ratio (CTR) is also arranged on the market, make drive current less, but transmission rate is extremely low (for example＜500Hz).Yet in a lot of practical applications, the speed of several KHz is necessary, and for example baud rate commonly used is 9600, is equivalent to the highest signal frequency of 4.8KHz.
Disclose a kind of photoelectric coupler isolated communication circuit in the Chinese patent application that on October 6th, 2010, disclosed notification number was CN101854168A, by increasing a triode and some resistance, accelerated the speed of optocoupler, also suitably reduced power consumption.But this circuit is limited to the reduction of power consumption, because input signal is when low, the optocoupler both sides have electric current to flow through always.
Granted publication number discloses a kind of high-speed low power consumption photoelectrical coupling circuit in the Chinese utility model patent of CN201805416U, complementation by two optocouplers comes work, can promote the speed of circuit, also suitably reduce power consumption (quiescent dissipation of output is very little).But under any state, two one of them always conductings of optocoupler, power consumption is always arranged, so the reduction of power consumption also is limited.
The manufacturer of digital isolator spare is a lot, and such as the HCPL series of Avago, the ISO72XX series of TI, the ADuM12/14XX series of ADI, the product of each manufacturer all is widely used.These devices are compared traditional photoelectrical coupler and are made great progress, speed can high (for example rank of MHz), and power consumption also has very large minimizing (for example 2mA/ passage), still, the power consumption of these devices is all more than 1mA, even quiescent dissipation also greatly (for example＞0.8mA).
In a lot of the application, it is too high that the power consumption of 1mA still seems, the two-wire system instrument of industry spot for example, its available current only has 4mA sometimes altogether, this 4mA has much other important use, such as driving sensor, calculate etc., for battery powered system, the electric current of 1mA will shorten the life-span of battery greatly.
The custom circuit of photoelectrical coupler is the transmission dead level, and it can't reduce electric current simultaneously, improves again speed, even DC level, a state at least therein, the both sides of photoelectrical coupler have electric current to flow through.
Publication number is to disclose a kind of optocoupler system in the U.S. Patent application of US2010/0213874A1, although also be with edging trigger ILEDH (large electric current), but in order to distinguish rising, to descend, it also has LILEDL (less electric current) and Null ILED (no current), it requires three kinds of electric currents of photoelectrical coupler transmission, large electric current (edge), little electric current (rising edge), no current (trailing edge), circuit is very complicated, and reliability is not high, and circuit devcie is many, power consumption is still larger, and cost is also high.
Publication number is to disclose a kind of low-power consumption optocoupler in the U.S. Patent application of US2010/0327195A1, also is to use edging trigger, but in order to distinguish risings, to descend, its driving pulse divides two kinds of durations: during rising edge, pulsewidth is lacked; Pulsewidth is long during trailing edge.But this circuit is realized very complex, and circuit devcie is many, has limited the reduction of power consumption, and cost is also high.
The utility model content
The technical problems to be solved in the utility model provides speed digital signal buffer circuit in a kind of little power consumption, and circuit is simple, and cost is lower, hardly power consumption when direct current or low frequency, and when intermediate frequency, power consumption is also extremely low, speed, wave distortion is minimum.
For solving the problems of the technologies described above, the utility model provides speed digital signal buffer circuit in a kind of little power consumption, comprising:
Differential circuit, its first input end receives input signal, its second input termination power;
The first optocoupler, its positive input terminal connect the first output of described differential circuit, and its negative input end connects the second output of described differential circuit;
The second optocoupler, its positive input terminal connect the second output of described differential circuit, and its negative input end connects the first output of described differential circuit;
Flip and flop generator, its first input end connects the output of described the first optocoupler, and its second input connects the output of described the second optocoupler.
According to a specific embodiment, the speed digital signal buffer circuit also comprises in this little power consumption:
Si Mite inverter, described input signal transfer to the first input end of described differential circuit via described Si Mite inverter.
According to a specific embodiment, described differential circuit comprises the first resistance, the second resistance and the first electric capacity, wherein,
One end of described the first resistance connects described power supply, and the other end connects an end of described the second resistance;
The other end of described the second resistance connects an end of described the first electric capacity, and the two ends of described the second resistance are respectively the first output and second output of described differential circuit;
One end of described the first electric capacity connects the output of described Si Mite inverter.
Alternatively, described differential circuit comprises the first resistance, the second resistance and the first electric capacity, wherein,
One end of described the first electric capacity connects described power supply, and the other end connects an end of described the second resistance;
The other end of described the second resistance connects an end of described the first resistance, and the two ends of described the second resistance are respectively the first output and second output of described differential circuit;
One end of described the first resistance connects the output of described Si Mite inverter.
Alternatively, described differential circuit comprises the first resistance, the second resistance and the first electric capacity, wherein,
Described the first resistance and the first capacitances in series, the end after the series connection connects described power supply, and the other end connects an end of described the second resistance;
The other end of described the second resistance connects the output of described Si Mite inverter.
Alternatively, described differential circuit comprises the first resistance, the second resistance and the first electric capacity, wherein,
Described the first resistance and the first capacitances in series, the end after the series connection connects the output of described Si Mite inverter, and the other end connects an end of described the second resistance;
The other end of described the second resistance connects described power supply.
According to a specific embodiment, described flip and flop generator comprises:
The first inverter, its input connects the output of described the first optocoupler, and its output is the output of described flip and flop generator;
The second inverter, its input connects the output of described the second optocoupler;
The 3rd resistance, its first end connects the output of described the first optocoupler, and its second end connects the output of described the second inverter;
The 4th resistance, its first end connects the output of described the second optocoupler, and its second end connects the output of described the first inverter.
According to a specific embodiment, described flip and flop generator comprises:
The first NAND gate, its first input end connects the output of described the first optocoupler, its second input receive logic high level, its output is the output of described flip and flop generator;
The second NAND gate, its first input end connects the output of described the second optocoupler, its second input receive logic high level;
The 3rd resistance, its first end connects the output of described the first optocoupler, and its second end connects the output of described the second NAND gate;
The 4th resistance, its first end connects the output of described the second optocoupler, and its second end connects the output of described the first NAND gate.
Compared with prior art, the utlity model has following advantage:
In little power consumption of the utility model embodiment in the speed digital signal buffer circuit, adopt differential circuit that input signal is carried out preliminary treatment, adopt two optocouplers respectively rising edge edge and the trailing edge edge of signal transmission, adopt afterwards the bistable circuit reconstruction signal, this circuit structure is simple, hardly power consumption when direct current or low frequency, when intermediate frequency, power consumption is also extremely low, speed, wave distortion is little, and the cost of whole circuit is also lower.
Description of drawings
Fig. 1 is the circuit diagram of a kind of buffer circuit of the prior art;
Fig. 2 is the circuit diagram of the buffer circuit of the utility model the first embodiment;
Fig. 3 is the circuit diagram of the buffer circuit of the utility model the second embodiment.
Embodiment
The utility model is described in further detail below in conjunction with specific embodiments and the drawings, but should not limit protection range of the present utility model with this.
Fig. 1 shows the circuit diagram of the buffer circuit of present embodiment, comprising: Si Mite inverter U1, differential circuit 11, the first optocoupler Opto1, the second optocoupler Opto2, flip and flop generator 12.
Wherein, input signal Input transfers to the input of differential circuit 11 after via Si Mite inverter U1 shaping.Need to prove that Si Mite inverter U1 is optional, in other specific embodiments, input signal Input can be directly inputted into the input of differential circuit 11.
Differential circuit 11 comprises the first resistance R 1, the second resistance R 2 and the first capacitor C 1.The first resistance R 1, the second resistance R 2 and the first capacitor C 1 are connected between the output of power Vcc 1 and Si Mite inverter U1 successively.Particularly, an end of the first resistance R 1 connects power Vcc 1, and the other end connects an end of the second resistance R 2; The other end of the second resistance R 2 connects an end of the first capacitor C 1; The other end of the first capacitor C 1 connects the output a of Si Mite inverter U1.Wherein the two ends of the second resistance R 2 are respectively as the first output b and the second output c of differential circuit 11.
Need to prove that the differential circuit 11 among Fig. 1 only is example, can be out of shape accordingly in other embodiments that for example the position of the first resistance R 1 and the first capacitor C 1 can change: the position of the first resistance R 1 and the first capacitor C 1 exchanges; Perhaps be placed on the position of Fig. 1 Central Plains the first resistance R 1 after the first resistance R 1 and 1 series connection of the first capacitor C, the position short circuit of Fig. 1 Central Plains the first capacitor C 1; Perhaps be placed on the position of Fig. 1 Central Plains the first capacitor C 1 after the first resistance R 1 and 1 series connection of the first capacitor C, the position short circuit of Fig. 1 Central Plains the first resistance R 1.
The positive input terminal of the first optocoupler Opto1 (i.e. the positive input terminal of light-emitting diode among the first optocoupler Opto1) connects the first output b of differential circuit 11, and its negative input end (i.e. the negative input end of light-emitting diode among the first optocoupler Opto1) connects the second output c of differential circuit 11.The positive input terminal of the second optocoupler Opto2 (i.e. the positive input terminal of light-emitting diode among the second optocoupler Opto2) connects the second output c of differential circuit 11, and its negative input end (i.e. the negative input end of light-emitting diode among the second optocoupler Opto2) connects the first output b of differential circuit 11.
The output d of the first optocoupler Opto1 connects the first input end of flip and flop generator 12, and the output e of the second optocoupler Opto2 connects the second input of flip and flop generator 12.
In the first embodiment, flip and flop generator 12 comprises: the first inverter U2-A, and its input connects the output of the first optocoupler Opto1, and its output is as the output Output of flip and flop generator 12; The second inverter U2-B, its input connects the output of the second optocoupler Opto2; The 3rd resistance R 3, its first end connects the output of the first optocoupler Opto1, and the second end connects the output of the second inverter U2-B; The 4th resistance R 4, its first end connects the output of the second optocoupler Opto2, and its second end connects the output of the first inverter U2-A.
At input signal Input from low to high the time, the output a of Si Mite inverter U1 from high to low, the peak current of differential circuit 11 flows through the light-emitting diode among the first optocoupler Opto1, the output d step-down of the first optocoupler Opto1, output Output uprises, since no current among this moment the second optocoupler Opto2, thereby node f step-down, when being full of the voltage of power Vcc 1 on the first capacitor C 1, whole buffer circuit is current sinking no longer just.
At input signal Input from high to low the time, the output a of Si Mite inverter U1 from low to high, the peak current of differential circuit 11 flows through the light-emitting diode among the second optocoupler Opto2, the output e step-down of the second optocoupler Opto2, node f uprises, because no current among the first optocoupler Opto1, thereby output Output step-down.When the electric charge on the first capacitor C 1 was all given out light, whole buffer circuit is current sinking no longer just.
Wherein, the output a of Si Mite inverter U1 just has the output resistance Rout of equivalence, Rout=75Ohm for example, and then time constant C1* (Rout+R1) should adapt with the delay time of the first optocoupler Opto1 and the second optocoupler Opto2.
Common the second resistance R 2 should be much larger than the resistance value of the first resistance R 1, in order to avoid the effective current at peak current initial stage wasted too much, still, time constant C 1*R2 generally should less than signal transmission the most short-period half.Make after the peak current, the electric current in the light-emitting diode in the optocoupler arrives zero as early as possible, and the electric charge among the C1 discharges as early as possible, or is full of as early as possible, for next edge ready.
The resistance value of the 3rd resistance R 3 and the 4th resistance R 4 should be moderate, can not be too little, guarantee that under the effect of peak current the output e of the output d of the first optocoupler Opto1 or the second optocoupler Opto2 can reach logic low potential.But the resistance value of the 3rd resistance R 3 and the 4th resistance R 4 can not be too large, in order to avoid affect rapidity.
The buffer circuit of present embodiment, simple in structure, hardly power consumption when direct current or low frequency; When intermediate frequency, power consumption is also extremely low, speed, and wave distortion is minimum.The first optocoupler Opto1, the second optocoupler Opto2 can be conventional common optical coupler devices, thereby the cost of whole circuit is also very low.
As a nonrestrictive example, among the first embodiment, power source voltage Vcc 1=Vcc2=3V, the capacitance C1=6.8nF of the first capacitor C, the resistance value R1=100Ohm of the first resistance R 1, the resistance value R2=4.7kOhm of the second resistance R 2, the resistance value R3=6.8kOhm of the 3rd resistance R 3, the resistance value R4=6.8kOhm of the 4th resistance R 4.The model of the first optocoupler Opto1 and the second optocoupler Opto2 is K817P2.During the frequency F=1Hz of input signal Input, the average sum of the electric current of power Vcc 1 and Vcc2: Icc1+Icc2＜0.5 μ A; During the frequency F=50Hz of input signal Input, the average sum of the electric current of power Vcc 1 and Vcc2: Icc1+Icc2=3 μ A; During the frequency F=5kHz of input signal Input, the average sum of the electric current of power Vcc 1 and Vcc2: Icc1+Icc2=200 μ A; During the frequency F=10kHz of input signal Input, the average sum of the electric current of power Vcc 1 and Vcc2: Icc1+Icc2=400 μ A.
When practical application, also can adopt the identical buffer circuit of another set of reversal connection, realize the transmitted in both directions of digital signal.
Although the buffer circuit of present embodiment is at the initial stage of powering on, before input was sent out first signal, output was uncertain, as long as there are data to send, output can synchronously, be no problem in the overwhelming majority is used just.
In addition, because the differential circuit of input and the circuits for triggering of output, noise slightly on the power supply of both sides, but because power consumption is extremely low, can be easy to adopt general capacitor filtering, capacitance-resistance filter to eliminate.
Fig. 2 shows the circuit diagram of the buffer circuit of the second embodiment, and except the physical circuit of flip and flop generator 12 slightly the difference, other circuit are identical with the first embodiment shown in Figure 1.In a second embodiment, flip and flop generator 12 specifically comprises: the first NAND gate U3-A, its first input end connects the output d of the first optocoupler Opto1, its second input receive logic high level (namely connecting second source Vcc2), and its output is the output of flip and flop generator 12; The second NAND gate U3-B, its first input end connect the output e of the second optocoupler, its second input receive logic high level (namely connecting second source Vcc2); The 3rd resistance R 3, its first end connect the output d of the first optocoupler Opto1, and its second end connects the output of the second NAND gate U3-B; The 4th resistance R 4, its first end connect the output e of the second optocoupler, and its second end connects the output of the first NAND gate U3-A.
Operation principle and first embodiment of the buffer circuit among second embodiment shown in Figure 2 are similar, repeat no more here.
Need to prove, in the first embodiment, flip and flop generator comprises the first inverter, the second inverter, the 3rd resistance and the 4th resistance, adopt the first NAND gate and the second NAND gate to replace respectively the first inverter and the second inverter among the second embodiment, but should be appreciated that for those skilled in the art gates such as also can adopting NOR gate, XOR gate or J-K flip flop etc. and the 3rd resistance and the collocation of the 4th resistance form flip and flop generator.
Although the utility model with preferred embodiment openly as above; but it is not to limit the utility model; any those skilled in the art are not within breaking away from spirit and scope of the present utility model; can make possible change and modification; therefore, protection range of the present utility model should be as the criterion with the scope that the utility model claim is defined.
Claims (8)
1. speed digital signal buffer circuit in the little power consumption is characterized in that, comprising:
Differential circuit, its first input end receives input signal, its second input termination power;
The first optocoupler, its positive input terminal connect the first output of described differential circuit, and its negative input end connects the second output of described differential circuit;
The second optocoupler, its positive input terminal connect the second output of described differential circuit, and its negative input end connects the first output of described differential circuit;
Flip and flop generator, its first input end connects the output of described the first optocoupler, and its second input connects the output of described the second optocoupler.
2. speed digital signal buffer circuit in little power consumption according to claim 1 is characterized in that, also comprises:
Si Mite inverter, described input signal transfer to the first input end of described differential circuit via described Si Mite inverter.
3. speed digital signal buffer circuit in little power consumption according to claim 2 is characterized in that, described differential circuit comprises the first resistance, the second resistance and the first electric capacity, wherein,
One end of described the first resistance connects described power supply, and the other end connects an end of described the second resistance;
The other end of described the second resistance connects an end of described the first electric capacity, and the two ends of described the second resistance are respectively the first output and second output of described differential circuit;
One end of described the first electric capacity connects the output of described Si Mite inverter.
4. speed digital signal buffer circuit in little power consumption according to claim 2 is characterized in that, described differential circuit comprises the first resistance, the second resistance and the first electric capacity, wherein,
One end of described the first electric capacity connects described power supply, and the other end connects an end of described the second resistance;
The other end of described the second resistance connects an end of described the first resistance, and the two ends of described the second resistance are respectively the first output and second output of described differential circuit;
One end of described the first resistance connects the output of described Si Mite inverter.
5. speed digital signal buffer circuit in little power consumption according to claim 2 is characterized in that, described differential circuit comprises the first resistance, the second resistance and the first electric capacity, wherein,
Described the first resistance and the first capacitances in series, the end after the series connection connects described power supply, and the other end connects an end of described the second resistance;
The other end of described the second resistance connects the output of described Si Mite inverter.
6. speed digital signal buffer circuit in little power consumption according to claim 2 is characterized in that, described differential circuit comprises the first resistance, the second resistance and the first electric capacity, wherein,
Described the first resistance and the first capacitances in series, the end after the series connection connects the output of described Si Mite inverter, and the other end connects an end of described the second resistance;
The other end of described the second resistance connects described power supply.
7. speed digital signal buffer circuit in each described little power consumption in 6 according to claim 1 is characterized in that described flip and flop generator comprises:
The first inverter, its input connects the output of described the first optocoupler, and its output is the output of described flip and flop generator;
The second inverter, its input connects the output of described the second optocoupler;
The 3rd resistance, its first end connects the output of described the first optocoupler, and its second end connects the output of described the second inverter;
The 4th resistance, its first end connects the output of described the second optocoupler, and its second end connects the output of described the first inverter.
8. speed digital signal buffer circuit in each described little power consumption in 6 according to claim 1 is characterized in that described flip and flop generator comprises:
The first NAND gate, its first input end connects the output of described the first optocoupler, its second input receive logic high level, its output is the output of described flip and flop generator;
The second NAND gate, its first input end connects the output of described the second optocoupler, its second input receive logic high level;
The 3rd resistance, its first end connects the output of described the first optocoupler, and its second end connects the output of described the second NAND gate;
The 4th resistance, its first end connects the output of described the second optocoupler, and its second end connects the output of described the first NAND gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220262556 CN202652187U (en) | 2012-06-05 | 2012-06-05 | Micropower medium-speed digital signal isolating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220262556 CN202652187U (en) | 2012-06-05 | 2012-06-05 | Micropower medium-speed digital signal isolating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202652187U true CN202652187U (en) | 2013-01-02 |
Family
ID=47421215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220262556 Expired - Lifetime CN202652187U (en) | 2012-06-05 | 2012-06-05 | Micropower medium-speed digital signal isolating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202652187U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107682003A (en) * | 2017-09-15 | 2018-02-09 | 上海微程电气设备有限公司 | A kind of number bus isolates telecommunication circuit |
-
2012
- 2012-06-05 CN CN 201220262556 patent/CN202652187U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107682003A (en) * | 2017-09-15 | 2018-02-09 | 上海微程电气设备有限公司 | A kind of number bus isolates telecommunication circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DK3061197T3 (en) | METHOD AND SYSTEM FOR PROVIDING PULSED POWER AND DATA ON A BUS | |
| CN202854225U (en) | Sinusoidal alternating current voltage zero cross detection circuit | |
| CN102215035A (en) | Alternating current mains supply isolation zero crossing checking circuit combined with low-voltage power line carrier wave communication signal coupling | |
| CN103063904A (en) | Zero cross detection circuit | |
| CN103684943A (en) | Bus system with power supply transmission and data communication functions | |
| CN102365848B (en) | Wireless two-way transmission of serial data signals between an electronic device and a power meter | |
| CN103926862B (en) | The means of communication of micro energy lose M-bus slave terminal circuits for intelligence instrument communication | |
| CN203883848U (en) | Clock synchronization device for intelligent substation synchronization tests | |
| CN102508014B (en) | Power line carrier communication zero-crossing detection system and method thereof | |
| CN202652187U (en) | Micropower medium-speed digital signal isolating circuit | |
| CN101226672A (en) | Communication control alarm device | |
| CN203135826U (en) | Drive circuit of voltage type gate control device | |
| CN203745879U (en) | RS485 data acquisition device | |
| CN205017636U (en) | A peak current detection circuitry for LED constant -current drive circuit | |
| CN103023482B (en) | Isolating interface circuit | |
| CN102368667A (en) | Offline type AC-DC (Alternating Current-Direct Current) control circuit and converting circuit comprising same | |
| CN109413803A (en) | LED adjusting control circuit | |
| CN203574621U (en) | Pulse switch drive circuit based on laser ranging | |
| CN203746065U (en) | Serial port expander of microprocessor | |
| CN207218378U (en) | The online switch modulation digital communication control system of local power utilization network | |
| CN203151466U (en) | Positive-negative logic level conversion switching circuit | |
| CN205320057U (en) | Level shifting circuit based on MAX series chip | |
| CN203216983U (en) | Zero-crossing detection circuit | |
| CN201751900U (en) | Novel type isolator for USB equipment | |
| CN103501190B (en) | Electric line carrier communication circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130102 |
|
| CX01 | Expiry of patent term |