CN202600420U

CN202600420U - Double-CPU circuit of power supply monitor of transformer substation

Info

Publication number: CN202600420U
Application number: CN 201220004934
Authority: CN
Inventors: 邓渝生; 赵应春
Original assignee: CHONGQING ELECTRIC POWER Corp MAINTENANCE BRANCH; State Grid Corp of China SGCC
Current assignee: CHONGQING ELECTRIC POWER Corp MAINTENANCE BRANCH; State Grid Corp of China SGCC
Priority date: 2012-01-06
Filing date: 2012-01-06
Publication date: 2012-12-12
Anticipated expiration: 2022-01-06

Abstract

The utility model relates to a double-CPU circuit of a power supply monitor of a transformer substation. A first single chip microcomputer (1) is respectively connected with a power-down protection memory (U4), an ethernet chip (U11), an RS232 interface chip ( U2 ) and an RS485 interface chip (U12); a keyboard (J9), a 5-V power supply and a first 8M crystal oscillator (J51) are connected with the first single chip microcomputer (1); the ethernet chip (U11) is connected with an ethernet interface (J45); the RS232 interface chip (U2) is connected with an RS232 interface (J1); the RS485 interface chip (U12) is connected with an RS485 interface (J2); and the first single chip microcomputer (1) is connected with a second single chip microcomputer (2) by an IIC bus. According to the utility model, two single chip microcomputers are applied to a power supply monitor of a transformer substation jointly; the data exchange is realized; the transmission rate is high; and the serial port resources are not occupied.

Description

The two cpu circuits of transformer station's power supply monitor

Technical field

The utility model relates to a kind of power supply monitor circuit, is specifically related to the two cpu circuits of a kind of transformer station power supply monitor.

Background technology

Along with science and technology development, single-chip microcomputer has been widely used in fields such as intelligent management and the process control of instrument and meter, household electrical appliance, medical equipment, Aero-Space, specialized equipment.All adopt single CPU in most controllers, speed is slow, and efficient is low, can not effectively solve the control of complex systems problem.

The utility model content

The purpose of the utility model provides the two cpu circuits of a kind of transformer station power supply monitor; It has solved the accumulator problem of detached island of information effectively; Its online feed-back type discharge technology; Both energy-conserving and environment-protective have alleviated the battery service working strength again, have reduced some potential dangers in the battery service operation.

In order to solve the existing problem of background technology; The utility model is taked following technical scheme: it comprises first single-chip microcomputer 1, second singlechip 2, power down protection storer U4, keyboard J9, Ethernet chip U11, Ethernet interface J45, RS232 interface chip U2, RS232 interface J1, RS485 interface chip U12, RS485 interface J2, liquid crystal display LCD interface J6, random access memory U8, a 8M crystal oscillator J51, the 2nd 8M crystal oscillator J52 and the chip U16 that resets; First single-chip microcomputer 1 interconnects with power down protection storer U4, Ethernet chip U11, RS232 interface chip U2 and RS485 interface chip U12 respectively; Keyboard J9,5V power supply and a 8M crystal oscillator J51 all link to each other with first single-chip microcomputer 1; Ethernet chip U11 links to each other with Ethernet interface J45; RS232 interface chip U2 links to each other with RS232 interface J1; RS485 interface chip U12 links to each other with RS485 interface J2; First single-chip microcomputer 1 links to each other with second singlechip 2 through iic bus, and second singlechip 2 interconnects with liquid crystal display LCD interface J6, random access memory U8, and 5V power supply, the 2nd 8M crystal oscillator J52 and the chip U16 that resets all link to each other with second singlechip 2.

In the utility model first single-chip microcomputer 1 constitute communication line through iic bus by data line SDA and two lines of clock line SCL with 2 two master-slave cpus of second singlechip.Not only can be used for sending data but also can receive data, can between two single-chip microcomputers, carry out the bi-directional data transmission.Bus keeps high level under idle condition, being connected to single-chip microcomputer on the bus in a single day has low level output all will draw bus to be low level.Single-chip microcomputer is that host scm sends initiating signal when carrying out the data transmission, and clocking sends stop signal at last; Between the SCL high period, the data on the sda line are just effective, and the last data of SDA must be could change in this moment of low level at SCL, and to transmit the data of next byte, the intact byte of every transmission just has the time-out of a clock; The equipment that is addressed to receives and all must produce an answer signal after the byte and between the SCL high period, accept equipment and draw SDA for low level and just can produce an answer signal.

The utility model has solved the accumulator problem of detached island of information effectively, its online feed-back type discharge technology, and both energy-conserving and environment-protective have alleviated the battery service working strength again, have reduced some potential dangers in the battery service operation.

Description of drawings

Fig. 1 is the structural representation of the utility model.

Embodiment

With reference to Fig. 1; This embodiment is taked following technical scheme: it comprises first single-chip microcomputer 1, second singlechip 2, power down protection storer U4, keyboard J9, Ethernet chip U11, Ethernet interface J45, RS232 interface chip U2, RS232 interface J1, RS485 interface chip U12, RS485 interface J2, liquid crystal display LCD interface J6, random access memory U8, a 8M crystal oscillator J51, the 2nd 8M crystal oscillator J52 and the chip U16 that resets; First single-chip microcomputer 1 interconnects with power down protection storer U4, Ethernet chip U11, RS232 interface chip U2 and RS485 interface chip U12 respectively; Keyboard J9,5V power supply and a 8M crystal oscillator J51 all link to each other with first single-chip microcomputer 1; Ethernet chip U11 links to each other with Ethernet interface J45; RS232 interface chip U2 links to each other with RS232 interface J1; RS485 interface chip U12 links to each other with RS485 interface J2; First single-chip microcomputer 1 links to each other with second singlechip 2 through iic bus, and second singlechip 2 interconnects with liquid crystal display LCD interface J6, random access memory U8, and 5V power supply, the 2nd 8M crystal oscillator J52 and the chip U16 that resets all link to each other with second singlechip 2.

First single-chip microcomputer 1 in this embodiment adopts SAK-XC167CI-32F40F, and second singlechip 2 adopts SAF-XE164K-24F66L, single-chip microcomputer SAK-XC167CI-32F40F; Five-stage pipeline high-performance 16 bit CPUs, the instruction cycletime of 25ns (cpu clock is 40MHz frequently), 25ns multiplication (16x16 position); Backstage division (32/16), multiply accumulating (MAC) instruction, synchronous flexibly external bus interface; 16 grades of priority interrupt systems, 8 group priority are supported debugging (ODCS) on the sheet; RAM on the 8KB/12KB sheet, 128KB/256KB program Flash storer, 16 path 10 figure place weighted-voltage D/A converters; Switching time＜3 μ s respectively catches/comparing unit with two 16 passages of two independent time benchmark, has the CAPCOM6 module of two independent timers; Generation is used for the pwm signal of AC and DC Electric Machine Control, 10 bit addressings, the I of 400kbit/s ²The C bus module, two synchronous/asynchronous serial-ports (USART), two high-speed synchronous serial-ports (SPI); The TwinCAN module with two global function CAN nodes of 32 packet buffers and gateway function, reaches 103 I/O pins; Bit addressing separately, the dual power supply on the plate can provide the voltage of 1: 6 volts of 5V volts, fast CAN transceiver for XC167CI; The LIN transceiver, EPROM, URAT (RS232 serial ports).

Single-chip microcomputer SAF-XE164K-24F66L; High-performance CPU and MPU with five-stage pipeline, when cpu clock was 80MHz, the instruction cycle was 12.5ns; Monocycle 32 additions and subtraction with 40 results; Support the extra-instruction of HLL and operating system, 16MB linear code and data address space, specific function memory areas on 1024 chunks.Subsequent use RAM on the 8KB sheet, dual port RAM on the 2KB sheet, data SRAM on the 16KB sheet, program/data SRAM on the 32KB sheet, program storage on the 576KB sheet.The multifunctional universal timer units of 5 timers, two can be synchronous ADC, support nearly 16 paths, 10 conversion accuracies, the external address space of 12MB is used for storage code and data.

First single-chip microcomputer 1 in this embodiment constitutes communication line through iic bus by data line SDA and two lines of clock line SCL with 2 two master-slave cpus of second singlechip.Not only can be used for sending data but also can receive data, can between two single-chip microcomputers, carry out the bi-directional data transmission.Bus keeps high level under idle condition, being connected to single-chip microcomputer on the bus in a single day has low level output all will draw bus to be low level.Single-chip microcomputer is that host scm sends initiating signal when carrying out the data transmission, and clocking sends stop signal at last; Between the SCL high period, the data on the sda line are just effective, and the last data of SDA must be could change in this moment of low level at SCL, and to transmit the data of next byte, the intact byte of every transmission just has the time-out of a clock; The equipment that is addressed to receives and all must produce an answer signal after the byte and between the SCL high period, accept equipment and draw SDA for low level and just can produce an answer signal.

Single-chip microcomputer SAK-XC167CI-32F40F in this embodiment and SAF-E164K-24F66L common application realize exchanges data in transformer station's power supply monitor; Two single-chip microcomputers realize that through iic bus data transmit, and transfer rate is fast, does not take serial port resource.

This embodiment has solved the accumulator problem of detached island of information effectively, its online feed-back type discharge technology, and both energy-conserving and environment-protective have alleviated the battery service working strength again, have reduced some potential dangers in the battery service operation.

Claims

1. two cpu circuits of transformer station's power supply monitor; It is characterized in that it comprises first single-chip microcomputer (1), second singlechip (2), power down protection storer (U4), keyboard (J9), Ethernet chip (U11), Ethernet interface (J45), RS232 interface chip (U2), RS232 interface (J1), RS485 interface chip (U12), RS485 interface (J2), liquid crystal display LCD interface (J6), random access memory (U8), a 8M crystal oscillator (J51), the 2nd 8M crystal oscillator (J52) and the chip that resets (U16); First single-chip microcomputer (1) interconnects with power down protection storer (U4), Ethernet chip (U11), RS232 interface chip (U2) and RS485 interface chip (U12) respectively; Keyboard (J9), 5V power supply and a 8M crystal oscillator (J51) all link to each other with first single-chip microcomputer (1); Ethernet chip (U11) links to each other with Ethernet interface (J45); RS232 interface chip (U2) links to each other with RS232 interface (J1); RS485 interface chip (U12) links to each other with RS485 interface (J2); First single-chip microcomputer (1) links to each other with second singlechip (2) through iic bus; Second singlechip (2) interconnects with liquid crystal display LCD interface (J6), random access memory (U8), and 5V power supply, the 2nd 8M crystal oscillator (J52) and the chip that resets (U16) all link to each other with second singlechip (2).