CN202585322U - Miniaturized power gain equalizer - Google Patents
Miniaturized power gain equalizer Download PDFInfo
- Publication number
- CN202585322U CN202585322U CN 201220171549 CN201220171549U CN202585322U CN 202585322 U CN202585322 U CN 202585322U CN 201220171549 CN201220171549 CN 201220171549 CN 201220171549 U CN201220171549 U CN 201220171549U CN 202585322 U CN202585322 U CN 202585322U
- Authority
- CN
- China
- Prior art keywords
- hole
- plated
- via hole
- resonant cavity
- chamber wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Control Of Motors That Do Not Use Commutators (AREA)
Abstract
The utility model relates to a miniaturized power gain equalizer, comprising a microstrip layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, a third dielectric layer and a third metal layer which are overlapped vertically and successively. A first plated through hole passes through a first via hole and is connected with a first plated counterbore to form a probe structure. The top of the probe structure is connected with a first metal connection board. A third plated through hole passes through a third via hole and is connected with a second plated counterbore to form a probe structure. The top of the probe structure is connected with a third metal connection board. A second plated through hole passes through the first via hole and is connected with a plated through hole and then passes through a via hole and is connected with a plated counterbore to form a probe structure. The top of the probe structure is connected with the first metal connection board. The beneficial effects are that the miniaturized power gain equalizer adopts a low-temperature co-fired ceramic technology to embed resonant cavities in multilayer dielectric substrates and adopts a three-dimensional staggered-floor arrangement manner to reduce volume occupied by planes, thereby realizing the miniaturization purpose.
Description
Technical field
The utility model belongs to the power device technology field, relates in particular to a kind of power gain equalizer that is directed against the adjusting of high power travelling wave tube power gain flatness.
Background technology
At present, the power gain equalizer of adjustment travelling wave tube gain flatness commonly used mainly comprises by the transmission line formal classification: micro strip line type, three kinds of waveguide type and coaxial line styles.Micro strip line type, the basic comprising of waveguide type and coaxial line style comprise transmission line main line and several resonance absorbing unit that are connected the transmission line main line.When the energy that transmits on the transmission line main line passes through certain resonance absorbing unit; This resonance absorbing unit is coupled into the resonance frequency and near the part energy thereof of this resonance absorbing unit in the resonance absorbing unit; The absorbing mechanism that relies on this resonance absorbing unit is with energy absorption, and the absorbing mechanism of resonance absorbing unit can be made up of absorbing material or resistance.Through the resonance frequency of adjustment resonance absorbing unit, the uptake size of absorbing mechanism, thereby obtain the needed curve of equalizer.
For micro strip line type; Because main transmission line resonant absorptive unit all is positioned at the same space layer; Therefore the space that further dwindles in addition of its volume, and the resonance absorbing unit of the more coaxial line style of Q value of resonance absorbing unit or waveguide type is low, is not easy to realize more precipitous attenuation curve.
For waveguide type and coaxial line style, because the use of absorbing material causes the simulation calculating amount big; Design cycle is longer, and in kind and simulation result there are differences, and needs later stage debugging work; Thereby need tunable mechanical structure, so project organization is complicated, volume is bigger.
LTCC (Low Temperature Co-fired Ceramics; LTCC) technology is a kind of multilager base plate wiring technique of successfully being developed in nineteen eighty-two by Hughes Electronics, has the integrated level height, the characteristics of excellent in high-frequency characteristics; It is to manufacture certain thickness and fine and close magnetisation band to low-temperature co-fired ceramic powder; Punching on tape again, slip casting, printed conductor figure etc. can be embedded into the design of electric capacity, resistance, passive part in the multilager base plate, finally overlap together; Behind 900 degree left and right sides sintering temperatures, manufacture highdensity multilayer circuit.Thereby can realize high integration degree, better the circuit function module of performance.
(Substrate Integrated Waveguide SIW) is made up of the wave guide wall that plated-through hole replaces the sheet metal and the both sides of bottom surface on the dielectric substrate substrate integration wave-guide, can regard the comprehensive of traditional metal waveguide and microstrip line as.The resonant cavity that substrate integration wave-guide constitutes be convenient to the plane integrated with have higher Q value.
The utility model content
The purpose of the utility model is in order to reduce power gain equalizer volume, to have proposed a kind of power gain equalizer of miniaturization.
The technical scheme of the utility model is: a kind of power gain equalizer of miniaturization comprises the little belt, first dielectric layer, the first metal layer, second dielectric layer, second metal level, the 3rd dielectric layer and the 3rd metal level that stack gradually from top to bottom;
Said little belt comprises transmission line main line, the first film resistance, second film resistor, the 3rd film resistor, first metallic interconnect, second metallic interconnect and the 3rd metallic interconnect, and said the first film resistance, second film resistor, the 3rd film resistor are arranged in order with first metallic interconnect, second metallic interconnect with after the 3rd metallic interconnect is connected respectively and are connected on the transmission line main line;
Said first dielectric layer comprises first medium substrate, first plated-through hole, second plated-through hole and the 3rd plated-through hole; Said second plated-through hole is positioned at the medium substrate center, and first plated-through hole and the 3rd plated-through hole lay respectively at the second plated-through hole both sides;
Said the first metal layer comprises dummy metal plate, first via hole, second via hole and the 3rd via hole, and said second via hole is positioned at dummy metal plate center, and first via hole and the 3rd via hole lay respectively at the second via hole both sides;
Said second dielectric layer comprises second medium substrate, the first resonant cavity chamber wall, the second resonant cavity chamber wall, the first metallization counterbore, plated-through hole and the second metallization counterbore, and the said first resonant cavity chamber wall comprises the first plated-through hole array, the first metal conduction band, the second plated-through hole array, the second metal conduction band and the 3rd plated-through hole array that stacks gradually from top to bottom; The said second resonant cavity chamber wall comprises the first plated-through hole array, the first metal conduction band, the second plated-through hole array, the second metal conduction band and the 3rd plated-through hole array that stacks gradually from top to bottom; Said plated-through hole is positioned at the second medium substrate center; The first resonant cavity chamber wall and the second resonant cavity chamber wall lay respectively at the plated-through hole both sides and are embedded in second medium substrate; The said first metallization counterbore and the second metallization counterbore lay respectively at the centermost of the first resonant cavity chamber wall and the second resonant cavity chamber wall; Said plated-through hole array is to arrange along the rectangle outer ring, and spacing is half with spacing between layer metallization via hole hole between the hole of the metallization via hole between adjacent two plated-through hole arrays;
Said second metal level comprises dummy metal plate, via hole, and said via hole is positioned at dummy metal plate center;
Said the 3rd dielectric layer comprises the 3rd medium substrate, metallization counterbore resonant cavity chamber wall; Said resonant cavity chamber wall comprises the first plated-through hole array, the first metal conduction band, the second plated-through hole array, the second metal conduction band and the 3rd plated-through hole array that stacks gradually from top to bottom; Said resonant cavity chamber wall is embedded in the 3rd medium substrate, and the metallization counterbore is positioned at wall center, resonant cavity chamber;
Said the 3rd metal level comprises metallic plate;
Said first plated-through hole passes first via hole and the first metallization counterbore formation probe structure that joins, and this probe structure top and first metallic interconnect join;
Said the 3rd plated-through hole passes the 3rd via hole and the second metallization counterbore formation probe structure that joins, and this probe structure top and the 3rd metallic interconnect join;
Said second plated-through hole passes first via hole and plated-through hole joins, and passes via hole and the metallization counterbore formation probe structure that joins again, and this probe structure top and first metallic interconnect join.
Aforementioned dummy metal plate adopts matrix grid shape structure.
The beneficial effect of the utility model is: the utility model adopts the form of printed circuit; Saved tunable mechanical structure; Reduced the complex design degree, adopt simultaneously LTCC (Low Temperature Co-fired Ceramics, LTCC) technology resonant cavity is embedded in the multilayer dielectricity substrate; And further reduced the shared volume in plane, thereby realized the purpose of miniaturization with three-dimensional staggered floor arrangement mode.The utility model has adopted substrate integration wave-guide (Substrate Integrated Waveguide; SIW) resonant cavity is used as the resonant element of the utility model; SIW is made up of plated-through hole the sheet metal and the both sides of bottom surface on the dielectric substrate; Energy is bound among the dielectric substrate, and it can regard the waveguiding structure that medium is filled as, and it is integrated to be convenient to the plane as microstrip line again simultaneously.Because microstrip structure is a semi-open structure, half is arranged is to be exposed to airbornely, in the air electromagnetic field distribution is arranged also near the microstrip circuit, thereby the loss of the loss ratio SIW structure of microstrip structure is big.Contrast waveguides, SIW is owing to having filled dielectric material, so the loss meeting of SIW is bigger than waveguide.So the Q value of the resonant element of realizing with SIW is between waveguide and little band.The utility model uses the SIW resonant cavity to be used as resonant element when reducing volume, has kept higher Q value size to a certain extent, and this helps realizing comparatively precipitous attenuation curve.
Description of drawings
Fig. 1 is the explosion perspective view of the utility model.
Fig. 2 is the perspective view that the utility model is overlooked direction.
Fig. 3 is the cross-sectional view of Fig. 2 in the A-A direction.
Fig. 4 is the side-looking structural representation of the first resonant cavity chamber wall of the utility model.
Fig. 5 is the structural representation of the dummy metal plate of the utility model.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the utility model is done further explanation:
Like Fig. 1, Fig. 2 and shown in Figure 3, a kind of power gain equalizer of miniaturization comprises little belt of stacking gradually from top to bottom 1, first dielectric layer 2, the first metal layer 3, second dielectric layer 4, second metal level 5, the 3rd dielectric layer 6 and the 3rd metal level 7;
Said little belt 1 comprises transmission line main line 10, the first film resistance 11, second film resistor 12, the 3rd film resistor 13, first metallic interconnect 14, second metallic interconnect 15 and the 3rd metallic interconnect 16, and said the first film resistance 11, second film resistor 12, the 3rd film resistor 13 are arranged in order with first metallic interconnect 14, second metallic interconnect 15 with after the 3rd metallic interconnect 16 is connected respectively and are connected on the transmission line main line 10;
Said first dielectric layer 2 comprises first medium substrate 20, first plated-through hole 21, second plated-through hole 22 and the 3rd plated-through hole 23; Said second plated-through hole 22 is positioned at medium substrate 20 centers, and first plated-through hole 21 and the 3rd plated-through hole 23 lay respectively at second plated-through hole, 22 both sides;
Said the first metal layer 3 comprises dummy metal plate 30, first via hole 31, second via hole 32 and the 3rd via hole 33, and said second via hole 32 is positioned at dummy metal plate 30 centers, and first via hole 31 and the 3rd via hole 33 lay respectively at second via hole, 32 both sides;
Said second dielectric layer 4 comprises second medium substrate 40, the first resonant cavity chamber wall 41, the second resonant cavity chamber wall 42, the first metallization counterbore 43, plated-through hole 44 and the second metallization counterbore 45.As shown in Figure 4, the said first resonant cavity chamber wall 41 comprises the first plated-through hole array 410 that stacks gradually from top to bottom, the first metal conduction band 411, the second plated-through hole array 412, the second metal conduction band 413 and the 3rd plated-through hole array 414; The said second resonant cavity chamber wall 42 comprises the first plated-through hole array 420 that stacks gradually from top to bottom, the first metal conduction band 421, the second plated-through hole array 422, the second metal conduction band 423 and the 3rd plated-through hole array 424; Said plated-through hole 44 is positioned at second medium substrate, 40 centers; The first resonant cavity chamber wall 41 and the second resonant cavity chamber wall 42 lay respectively at plated-through hole 44 both sides and are embedded in second medium substrate 40; The said first metallization counterbore 43 and the second metallization counterbore 45 lay respectively at the centermost of the first resonant cavity chamber wall 41 and the second resonant cavity chamber wall 42; Said plated-through hole array (410,412,414) is to arrange along the rectangle outer ring, and spacing is half with spacing between layer metallization via hole hole between the hole of the metallization via hole between adjacent two plated-through hole arrays; The said first plated-through hole array 410 and the second plated-through hole array 412 interconnect through the first metal conduction band 411; The second plated-through hole array 412 and the 3rd plated-through hole array 414 interconnect through the second metal conduction band 413; The order of connection is the first plated-through hole array 410, the first metal conduction band 411, the second plated-through hole array 412, the second metal conduction band 413 and the 3rd plated-through hole array 414 successively from top to bottom; Said second resonant cavity chamber wall 42 structures and the first resonant cavity chamber wall 41 are similar, therefore are not described in detail.
Said second metal level 5 comprises dummy metal plate 50, via hole 51, and said via hole 51 is positioned at dummy metal plate 50 centers,
Said dummy metal plate 50 is that manufacture method is identical with dummy metal plate 30;
Said the 3rd dielectric layer 6 comprises the 3rd medium substrate 60, metallization counterbore 61 resonant cavity chamber walls 62; Said resonant cavity chamber wall 62 comprises the first plated-through hole array 620 that stacks gradually from top to bottom, the first metal conduction band 621, the second plated-through hole array 622, the second metal conduction band 623 and the 3rd plated-through hole array 624; Said resonant cavity chamber wall 62 is embedded in the 3rd medium substrate 60, and metallization counterbore 61 is positioned at wall 62 centers, resonant cavity chamber; Said resonant cavity chamber wall 62 structures and the first resonant cavity chamber wall 41 are similar, therefore are not described in detail.
Said the 3rd metal level 7 comprises metallic plate 70.
Said first plated-through hole 21 passes first via hole 31 and the first metallization counterbore 43 formation probe structure that joins, and this probe structure top and first metallic interconnect 14 join;
Said the 3rd plated-through hole 23 passes the 3rd via hole 33 and the second metallization counterbore 45 formation probe structure that joins, and this probe structure top and the 3rd metallic interconnect 16 join;
Said second plated-through hole 22 passes first via hole 32 and joins with plated-through hole 44, passes via hole 51 and the metallization counterbore 61 formation probe structure that joins again, and this probe structure top and first metallic interconnect 15 join;
As shown in Figure 5, said dummy metal plate 30 adopts matrix grid shape structures, but for simplified structure so that describe, in other accompanying drawings, these matrix grid shape structures are not described in detail out.Therefore dummy metal plate 50 structures and dummy metal plate 30 similar also are not described in detail.
Do a brief description in the face of the operation principle and the process of present embodiment down: energy is flowed into by an end of gain power equalizer; Flow along transmission line main line 10; When energy passes to the first film resistance 11; First resonant cavity (relating to label 30,41,50) resonance frequency and near part energy thereof are passed through film resistor 11, the first metallic interconnects 14, again through passed the probe structure that first via hole 31 and the first metallization counterbore 43 join and form by first plated-through hole 21; In first resonant cavity chamber wall 41, evoke electromagnetic viscosimeter; The energy that coupling is come in is absorbed by film resistor 11, and near the energy non-first resonant cavity resonance frequency and the resonance frequency thereof will not flow through film resistor 11, but continues to advance forward;
When energy passes to second film resistor 12; Second resonant cavity (relating to label 50,62,70) resonance frequency and near part energy thereof are passed through film resistor 12, the first metallic interconnects 15, join with plated-through hole 44 through passed first via hole 32 by second plated-through hole 22 again; Pass via hole 51 and the metallization counterbore 61 formation probe structure that joins again; In resonant cavity chamber wall 62, evoke electromagnetic viscosimeter, the energy that coupling is come in is absorbed by film resistor 12, and near the energy non-second resonant cavity resonance frequency and the resonance frequency thereof will not flow through film resistor 12; But continue to advance forward
When energy passes to second film resistor 13, operation principle and noted earlier similar,
The energy that transmits out along the transmission line main line at last can be implemented in the energy attenuation of the different sizes on the different frequency point.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help the principle of reader understanding's the utility model, should to be understood that the protection range of the utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these teachings of the utility model, and these distortion and combination are still in the protection range of the utility model.
Claims (2)
1. the power gain equalizer of a miniaturization comprises the little belt (1), first dielectric layer (2), the first metal layer (3), second dielectric layer (4), second metal level (5), the 3rd dielectric layer (6) and the 3rd metal level (7) that stack gradually from top to bottom;
Said little belt (1) comprises transmission line main line (10), the first film resistance (11), second film resistor (12), the 3rd film resistor (13), first metallic interconnect (14), second metallic interconnect (15) and the 3rd metallic interconnect (16), and said the first film resistance (11), second film resistor (12), the 3rd film resistor (13) are arranged in order with first metallic interconnect (14), second metallic interconnect (15) with after the 3rd metallic interconnect (16) is connected respectively and are connected on the transmission line main line (10);
Said first dielectric layer (2) comprises first medium substrate (20), first plated-through hole (21), second plated-through hole (22) and the 3rd plated-through hole (23); Said second plated-through hole (22) is positioned at medium substrate (20) center, and first plated-through hole (21) and the 3rd plated-through hole (23) lay respectively at second plated-through hole (22) both sides;
Said the first metal layer (3) comprises dummy metal plate (30), first via hole (31), second via hole (32) and the 3rd via hole (33); Said second via hole (32) is positioned at dummy metal plate (30) center, and first via hole (31) and the 3rd via hole (33) lay respectively at second via hole (32) both sides;
Said second dielectric layer (4) comprises second medium substrate (40), the first resonant cavity chamber wall (41), the second resonant cavity chamber wall (42), the first metallization counterbore (43), plated-through hole (44) and the second metallization counterbore (45), and the said first resonant cavity chamber wall (41) comprises the first plated-through hole array (410), the first metal conduction band (411), the second plated-through hole array (412), the second metal conduction band (413) and the 3rd plated-through hole array (414) that stacks gradually from top to bottom; The said second resonant cavity chamber wall (42) comprises the first plated-through hole array (420), the first metal conduction band (421), the second plated-through hole array (422), the second metal conduction band (423) and the 3rd plated-through hole array (424) that stacks gradually from top to bottom; Said plated-through hole (44) is positioned at second medium substrate (40) center; The first resonant cavity chamber wall (41) and the second resonant cavity chamber wall (42) lay respectively at plated-through hole (44) both sides and are embedded in second medium substrate (40); The said first metallization counterbore (43) and the second metallization counterbore (45) lay respectively at the centermost of the first resonant cavity chamber wall (41) and the second resonant cavity chamber wall (42); Said plated-through hole array (410,412,414) is to arrange along the rectangle outer ring, and spacing is half with spacing between layer metallization via hole hole between the hole of the metallization via hole between adjacent two plated-through hole arrays;
Said second metal level (5) comprises dummy metal plate (50), via hole (51), and said via hole (51) is positioned at dummy metal plate (50) center;
Said the 3rd dielectric layer (6) comprises the 3rd medium substrate (60), metallization counterbore (61) resonant cavity chamber wall (62); Said resonant cavity chamber wall (62) comprises the first plated-through hole array (620), the first metal conduction band (621), the second plated-through hole array (622), the second metal conduction band (623) and the 3rd plated-through hole array (624) that stacks gradually from top to bottom; Said resonant cavity chamber wall (62) is embedded in the 3rd medium substrate (60), and metallization counterbore (61) is positioned at resonant cavity chamber wall (62) center;
Said the 3rd metal level (7) comprises metallic plate (70);
Said first plated-through hole (21) passes first via hole (31) and first metallization counterbore (43) the formation probe structure that joins, and this probe structure top and first metallic interconnect (14) join;
Said the 3rd plated-through hole (23) passes the 3rd via hole (33) and second metallization counterbore (45) the formation probe structure that joins, and this probe structure top and the 3rd metallic interconnect (16) join;
Said second plated-through hole (22) passes first via hole (32) and plated-through hole (44) and joins, and passes via hole (51) and metallization counterbore (61) the formation probe structure that joins again, and this probe structure top and first metallic interconnect (15) join.
2. the power gain equalizer of a kind of miniaturization according to claim 1 is characterized in that, said dummy metal plate (30,50) adopts matrix grid shape structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220171549 CN202585322U (en) | 2012-04-20 | 2012-04-20 | Miniaturized power gain equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220171549 CN202585322U (en) | 2012-04-20 | 2012-04-20 | Miniaturized power gain equalizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202585322U true CN202585322U (en) | 2012-12-05 |
Family
ID=47254707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220171549 Expired - Lifetime CN202585322U (en) | 2012-04-20 | 2012-04-20 | Miniaturized power gain equalizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202585322U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646565A (en) * | 2012-04-20 | 2012-08-22 | 电子科技大学 | Miniaturized power gain balancer |
| CN103956313A (en) * | 2014-05-07 | 2014-07-30 | 电子科技大学 | Miniaturized power gain equalizer |
| CN105161810A (en) * | 2015-09-10 | 2015-12-16 | 电子科技大学 | Low temperature co-fired ceramic (LTCC) miniature power gain equalizer based on composite right/left-handed structure |
-
2012
- 2012-04-20 CN CN 201220171549 patent/CN202585322U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646565A (en) * | 2012-04-20 | 2012-08-22 | 电子科技大学 | Miniaturized power gain balancer |
| CN102646565B (en) * | 2012-04-20 | 2015-02-25 | 电子科技大学 | Miniaturized power gain balancer |
| CN103956313A (en) * | 2014-05-07 | 2014-07-30 | 电子科技大学 | Miniaturized power gain equalizer |
| CN105161810A (en) * | 2015-09-10 | 2015-12-16 | 电子科技大学 | Low temperature co-fired ceramic (LTCC) miniature power gain equalizer based on composite right/left-handed structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Lee et al. | Low-loss LTCC cavity filters using system-on-package technology at 60 GHz | |
| CN103515682B (en) | Multi-step formula substrate integration wave-guide realizes micro-vertical transition structure bringing to waveguide | |
| CN105680133A (en) | Inter-board perpendicular interconnection circuit structure for substrate integrated ridge waveguide | |
| CN104332413A (en) | 3D assembling method for integrally integrating chips of T/R assembly | |
| CN107394328B (en) | A kind of D wave band waveguide to planar circuit transition device | |
| CN106602190A (en) | Multilayer substrate integration waveguide filter with high out-of-band rejection | |
| CN206541917U (en) | A kind of substrate integration wave-guide millimeter wave filter of coated by dielectric | |
| CN202633488U (en) | Resonance type substrate integrated waveguide power synthesizer | |
| CN202019043U (en) | Substrate integrated waveguide filter with steep sideband characteristic | |
| CN100449864C (en) | Substrate integrated waveguide comb-shaped power distributor | |
| CN204905392U (en) | Integrated waveguide filter of dual 14 folding mould substrates | |
| CN102646565B (en) | Miniaturized power gain balancer | |
| CN202585322U (en) | Miniaturized power gain equalizer | |
| CN104752793B (en) | Bandpass filter | |
| CN102377004A (en) | Miniaturized substrate integrated waveguide circulator | |
| CN104218279B (en) | Novel dual-mode band-pass filter based on LTCC (low temperature co-fired ceramics) | |
| CN101888003A (en) | Bandpass filter with LTCC multilayer composite left-and-right-hand transmission line structure | |
| CN110021805A (en) | Based on the three-dimensional transition structure of the air gap waveguide in complicated feed network | |
| CN104201454A (en) | LTCC (Low Temperature Co-Fired Ceramic) miniaturization microwave passive device | |
| CN102354781A (en) | Planar integrated waveguide bandpass filter with quasi-elliptic function type | |
| CN105161810B (en) | LTCC based on composite left-and-right-hand structure minimizes power gain balancer | |
| CN111769348B (en) | Transition structure of asymmetric strip line and microstrip line | |
| CN107039721B (en) | Miniaturization balanced device based on Novel spiral defect sturcture | |
| CN103594761B (en) | Substrate integration wave-guide ferrite switch | |
| Zou et al. | Design of an X-band symmetrical window bandpass filter based on substrate integrated waveguide |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20121205 Effective date of abandoning: 20150225 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20121205 Effective date of abandoning: 20150225 |
|
| RGAV | Abandon patent right to avoid regrant |