CN202548496U - Pixel array substrate - Google Patents
Pixel array substrate Download PDFInfo
- Publication number
- CN202548496U CN202548496U CN2012201394172U CN201220139417U CN202548496U CN 202548496 U CN202548496 U CN 202548496U CN 2012201394172 U CN2012201394172 U CN 2012201394172U CN 201220139417 U CN201220139417 U CN 201220139417U CN 202548496 U CN202548496 U CN 202548496U
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- Prior art keywords
- electrode
- array substrate
- pixel
- picture element
- pixel array
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- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 238000009413 insulation Methods 0.000 claims description 18
- 230000001681 protective effect Effects 0.000 claims description 10
- 230000009977 dual effect Effects 0.000 claims description 6
- 230000008878 coupling Effects 0.000 abstract description 14
- 238000010168 coupling process Methods 0.000 abstract description 14
- 238000005859 coupling reaction Methods 0.000 abstract description 14
- 230000000694 effects Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
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- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The utility model discloses a pixel array substrate, including a base plate, many scanning lines, many data lines, many sharing lines, a plurality of pixel unit and a plurality of electrode that shields. The scanning lines, the data lines and the sharing lines are all arranged on the substrate. The data lines and the scanning lines are staggered to divide a plurality of pixel areas on the plane of the substrate. Each pixel unit is disposed in one of the pixel regions and includes a pixel electrode. Each pixel electrode has a first side edge, and the first side edge between two adjacent scan lines faces one of the scan lines. The shielding electrodes are respectively arranged in the pixel regions and are positioned between the pixel electrodes and the substrate. Each shielding electrode protrudes out of one of the first side edges and is electrically insulated from the sharing line, the scanning line and the data line. The utility model discloses a during the operation of pixel array substrate, can reduce to take place the picture quality because of receiving the destroyed situation of coupling capacitance's influence.
Description
Technical field
The utility model relates to a kind of element of display, and particularly relevant for a kind of pixel array substrate (pixel array substrate).
Background technology
Present some large scale or high-resolution LCD (Liquid Crystal Display; LCD) has a large amount of sweep trace (scan line); And the LCD of this type can once drive many adjacent sweep traces when running; With open a plurality of thin film transistor (TFT)s (Thin-Film Transistor, TFT).Can increase the duration of charging of the pairing liquid crystal capacitance of each pixel electrode (pixel electrode) (liquid crystal capacitance) like this, and then reduce the situation that the liquid crystal capacitance undercharge takes place.
In above-mentioned LCD, the two can form coupling capacitance each pixel electrode and the sweep trace that is adjacent, and said coupling capacitance can influence the gray scale voltage that pixel electrode produces.When LCD operated, some sweep traces can be driven, and came liquid crystal capacitance is charged so that some pixel electrodes produce gray scale voltage.Yet, at this moment, still have other sweep trace not driven, so the quantity of electric charge that said coupling capacitance had and inconsistent.This may cause pixel electrode to produce wrong gray scale voltage, destroys the image quality of LCD.
The utility model content
In view of this, the fundamental purpose of the utility model is to provide a kind of pixel array substrate that can reduce coupling capacitance to the influence of gray scale voltage.
For achieving the above object, the utility model proposes a kind of pixel array substrate, and it comprises a substrate, multi-strip scanning line, many data lines, many common lines, a plurality of picture elements unit, an insulation course and a plurality of shielding electrodes.Substrate has a plane.Said sweep trace is arranged side by side each other, and is configured on this plane; And said data line is arranged side by side each other, and is configured on this plane; Said data line and said sweep trace are staggered, mark off a plurality of picture elements zone in the plane.Said common lines and said sweep trace are arranged side by side, and configuration in the plane.In picture element zone, each picture element unit also comprises a picture element switch, a pixel electrode and a conductive pole to each picture element configuration of cells therein.Said picture element switch electrically connects said sweep trace and said data line.Said conductive pole is connected between said picture element switch and the said pixel electrode, and wherein each pixel electrode has a first side edge, and the said first side edge between adjacent two sweep traces is all towards sweep trace wherein.Insulation course is configured between said pixel electrode and the plane, and covers said sweep trace, said data line, said common lines and said picture element switch.Said conductive pole is configured in the insulation course.Said shielding electrode is configured in respectively in the said picture element zone, and between said pixel electrode and plane.Said shielding electrode is overlapped with said pixel electrode respectively, and wherein each shielding electrode protrudes from one of them first side edge, and said shielding electrode all is electrically insulated with said common lines, said sweep trace and said data line.
In the utility model one embodiment, above-mentioned pixel array substrate more comprises a protective seam.Protective seam is configured between plane and the insulation course, and covers said sweep trace and said common lines, and wherein said shielding electrode is configured between protective seam and the insulation course.
In the utility model one embodiment, the quantity of the shielding electrode in each picture element zone is one.
In the utility model one embodiment, the quantity of the shielding electrode in each picture element zone is a plurality of.
In the utility model one embodiment, each pixel electrode has more a pair of second side respect to one another edge, and the first side edge is connected between these two second side edge.One of them shielding electrode in the same picture element zone protrudes from this two second side edge.
In the utility model one embodiment, above-mentioned pixel array substrate more comprises a plurality of capacitance electrodes.Said capacitance electrode is configured in respectively in the said picture element zone, and connects said common lines.Insulation course more covers said capacitance electrode, and each capacitance electrode and one of them pixel electrode are overlapped.
In the utility model one embodiment, each pixel electrode has more a pair of second side respect to one another edge, and the first side edge is connected between these two second side edge.Each capacitance electrode protrudes from one of them second side edge.
In the utility model one embodiment, the quantity of the capacitance electrode in each picture element zone is a plurality of.
In the utility model one embodiment, each bar common lines has relative dual side-edge, and said capacitance electrode protrudes from one of them side of said common lines.
In the utility model one embodiment, above-mentioned each bar common lines has relative dual side-edge, and said capacitance electrode protrudes from the said side of said common lines.
In the utility model one embodiment, the quantity of the shielding electrode in each picture element zone is a plurality of.In same picture element zone, capacitance electrode is between said shielding electrode.
In the utility model one embodiment, each pixel electrode has more a pair of second side respect to one another edge, and the first side edge is connected between these two second side edge.The shape of said shielding electrode is annular, and each shielding electrode protrudes from first side edge and this two second side edge of one of them pixel electrode.
Based on above-mentioned; When the pixel array substrate of the utility model operates; Said shielding electrode can produce electric field shielding effect (electric field shielding effect); And then can reduce the influence of pixel electrode and the two formed coupling capacitance of sweep trace to gray scale voltage, to reduce image quality takes place because of the ruined situation of the influence that receives coupling capacitance.
Description of drawings
Figure 1A is the schematic top plan view of the pixel array substrate of the utility model one embodiment;
Figure 1B is the diagrammatic cross-section of being drawn along I-I line section among Figure 1A;
Fig. 2 is the schematic top plan view of the pixel array substrate of another embodiment of the utility model;
Fig. 3 is the schematic top plan view of the pixel array substrate of the another embodiment of the utility model.
Description of reference numerals
100,200,300 pixel array substrates
110 substrates
112 planes
The 120c common lines
The 120d data line
The 120s sweep trace
130 picture element unit
132 picture element switches
134 pixel electrodes
136 conductive poles
140 insulation courses
150,350 shielding electrodes
160 protective seams
170,270 capacitance electrodes
The C1 channel layer
The D1 drain electrode
E1 first side edge
E2 second side edge
The E3 side
The G1 grid
P1 picture element zone
The S1 source electrode.
Embodiment
For letting the above-mentioned feature and advantage of the utility model can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended accompanying drawing, elaborates as follows.
Figure 1A is the schematic top plan view of the pixel array substrate of the utility model one embodiment, and Figure 1B is the diagrammatic cross-section of being drawn along I-I line section among Figure 1A.See also Figure 1A and Figure 1B, the pixel array substrate 100 of present embodiment comprises a substrate 110, multi-strip scanning line 120s, many data line 120d and many common lines 120c.Substrate 110 has a plane 112, and said sweep trace 120s, data line 120d and common lines 120c all are configured on the plane 112.
Said data line 120d is arranged side by side each other, and said sweep trace 120s is arranged side by side each other, and wherein said data line 120d and said sweep trace 120s are staggered, on plane 112, to mark off a plurality of picture elements zone P1.In detail, said data line 120d and said sweep trace 120s are netted arrangement, thereby form a plurality of grids (lattice), and wherein grid is picture element zone P1, shown in Figure 1A.
Said common lines 120c and said sweep trace 120s are arranged side by side, and each bar sweep trace 120s can be between adjacent two common lines 120c, so common lines 120c can pass a plurality of picture elements zone P1.In addition, common lines 120c and sweep trace 120s the two can be by being made with skim layer.For example, common lines 120c and sweep trace 120s the two can be by with one deck metal level after little shadow (photolithography) and etching (etching) and form.Therefore, constituting the two material of common lines 120c and sweep trace 120s all can be identical.
Said picture element switch 132 electrically connects said sweep trace 120s and said data line 120d.In detail; Each picture element switch 132 can be field-effect transistor (Field-Effect Transistor; FET), and can comprise one source pole S1, a drain D 1, a grid G 1 and a channel layer C1, wherein source S 1, drain D 1 and channel layer C1 all are positioned at the top of grid G 1; And channel layer C1 is between grid G 1 and source S 1, with and grid G 1 and drain D 1 between.In addition, channel layer C1 can be a kind of semiconductor layer.
In same picture element unit 130, grid G 1 connects sweep trace 120s, and can be one-body molded with sweep trace 120s.In detail, grid G 1 and sweep trace 120s the two can be by being made with skim layer, for example grid G 1 and sweep trace 120s the two can by with one deck metal level after little shadow and etching and form.Source S 1 connects data line 120d, and drain D 1 connects conductive pole 136.
When multi-strip scanning line 120s drove, a plurality of picture element switches 132 that the sweep trace 120s that has driven is electrically connected can be unlocked.At this moment, the GTG signal that data line 120d is exported can input to the source S 1 of the said picture element switch of having opened 132, and passes through channel layer C1, drain D 1 and conductive pole 136 in regular turn.Afterwards, the GTG signal is passed to pixel electrode 134, thereby produces gray scale voltage.
Said shielding electrode 150 is overlapped with said pixel electrode 134 respectively.Each pixel electrode 134 has a first side edge E1 and a pair of second side edge E2 respect to one another.In each pixel electrode 134, first side edge E1 is connected between the said second side edge E2, and each shielding electrode 150 protrudes from one of them first side edge E1.
Said shielding electrode 150 all is electrically insulated with said common lines 120c, said sweep trace 120s and said data line 120d; And the said first side edge E1 between adjacent two sweep trace 120s all can be towards sweep trace 120s wherein, so shielding electrode 150 can be configured in wherein between a sweep trace 120s and one of them pixel electrode 134.
In addition, pixel array substrate 100 can more comprise a protective seam 160, shown in Figure 1B.Protective seam 160 is configured between plane 112 and the insulation course 140; And cover said sweep trace 120s and said common lines 120c, and the source S 1 of said shielding electrode 150 and said picture element switch 132 and drain D 1 are all configurable between protective seam 160 and insulation course 140.Shielding electrode 150, source S 1 and drain D 1 three can be by being made with skim layer, for example be by with one deck metal level after little shadow and etching and form, the material that therefore constitutes shielding electrode 150, source S 1 and drain D 1 three all can be identical.
In the present embodiment, pixel array substrate 100 can more comprise a plurality of capacitance electrodes 170, and wherein said capacitance electrode 170 is configured in respectively in the said picture element zone P1, and the quantity of the capacitance electrode 170 in the P1 of each picture element zone can be a plurality of.With Figure 1A is example, and the quantity of the capacitance electrode 170 in the P1 of each picture element zone is two.In addition, each capacitance electrode 170 is positioned at the below of pixel electrode 134, and overlaps with pixel electrode 134, and wherein each capacitance electrode 170 protrudes from one of them second side edge E2.
Said capacitance electrode 170 can be configured on the plane 112, and capacitance electrode 170 and common lines 120c the two can be by being made with skim layer.For example; Capacitance electrode 170 and common lines 120c the two can be by with one deck metal level after little shadow and etching and form; Therefore constituting the two material of capacitance electrode 170 and common lines 120c all can be identical, and insulation course 140 more covers said capacitance electrode 170.In addition and since sweep trace 120s and common lines 120c the two can be by being made with skim layer, so capacitance electrode 170, sweep trace 120s and common lines 120c three more can be by being made with skim layer.
Said capacitance electrode 170 connects said common lines 120c, so that capacitance electrode 170 electrically conducts with its common lines 120c that is connected.In the embodiment shown in Figure 1A, each bar common lines 120c has relative dual side-edge E3, and said capacitance electrode 170 protrudes from one of them side E3 of said common lines 120c.In other words, in same common lines 120c, 170 of a plurality of capacitance electrodes connect one of them side E3, and do not connect another side E3.
Because common lines 120c and capacitance electrode 170 are all overlapping with pixel electrode 134; Common lines 120c, capacitance electrode 170 in the therefore same picture element zone P1 can form a kind of storage capacitors (storage capacitances claims Cst again) that is used to keep gray scale voltage with pixel electrode 134 threes.In addition, above-mentioned storage capacitors can be that framework is in shared online storage capacitors (Cst on common).
Fig. 2 is the schematic top plan view of the pixel array substrate of another embodiment of the utility model.See also Fig. 2; Pixel array substrate 200 and pixel array substrate 100 the two structural similarity of present embodiment; Effect is identical; For example pixel array substrate 200 also comprises elements such as sweep trace 120s, data line 120d, common lines 120c and picture element unit 130, and the two cross-section structure of pixel array substrate 200,100 is very similar.Therefore, below will mainly introduce the two difference of pixel array substrate 100,200, and only cooperate Fig. 2 to carry out detailed explanation, no longer repeat to introduce the two identical technical characterictic and effect.
The two difference of pixel array substrate 100,200 comprises the quantity of the shielding electrode 150 in the P1 of each picture element zone, and the included a plurality of capacitance electrodes 270 of pixel array substrate 200 and many common lines 120c connected mode between the two.In detail; In the present embodiment; The quantity of the shielding electrode 150 in the P1 of each picture element zone is a plurality of; And in same picture element zone P1, one of them shielding electrode 150 protrudes from two second side edge E2 of pixel electrode 134, and another shielding electrode 150 then protrudes from first side edge E1.
Each capacitance electrode 270 is positioned at the below of pixel electrode 134, and capacitance electrode 270 and common lines 120c the two can be by being made with skim layer.Capacitance electrode 270 is overlapped with pixel electrode 134, and wherein each capacitance electrode 270 protrudes from one of them second side edge E2.In addition, in the P1 of same picture element zone, said capacitance electrode 270 can be between said shielding electrode 150, and is as shown in Figure 2.
Capacitance electrode 270 and the common lines 120c connected mode between the two is different from the connected mode between the two of capacitance electrode 170 and common lines 120c in the previous embodiment.In detail, in the present embodiment, said capacitance electrode 270 protrudes from the dual side-edge E3 of said common lines 120c.That is to say that in same common lines 120c, some capacitance electrodes 270 connect one of them side E3, and other capacitance electrodes 270 connect another side E3, as shown in Figure 2.
Fig. 3 is the schematic top plan view of the pixel array substrate of another embodiment of the utility model.See also Fig. 3; The pixel array substrate 300 of present embodiment is similar with pixel array substrate 100; For example pixel array substrate 300 also comprises sweep trace 120s, data line 120d, common lines 120c and picture element unit 130; And the two cross-section structure of pixel array substrate 300,100 is very similar, will mainly introduce the two difference of pixel array substrate 100,300 below therefore, no longer repeats to introduce the two identical technical characterictic and effect; Do not illustrate the cross-section structure of pixel array substrate 300 yet, and only cooperate Fig. 3 to carry out detailed explanation.
In detail; The two main difference of pixel array substrate 300,100 is: a plurality of shielding electrodes 350 that pixel array substrate 300 is included; Its shape is annular; Wherein each shielding electrode 350 is not only overlapped with one of them pixel electrode 134, and protrudes from first side edge E1 and two second side edge E2 of pixel electrode 134, and is as shown in Figure 3.
In addition, in the embodiment shown in fig. 3, pixel array substrate 300 can not comprise the capacitance electrode 170,270 in any previous embodiment.But; Common lines 120c is still overlapped with pixel electrode 134; Therefore even pixel array substrate 300 does not comprise any capacitance electrode 170,270, the two still can be formed for keeping the storage capacitors of gray scale voltage the common lines 120c in the same picture element zone P1 and pixel electrode 134.
In sum, the included shielding electrode of the pixel array substrate of the utility model can produce the electric field shielding effect in pixel electrode and the two formed coupling capacitance of sweep trace.So, the utility model can reduce the influence of coupling capacitance to gray scale voltage, impels pixel electrode to produce suitable gray scale voltage, image quality takes place because of the ruined situation of the influence that receives coupling capacitance to reduce.
Though the utility model discloses as above with previous embodiment; Right its is not in order to qualification the utility model, and any people who is familiar with alike technology is in spirit that does not break away from the utility model and scope; The equivalence of doing to change with retouching is replaced, and still is in the scope of patent protection of the utility model.
Claims (12)
1. pixel array substrate is characterized in that it comprises:
One substrate has a plane;
The multi-strip scanning line, arranged side by side each other, and be configured on this plane;
Many data lines, arranged side by side each other, and be configured on this plane, said data line and said sweep trace are staggered, on this plane, mark off a plurality of picture elements zone;
Many common lines, arranged side by side with said sweep trace, and be configured on this plane;
A plurality of picture elements unit; Respectively this picture element configuration of cells is therein in picture element zone; Each picture element unit comprises a picture element switch, a pixel electrode and a conductive pole, and said picture element switch electrically connects said sweep trace and said data line, and said conductive pole is connected between said picture element switch and the said pixel electrode; Wherein respectively this pixel electrode has a first side edge, and the said first side edge between adjacent two sweep traces is all towards sweep trace wherein;
One insulation course is configured between said pixel electrode and this plane, and covers said sweep trace, said data line, said common lines and said picture element switch, and wherein said conductive pole is configured in this insulation course; And
A plurality of shielding electrodes; Be configured in respectively in the said picture element zone; And between said pixel electrode and this plane; Said shielding electrode is overlapped with said pixel electrode respectively, and wherein respectively this shielding electrode protrudes from one of them first side edge, and said shielding electrode all is electrically insulated with said common lines, said sweep trace and said data line.
2. pixel array substrate as claimed in claim 1; It is characterized in that; This pixel array substrate more comprises a protective seam; This protective seam is configured between said plane and the said insulation course, and covers said sweep trace and common lines, and wherein said shielding electrode is configured between this protective seam and the said insulation course.
3. pixel array substrate as claimed in claim 1 is characterized in that, the quantity of the said shielding electrode in each said picture element zone is one.
4. pixel array substrate as claimed in claim 1 is characterized in that, the quantity of the said shielding electrode in each said picture element zone is a plurality of.
5. pixel array substrate as claimed in claim 4; It is characterized in that; Each said pixel electrode has more a pair of second side respect to one another edge; And said first side edge is connected between these two second side edge, and one of them shielding electrode in the same picture element zone protrudes from this two second side edge.
6. pixel array substrate as claimed in claim 1; It is characterized in that; This pixel array substrate more comprises a plurality of capacitance electrodes, and said capacitance electrode is configured in respectively in the said picture element zone, and connects said common lines; Said insulation course more covers said capacitance electrode, and respectively this capacitance electrode and one of them pixel electrode are overlapped.
7. pixel array substrate as claimed in claim 6; It is characterized in that; Each said pixel electrode has more a pair of second side respect to one another edge, and said first side edge is connected between these two second side edge, and each said capacitance electrode protrudes from one of them second side edge.
8. pixel array substrate as claimed in claim 6 is characterized in that, the quantity of the said capacitance electrode in each said picture element zone is a plurality of.
9. pixel array substrate as claimed in claim 6 is characterized in that, each said common lines has relative dual side-edge, and said capacitance electrode protrudes from one of them side of said common lines.
10. pixel array substrate as claimed in claim 6 is characterized in that, each said common lines has relative dual side-edge, and said capacitance electrode protrudes from the said side of said common lines.
11. pixel array substrate as claimed in claim 10 is characterized in that, the quantity of the said shielding electrode in each said picture element zone is a plurality of, and in same picture element zone, said capacitance electrode is between said shielding electrode.
12. pixel array substrate as claimed in claim 1; It is characterized in that; Each said pixel electrode has more a pair of second side respect to one another edge; And said first side edge is connected between these two second side edge, and the shape of said shielding electrode is annular, and each said shielding electrode protrudes from said first side edge and this two second side edge of one of them pixel electrode.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101200225U TWM432061U (en) | 2012-01-05 | 2012-01-05 | Pixel array substrate |
| TW101200225 | 2012-01-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202548496U true CN202548496U (en) | 2012-11-21 |
Family
ID=46723866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012201394172U Expired - Fee Related CN202548496U (en) | 2012-01-05 | 2012-04-05 | Pixel array substrate |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2013140366A (en) |
| CN (1) | CN202548496U (en) |
| TW (1) | TWM432061U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112908156A (en) * | 2019-12-04 | 2021-06-04 | 友达光电股份有限公司 | Pixel array substrate |
| US11705462B2 (en) | 2019-08-20 | 2023-07-18 | Au Optronics Corporation | Electronic device |
| DE112020003935B4 (en) | 2019-08-20 | 2023-08-17 | Au Optronics Corporation | ELECTRONIC DEVICE |
| DE112020003936B4 (en) | 2019-08-20 | 2023-09-28 | Au Optronics Corporation | Electronic device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI595299B (en) * | 2014-01-23 | 2017-08-11 | 元太科技工業股份有限公司 | Pixel array |
| TWI733462B (en) * | 2019-12-04 | 2021-07-11 | 友達光電股份有限公司 | Pixel array substrate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3210437B2 (en) * | 1991-09-24 | 2001-09-17 | 株式会社東芝 | Liquid crystal display |
| TWI329775B (en) * | 2007-03-27 | 2010-09-01 | Au Optronics Corp | Pixel structure and manufacturinf method thereof |
| JP2009003328A (en) * | 2007-06-25 | 2009-01-08 | Mitsubishi Electric Corp | Display device and its manufacturing method |
| KR101443380B1 (en) * | 2007-11-23 | 2014-09-26 | 엘지디스플레이 주식회사 | Liquid crystal display device |
-
2012
- 2012-01-05 TW TW101200225U patent/TWM432061U/en not_active IP Right Cessation
- 2012-04-05 CN CN2012201394172U patent/CN202548496U/en not_active Expired - Fee Related
-
2013
- 2013-01-04 JP JP2013000251A patent/JP2013140366A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11705462B2 (en) | 2019-08-20 | 2023-07-18 | Au Optronics Corporation | Electronic device |
| DE112020003935B4 (en) | 2019-08-20 | 2023-08-17 | Au Optronics Corporation | ELECTRONIC DEVICE |
| DE112020003936B4 (en) | 2019-08-20 | 2023-09-28 | Au Optronics Corporation | Electronic device |
| CN112908156A (en) * | 2019-12-04 | 2021-06-04 | 友达光电股份有限公司 | Pixel array substrate |
| CN112908156B (en) * | 2019-12-04 | 2022-09-16 | 友达光电股份有限公司 | Pixel array substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| TWM432061U (en) | 2012-06-21 |
| JP2013140366A (en) | 2013-07-18 |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121121 Termination date: 20200405 |
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| CF01 | Termination of patent right due to non-payment of annual fee |