CN202502355U

CN202502355U - Time hack device

Info

Publication number: CN202502355U
Application number: CN2012201140157U
Authority: CN
Inventors: 左伟杰; 李威鹏; 宋德祥; 赵景芳; 雷文鹤; 宋运隆; 程勇; 王学强
Original assignee: THINKHI
Current assignee: THINKHI
Priority date: 2012-03-23
Filing date: 2012-03-23
Publication date: 2012-10-24
Anticipated expiration: 2022-03-23

Abstract

The utility model relates to a time hack device, comprising a first master clock and a second master clock. The first master clock and the second master clock are used for respectively receiving radio time reference signals and are composed of CPU plug-in units, power supply plug-in units, APU plug-in units, EXT-L plug-in units and EXT-E plug-in units. All the plug-in units of the two clocks are arranged on a substrate; and an IRIG-B input port and an IRIG-B output port of the CPU plug-in unit of the first master clock are respectively connected with an IRIG-B output port and an IRIG-B input port of the CPU plug-in unit of the second master clock. Any one of the clocks can receive information of the other clock so as to carry out mutual detection and mutual standby. According to the utility model, the utilization of the time hack device can realize functions of two time hack devices, thereby saving the cost and the occupied space.

Description

A kind of to the time device

Technical field

The utility model relate to a kind of electric system accurately to the time device, particularly satisfy in the Power System Intelligent transformer station requirement to the synchro system high reliability.

Background technology

Along with the fast development of electric system, urgent day by day to the requirement of time synchronized, need accurately, safety, clock source reliably, for all kinds of operational outfits of electric system provide the precise time benchmark.To the time struggle against global position system (BD), Global Positioning System (GPS) (GPS) etc. to the north of the device as wireless clock source; With the IRIG-B sign indicating number is wired time source, is aided with punctual function, and coming provides needed various forms of time service output for electric system; Form the electric system clock synchronization system; The electric system clock synchronization system is that scheduling at different levels mechanism, generating plant, transformer station, collection control center of China's electrical network etc. provides the unified time benchmark, to satisfy the requirement to time synchronized of various systems and equipment, guarantees the real-time data acquisition time consistency; Thereby improve the level of power grid accident analysis and stable control, improve operation of power networks efficient and reliability.

To the time device constitute by a major clock, the major clock hardware configuration is as shown in Figure 1, comprises power insert, CPU card, APU plug-in unit, EXT-L plug-in unit (optical interface output), EXT-E plug-in unit (electrical interface output).The ANT mouth of APU plug-in unit is the access port of GPS or Big Dipper antenna, is the BNC mouth; The IRIG-B port of APU plug-in unit be used to receive wired to the time signal.EXT-L plug-in unit, EXT-E plug-in unit are used to export light/electrical clock signal.In order to improve reliability, adopt redundant mode on the engineering, as shown in Figure 2, with two to the time device realize mutually fully.This mode has increased cost, takes up room again.

The utility model content

The purpose of the utility model provide a kind of to the time device, only just can realize the redundant function that is equipped with system mutually, with solution prior art cost height, big problem takes up room with an equipment.

For realizing above-mentioned purpose; The scheme of the utility model is: a kind of to the time device; Comprise first major clock and second major clock that are used for receiving respectively the wireless time reference signal; First major clock and second major clock constitute by CPU card, power insert, APU plug-in unit, EXT-L plug-in unit and EXT-E plug-in unit, and each plug-in unit of two clocks is arranged on the substrate; IRIG-B output, the input port of the CPU card that the IRIG-B input of the CPU card of first major clock, output port connect second major clock respectively.

The IRIG-B input of first major clock, output port connect IRIG-B output, the input port of second major clock through optical fiber.

The utility model to the time device integrated two major clocks; The hardware configuration of each major clock is identical with existing major clock; IRIG-B input, the output port correspondence of two major clocks (CPU card) are coupled together; Major clock can receive the information of another major clock arbitrarily, to examine mutually and to be equipped with mutually.With one to the time device realize original two to the time device function, provide cost savings and take up room.

Description of drawings

Fig. 1 be prior art to the time device port synoptic diagram;

Fig. 2 is the synchro system synoptic diagram of existing redundant fashion;

Fig. 3 be the utility model to the time device port synoptic diagram;

Fig. 4 is the structural representation of the utility model.

Embodiment

Below in conjunction with accompanying drawing the utility model is done further detailed explanation, in the description, major clock also abbreviates clock as.

As Fig. 3, shown in Figure 4 to the time device, comprise two cover major clocks, major clock A and major clock B.Every cover major clock comprises power insert, CPU card, APU plug-in unit, EXT-L plug-in unit (optical interface output), EXT-E plug-in unit (electrical interface output).The IRIG-B input of the CPU card of major clock A, output port connect IRIG-B output, the input port of the CPU card of major clock B respectively through optical fiber.Each plug-in unit of two clocks is arranged on the substrate.Every cover major clock can receive wireless time reference signal (GPS or Big Dipper signal) and wired time reference signal (benchmark IRIG-B coded signal).When device and satellite-signal were synchronous, device output signal was benchmark with the satellite-signal, when with the satellite-signal step-out, is normal operating conditions like the IRIG-B sign indicating number that receives, and adopting the IRIG-B sign indicating number is reference signal; When two reference signals are all lost,, will get into punctual hold mode like synchronous mistake once.Arbitrarily clock can receive another clock to the time information, to be equipped with the IRIG-B temporal information of clock mutually complete when self satellite-signal is bad, then can adopt when being equipped with clock information mutually and continuing accurately to walk.During normal operation, inspection is equipped with the IRIG-B sign indicating number information of clock mutually, and judges whether the punctual edge of IRIG-B sign indicating number is timely normal along at interval, when undesired, sends the mutual warning information that is equipped with through the GOOSE net.

Detecting method is following mutually: two table apparatus clock A and clock B form redundant mutual being equipped with.With the A clock is example, and A receives the IRIG-B sign indicating number information of B, and the start bit of record two continuous frames IRIG-B sign indicating number is t1, t2 constantly, and whether the difference of judging t1 and t2 in setting-up time, if, think that then another clock is undesired above setting-up time, otherwise normally.A begins counting from first start element that receives B, judges whether the code element receive is the start element of next frame, is not accumulated counts then; Be then to continue next step to judge the count value size; If it is normal that this count value within X ± 20 scopes, then is equipped with mutually, light mutually pilot lamp fully; If this count value is not within X ± 20 scopes, then closure is equipped with alarm relay mutually, and through GOOSE net transmission B clock warning information.In like manner, B receives the IRIG-B sign indicating number information of A, and judgment mode is identical.Wherein X is the stored counts value in 1 second of 100M crystal oscillator after GPS pulse per second (PPS) calibration.

Claims

One kind to the time device; It is characterized in that; Comprise first major clock and second major clock that are used for receiving respectively the wireless time reference signal; First major clock and second major clock constitute by CPU card, power insert, APU plug-in unit, EXT-L plug-in unit and EXT-E plug-in unit, and each plug-in unit of two clocks is arranged on the substrate; IRIG-B output, the input port of the CPU card that the IRIG-B input of the CPU card of first major clock, output port connect second major clock respectively.
2. according to claim 1 a kind of to the time device, it is characterized in that the IRIG-B of first major clock input, output port connect IRIG-B output, the input port of second major clock through optical fiber.