CN202495917U - CMOS clock generating circuit without using crystal oscillator - Google Patents
CMOS clock generating circuit without using crystal oscillator Download PDFInfo
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- CN202495917U CN202495917U CN2012200987310U CN201220098731U CN202495917U CN 202495917 U CN202495917 U CN 202495917U CN 2012200987310 U CN2012200987310 U CN 2012200987310U CN 201220098731 U CN201220098731 U CN 201220098731U CN 202495917 U CN202495917 U CN 202495917U
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Abstract
The utility model relates to a CMOS clock generating circuit without using a crystal oscillator. The CMOS clock generating circuit comprises a numerically controlled oscillator, an electric level conversion module, a programmable frequency divider, a duty cycle correcting circuit, a frequency locking module and a non-volatile memory, wherein the numerically controlled oscillator generates and outputs high-frequency sinusoidal oscillation signals, the electric level conversion module receives the high-frequency sinusoidal oscillation signals and outputs square signals outputted in a single-ended mode, the programmable frequency divider outputs clock signals provided with predetermined frequency obtained by decreasing the frequency of the square signals, the duty cycle correcting circuit outputs adjusted clock signals whose duty cycles meet requirements of a predetermined clock on duty cycle; and the frequency locking module is connected to an external crystal oscillator in a process of setting frequency locking control information and outputs frequency locking control information corresponding to output signals of the external crystal oscillator and output signals of the programmable frequency divider. The CMOS clock generating circuit provided by the utility model enables the clock generating circuit to be smaller in size and lower in power consumption, and can be realized in a chip by using a low cost CMOS technology, thereby improving the integration level and stability of a system and reducing implementation cost and power consumption of the system.
Description
Technical field
The utility model relates to the clock generating technology, particularly relates to no crystal oscillator cmos clock and produces circuit.
Background technology
Clock signal is very important for a lot of electronic products, and each element in the electronic product can collaborative work under the effect of clock signal.
At present, the clock generating mode mainly comprises following three kinds:
Mode one, utilize phase-locked loop (Phase Lock Loop, PLL) frequency synthesizer clocking.An object lesson of phase-locked loop frequency integrator is as shown in Figure 1.
Phase-locked loop frequency integrator among Fig. 1 mainly comprises: crystal oscillator, frequency divider (comprising the programmable frequency divider among Fig. 1), phase frequency detector, charge pump, low pass filter and voltage controlled oscillator.Phase frequency detector is two phase of input signals relatively, and produce the voltage that phase difference therewith is directly proportional.High fdrequency component and noise in the above-mentioned voltage of low pass filter filters out are to increase the stability of system.Voltage controlled oscillator receives voltage control, the output corresponding clock signals, and the frequency of this clock signal is the multiple of crystal oscillator frequency normally, like integral multiple or little several times.
Mode two, utilize bulk acoustic wave piezo-electric resonator clocking.
The bulk acoustic wave piezo-electric resonator has very high Q value (can reach 48000); Can produce the good oscillator signal of quality (as the phase noise of the clock signal of 10MHz for-125dBc/Hz1kHz); And can pass through MEMS (Micro-electromechanical System, MEMS) technology is embedded into the bulk acoustic wave piezo-electric resonator in the encapsulation of chip.
Mode three, utilize the FBAR clocking.
FBAR (FBAR, Film Bulk Acoustic Resonator) has utilized the physical characteristic of piezoelectric membrane, and Q value higher (usually greater than 1000) not only can produce the good oscillator signal of quality, and power consumption is very low.In addition, FBAR also have higher operating frequency (as＞5GHz), lower temperature coefficient and can adopt characteristics such as IC (integrated circuit) technology.
The inventor finds in realizing the utility model process: there is problem such as realization and power consumption height outside the sheet in aforesaid way one; Concrete, along with the development of large scale integrated circuit technology, the integrated level of chip is increasingly high, and area of chip is more and more littler, and crystal oscillator adopts the outer mode that realizes of sheet usually; Yet the outer implementation of sheet can influence area, cost and the reliability of system; In addition, the power consumption of crystal oscillator and adjunct circuit thereof is not low, thereby becomes a development bottleneck of low-power consumption product.MEMS in the aforesaid way two technology is incompatible with the integrated circuit CMOS technology of main flow at present, has the high and problem such as be of limited application of cost of manufacture.Though aforesaid way three can adopt IC technology, because piezoelectric membrane needs some special materials such as AIN, ZnO to make, therefore, with standard CMOS process flow process and incompatible; In addition, FBAR is the same with the bulk acoustic wave piezo-electric resonator, though can be embedded in the encapsulation of chip, is difficult to the real integrated comprehensively of realization system.
The utility model content
The purpose of the utility model is; Overcome the problem that existing clock generating technology exists, and provide a kind of no crystal oscillator cmos clock to produce circuit, technical problem to be solved is; Make the volume of the clock generation circuit that high accurate clock signal can be provided littler and power consumption is lower; And can utilize cheaply that the CMOS technology realizes in chip, thereby further improve the integrated level and the stability of system, and the reduction system realizes cost and power consumption.
The purpose of the utility model and solve its technical problem and can adopt following technical scheme to realize.
A kind of no crystal oscillator cmos clock that proposes according to the utility model produces circuit, comprising: digital controlled oscillator, export the high frequency pure oscillation signal of its generation; Level switch module is connected with said digital controlled oscillator, receives said high frequency pure oscillation signal and exports the square-wave signal of the single-ended mode output that said high frequency pure oscillation conversion of signals is; Programmable frequency divider is connected with said level switch module, receives said square-wave signal, and exports the clock signal with preset frequency after the said square-wave signal down conversion process; Duty-cycle correction circuit is connected with said programmable frequency divider, receives said clock signal, and output duty cycle satisfies the adjusted clock signal that the predetermined clock duty ratio requires; The frequency lock module; Be connected with said programmable frequency divider; And in the process that the frequency lock control information is set; Said frequency lock module also is connected with external crystal-controlled oscillation, and said frequency lock module receives the output signal of said external crystal-controlled oscillation and the output signal of said programmable frequency divider, and exports the frequency lock control information of the variable capacitance array of the corresponding said digital controlled oscillator of control of two said output signal frequency differences; Non-volatility memorizer is connected respectively with digital controlled oscillator with said frequency lock module, receives the frequency lock control information of the said frequency lock module output of storage, and to said digital controlled oscillator said frequency lock control information is provided.
The purpose of the utility model and solve its technical problem and can also adopt following technical measures to come further to realize.
Preferable, aforesaid no crystal oscillator cmos clock produces circuit, and wherein said digital controlled oscillator comprises: metal-oxide-semiconductor Mn1, Mn2, Mp1, Mp2 and Mp3, LC resonant slots and frequency self calibration module; Said metal-oxide-semiconductor Mn1, Mn2, Mp1 and Mp2 form the cross-couplings unit that said LC resonant slots provides the negative resistance energy; Said metal-oxide-semiconductor Mp3 is connected with said cross-couplings unit; Said LC resonant slots comprises: inductance, fixed capacity, one group are controlled by the variable capacitance array of frequency self calibration module and the variable capacitance array that another group is controlled by said frequency lock control information, and said inductance, fixed capacity and two groups of variable capacitance arrays are connected with said cross-couplings unit respectively.
Preferable, aforesaid no crystal oscillator cmos clock produces circuit, and wherein said frequency self calibration module comprises: temperature sensor and connected analog to digital converter, and said analog to digital converter is connected with said cross-couplings unit.
Preferable, aforesaid no crystal oscillator cmos clock produces circuit, and wherein every group of variable capacitance array includes a plurality of variable-capacitance unit, and each variable-capacitance unit includes: a variable capacitance and a connected switching tube.
Preferable, aforesaid no crystal oscillator cmos clock produces circuit, and wherein variable capacitance comprises: N type MOS varactor and P type MOS varactor, and N type MOS varactor and the parallel connection of P type MOS varactor.
Preferable, aforesaid no crystal oscillator cmos clock produces circuit, and wherein said digital controlled oscillator also comprises: amplitude detection unit and common mode feedback unit, and said amplitude detection unit and common mode feedback unit are respectively with said cross-couplings unit and connect.
Preferable; Aforesaid no crystal oscillator cmos clock produces circuit; Wherein said level switch module comprises: the first conversion submodule receives the high frequency pure oscillation signal of said digital controlled oscillator output, and exports the single-ended mode sinusoidal signal that said high frequency pure oscillation conversion of signals is; The second conversion submodule is connected with the said first conversion submodule, receives said single-ended mode sinusoidal signal, and exports the square-wave signal that single-ended mode that said single-ended mode sinusoidal signal converts into is exported.
Preferable, aforesaid no crystal oscillator cmos clock produces circuit, and wherein said programmable frequency divider is for adopting the programmable frequency divider of tandem type structural design.
By technique scheme; The no crystal oscillator cmos clock of the utility model produces circuit and has advantage and beneficial effect at least: the utility model is provided with the frequency lock control information of the variable capacitance array in the digital controlled oscillator through only in the frequency calibration process of clock signal, using crystal oscillator; Promptly after the frequency calibration of clock signal; Do not re-use crystal oscillator; And the execution clock signal produces each element of operating, and all with cheaply integrated circuit CMOS technology is compatible fully, the problems such as comprehensive integrated and high power consumption of having avoided chip to be provided with, can not be real outward; Thereby the no crystal oscillator cmos clock that the utility model provides produces circuit owing to need in course of normal operation, not use crystal oscillator; And can adopt standard CMOS process that it is integrated in the chip, therefore, realize that real fully integrated monolithic clock produces circuit; Not only can make the volume of circuit system littler; Power consumption is lower, and cost is also lower, but also can avoid circuit because of being collided and shaking the phenomenon that causes circuit to damage; And then the utility model improved the integrated level and the stability of system, and reduced the realization cost and the power consumption of system.
In sum, the utility model has obvious improvement technically, and has significantly positive technique effect, becomes the new design of a novelty, progress, practicality.
Above-mentioned explanation only is the general introduction of the utility model technical scheme; In order more to know the technological means of understanding the utility model; And can implement according to the content of specification, and in order to let the above-mentioned of the utility model and other purposes, characteristic and the advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Fig. 1 is the sketch map of existing phase-locked loop frequency integrator;
Fig. 2 is the sketch map that the no crystal oscillator cmos clock of the utility model embodiment produces circuit;
Fig. 3 is the sketch map of the digital controlled oscillator of the utility model embodiment;
Fig. 4 is the sketch map of the variable capacitance of the utility model embodiment;
Fig. 5 is the C-V characteristic curve sketch map of single NMOS varactor and single PMOS varactor;
Fig. 6 is the C-V characteristic curve sketch map of the variable capacitance of the utility model;
Fig. 7 is the operation principle sketch map of frequency lock module.
Embodiment
For further setting forth the utility model is to reach technological means and the effect that predetermined utility model purpose is taked; Below in conjunction with accompanying drawing and preferred embodiment; To no crystal oscillator CMOS (the Complementary Metal Oxide Semiconductor that proposes according to the utility model; Complementary metal oxide semiconductors (CMOS)) its embodiment of clock generation circuit, structure, characteristic and effect, specify as after.
Present embodiment is the clock generation circuit that on the basis of digital controlled oscillator, produces the high accuracy clock signal.Need to prove that " the no crystal oscillator " in the utility model is meant that the electronic equipment in normal use (as the back of dispatching from the factory) that needs clock signal need not use crystal oscillator, promptly the clock signal of electronic equipment is not to be provided by crystal oscillator; Crystal oscillator only uses during the frequency lock control information of the variable capacitance array in digital controlled oscillator is set, and only uses before electronic equipment dispatches from the factory or during electronic equipment maintenance like crystal oscillator.
The structure that the no crystal oscillator cmos clock of present embodiment produces circuit is shown in accompanying drawing 2.
No crystal oscillator cmos clock among Fig. 2 produces circuit and comprises: digital controlled oscillator 101, level switch module 102, programmable frequency divider 103, duty-cycle correction circuit 104, frequency lock module 105 and non-volatility memorizer 106.Wherein, Digital controlled oscillator 101 is connected respectively with non-volatility memorizer 106 with level switch module 102; Programmable frequency divider 103 is connected respectively with level switch module 102, duty-cycle correction circuit 104 and frequency lock module 105, and non-volatility memorizer 106 is connected with frequency lock module 105.
Digital controlled oscillator 101 is mainly used in and produces high frequency pure oscillation signal (also can be called the difference sinusoidal signal), and to level switch module 102 these high frequency pure oscillation signals of output.Digital controlled oscillator 101 is core circuits of clocking; Has the frequency self-calibration function; For example, when ambient temperature changed, digital controlled oscillator 101 can guarantee the constant high frequency pure oscillation signal of output frequency of oscillation through its frequency self-calibration function.
Digital controlled oscillator 101 can comprise: five metal-oxide-semiconductors (being Mn1, Mn2, Mp1, Mp2 and Mp3), LC resonant slots and frequency self calibration module; In addition, this digital controlled oscillator 101 can also comprise: amplitude detection unit 203 and common mode feedback unit 204.Said frequencies self calibration module can be specially temperature sensor 201 and connected analog to digital converter 202.
A concrete example of digital controlled oscillator 101 is shown in accompanying drawing 3.
Among Fig. 3; Four metal-oxide-semiconductors in five metal-oxide-semiconductors are that Mn1, Mn2, Mp1 and Mp2 form the cross-couplings unit; The cross-couplings unit is mainly used in to the LC resonant slots negative resistance energy is provided; Another metal-oxide-semiconductor is that Mp3 is connected with above-mentioned cross-couplings unit, and Mp3 is mainly used in to the cross-couplings unit biasing tail current is provided.The LC resonant slots comprises: inductance L, fixed capacity C and variable capacitance array, and inductance L, fixed capacity C and two groups of variable capacitance arrays are connected with above-mentioned cross-couplings unit respectively; Variable capacitance array wherein can be divided into two groups, forms (m＞2) by m variable capacitance Cf and m switch transistor T f for one group, is controlled by temperature sensor 201; When ambient temperature changes; Clock signal can squint, and temperature sensor 201 provides digital signal through analog to digital converter 202 for this group variable capacitance array after detecting variation of temperature; Can change the size of variable capacitance, thereby adjust the frequency of the signal of its output; Another group is formed (n＞2) by n variable capacitance Cr and n switch transistor T r, is controlled by frequency lock control information (the frequency lock control information that promptly from the non-volatility memorizer 106 of Fig. 2, reads out).Amplitude detection unit 203 with common mode feedback unit 204 respectively with above-mentioned cross-couplings unit and connect; And the effect of amplitude detection unit 203 and common mode feedback unit 204 comprises: make the amplitude of the output signal of digital controlled oscillator 101 remain on (being that amplitude output signal keeps stablizing) in the fixing scope; Like this; Not only help the processing of late-class circuit, and improved the phase noise performance of digital controlled oscillator 101.
The concrete example of above-mentioned variable capacitance Cf or Cr is shown in accompanying drawing 4.
Among Fig. 4, variable capacitance Cf or Cr comprise N type MOS (being a NMOS) varactor Mn0 and a P type MOS (being PMOS) varactor Mp0, and Mn0 and Mp0 are connected in parallel.The C-V characteristic curve of single NMOS varactor and single PMOS varactor is shown in accompanying drawing 5.
As can beappreciated from fig. 5; No matter be single NMOS varactor, or single PMOS varactor, its C-V characteristic curve is steeper all; That is to say; Even if very little variation takes place control voltage Vct r l, the variable capacitance of single NMOS varactor and single PMOS varactor all can be along with producing bigger variation, and this phenomenon is unfavorable for the frequency adjustment of digital controlled oscillator 101.
Fig. 6 shows the C-V characteristic curve of employing Mn0 of the utility model and the variable capacitance that Mp0 is connected in parallel.As can beappreciated from fig. 6; The NMOS varactor in Fig. 5 and the C-V characteristic curve of PMOS varactor; It is smooth many that the C-V characteristic curve of the variable capacitance of the utility model is wanted, and therefore, the variable capacitance of this structure is more suitable for being applied in the digital controlled oscillator 101.
The high frequency pure oscillation conversion of signals that level switch module 102 is mainly used in digital controlled oscillator 101 outputs is the square-wave signal of single-ended mode output, so that the processing of subsequent conditioning circuit.Level switch module 102 can comprise: the first conversion submodule and the second conversion submodule.The high frequency pure oscillation conversion of signals that the first conversion submodule is mainly used in digital controlled oscillator 101 outputs is the single-ended mode sinusoidal signal, and to second this single-ended mode sinusoidal signal of conversion submodule output; The second conversion submodule is mainly used in the square-wave signal that the single-ended mode sinusoidal signal that it is received converts single-ended mode output into.Level switch module 102 also can adopt alternate manner to realize the conversion of signal.
Duty-cycle correction circuit 104 is mainly used in the duty ratio of its clock signal that receives of adjustment; Make the duty ratio of clock signal satisfy the requirement of predetermined clock duty ratio; And the adjusted clock signal of output duty cycle, thereby the high accuracy clock signal is provided for other element in the electronic equipment.Above-mentioned predetermined clock duty ratio require can for a concrete numerical value as 50%, and the predetermined clock duty ratio requires can be stored in the duty-cycle correction circuit 104.
The operation that the frequency lock module 105 of the utility model is carried out can just be carried out before no crystal oscillator cmos clock produces formal use of chip at circuit place, promptly realizes disposable calibration.So after calibration finished, described frequency lock module did not just need to work again.As to obtain different clock frequencies, and get final product through the size of changing frequency dividing ratio, do not influence the performance of clock signal.
The operation principle of the frequency lock module 105 of the utility model is shown in accompanying drawing 7.
Among Fig. 7, the input of frequency lock module 105 comprises the output of programmable frequency divider 103 and the output of external crystal-controlled oscillation, and the process of frequency lock is controlled by enable signal.When no crystal oscillator cmos clock produces circuit and works for the first time when dispatching from the factory (as), enable signal is a high level, the process that expression begins to carry out frequency calibration.Echo signal among Fig. 7 is the high frequency pure oscillation signal process level switch module 102 of digital controlled oscillator 101 generations and the output after programmable frequency divider 103 processing.Reference signal among Fig. 7 is the stable high accurate clock signal of external crystal-controlled oscillation output, and both come the height of comparison frequency through counter.The minimum frequency difference that can be identified of REF signal and CLK signal is by the figure place decision of counter, and the figure place of counter is high more, and the difference on the frequency that can compare is just more little, and promptly frequency ratio resolution is just high more; Certainly, the circuit of counter also can be more complicated.Concrete frequency comparison procedure is to carry out in up-down counter and the state machine in Fig. 7.The state if the counter of CLK signal attains to a high place; And the counter of REF signal also is not reset, and explains that then the frequency ratio of CLK signal is higher, requires the value of register-stored to increase; Thereby increase the capacitance of the LC resonant slots in the digital controlled oscillator 101, reduce frequency of oscillation; On the contrary, if the counter of REF signal is reset, and the counter of CLK signal is also at low level; The frequency ratio that the CLK signal then is described is lower; Require the value of register-stored to reduce, thereby reduce the capacitance of the LC resonant slots in the digital controlled oscillator 101, improve frequency of oscillation.Through comparison procedure several times, the frequency of last REF signal and CLK signal equates that the frequency accuracy of CLK signal is identical with the frequency accuracy of the clock signal of external crystal-controlled oscillation, thus the end of frequency calibration process.At this moment, enable signal becomes low level, and the n-bit byte in the register is stored in the non-volatility memorizer 106.When no crystal oscillator cmos clock generation next time circuit powered on, the control word of the Cr group variable capacitance array in the digital controlled oscillator 101 can directly be read from non-volatility memorizer 106, and frequency lock module 105 does not need work, has just no longer needed crystal oscillator yet.
The above only is the preferred embodiment of the utility model; Be not that the utility model is done any pro forma restriction; Though the utility model discloses as above with preferred embodiment; Yet be not in order to limit the utility model; Any professional and technical personnel of being familiar with makes a little change or is modified to the equivalent embodiment of equivalent variations when the technology contents of above-mentioned announcement capable of using in not breaking away from the utility model technical scheme scope, is the content that does not break away from the utility model technical scheme in every case;, all still belong in the scope of the utility model technical scheme any simple modification, equivalent variations and modification that above embodiment did according to the technical spirit of the utility model.
Claims (8)
1. a no crystal oscillator cmos clock produces circuit, it is characterized in that, comprising:
Digital controlled oscillator is exported the high frequency pure oscillation signal of its generation;
Level switch module is connected with said digital controlled oscillator, receives said high frequency pure oscillation signal and exports the square-wave signal of the single-ended mode output that said high frequency pure oscillation conversion of signals is;
Programmable frequency divider is connected with said level switch module, receives said square-wave signal, and exports the clock signal with preset frequency after the said square-wave signal down conversion process;
Duty-cycle correction circuit is connected with said programmable frequency divider, receives said clock signal, and output duty cycle satisfies the adjusted clock signal that the predetermined clock duty ratio requires;
The frequency lock module; Be connected with said programmable frequency divider; And in the process that the frequency lock control information is set; Said frequency lock module also is connected with external crystal-controlled oscillation, and said frequency lock module receives the output signal of said external crystal-controlled oscillation and the output signal of said programmable frequency divider, and exports the frequency lock control information of the variable capacitance array of the corresponding said digital controlled oscillator of control of two said output signal frequency differences;
Non-volatility memorizer is connected respectively with digital controlled oscillator with said frequency lock module, receives the frequency lock control information of the said frequency lock module output of storage, and to said digital controlled oscillator said frequency lock control information is provided.
2. no crystal oscillator cmos clock according to claim 1 produces circuit, it is characterized in that said digital controlled oscillator comprises: metal-oxide-semiconductor Mn1, Mn2, Mp1, Mp2 and Mp3, LC resonant slots and frequency self calibration module;
Said metal-oxide-semiconductor Mn1, Mn2, Mp1 and Mp2 form the cross-couplings unit that said LC resonant slots provides the negative resistance energy;
Said metal-oxide-semiconductor Mp3 is connected with said cross-couplings unit;
Said LC resonant slots comprises: inductance, fixed capacity, one group are controlled by the variable capacitance array of frequency self calibration module and the variable capacitance array that another group is controlled by said frequency lock control information, and said inductance, fixed capacity and two groups of variable capacitance arrays are connected with said cross-couplings unit respectively.
3. no crystal oscillator cmos clock according to claim 2 produces circuit, it is characterized in that said frequency self calibration module comprises: temperature sensor and connected analog to digital converter, and said analog to digital converter is connected with said cross-couplings unit.
4. no crystal oscillator cmos clock according to claim 2 produces circuit, it is characterized in that every group of variable capacitance array includes a plurality of variable-capacitance unit, and each variable-capacitance unit includes: a variable capacitance and a connected switching tube.
5. no crystal oscillator cmos clock according to claim 4 produces circuit, it is characterized in that said variable capacitance comprises: N type MOS varactor and P type MOS varactor, and said N type MOS varactor and the parallel connection of P type MOS varactor.
6. produce circuit according to claim 2 or 3 or 4 or 5 described no crystal oscillator cmos clocks; It is characterized in that; Said digital controlled oscillator also comprises: amplitude detection unit and common mode feedback unit, and said amplitude detection unit and common mode feedback unit are respectively with said cross-couplings unit and connect.
7. produce circuit according to claim 1 or 2 or 3 or 4 or 5 described no crystal oscillator cmos clocks, it is characterized in that said level switch module comprises:
The first conversion submodule receives the high frequency pure oscillation signal of said digital controlled oscillator output, and exports the single-ended mode sinusoidal signal that said high frequency pure oscillation conversion of signals is;
The second conversion submodule is connected with the said first conversion submodule, receives said single-ended mode sinusoidal signal, and exports the square-wave signal that single-ended mode that said single-ended mode sinusoidal signal converts into is exported.
8. produce circuit according to claim 1 or 2 or 3 or 4 or 5 described no crystal oscillator cmos clocks, it is characterized in that said programmable frequency divider is for adopting the programmable frequency divider of tandem type structural design.
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| CN2012200987310U CN202495917U (en) | 2012-03-16 | 2012-03-16 | CMOS clock generating circuit without using crystal oscillator |
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| CN2012200987310U CN202495917U (en) | 2012-03-16 | 2012-03-16 | CMOS clock generating circuit without using crystal oscillator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102638247A (en) * | 2012-03-16 | 2012-08-15 | 安徽大学 | Clock generating method and clock generating circuit for CMOS (complementary metal oxide semiconductor) without crystal oscillator |
| CN103888136A (en) * | 2012-12-20 | 2014-06-25 | 澜起科技（上海）有限公司 | No-crystal clock generation system of broadcast system-on-chip |
| CN103973266A (en) * | 2013-01-31 | 2014-08-06 | 新唐科技股份有限公司 | Oscillator correction circuit and method and integrated circuit |
| CN104008222A (en) * | 2013-02-22 | 2014-08-27 | 国际商业机器公司 | Setting switch size and transition pattern in a resonant clock distribution system |
| CN107196656A (en) * | 2016-03-15 | 2017-09-22 | 联发科技（新加坡）私人有限公司 | A kind of signal calibration circuit and signal calibration method |
| CN107291148A (en) * | 2016-03-31 | 2017-10-24 | 大唐恩智浦半导体有限公司 | Sinusoidal wave generating device |
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2012
- 2012-03-16 CN CN2012200987310U patent/CN202495917U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102638247A (en) * | 2012-03-16 | 2012-08-15 | 安徽大学 | Clock generating method and clock generating circuit for CMOS (complementary metal oxide semiconductor) without crystal oscillator |
| CN102638247B (en) * | 2012-03-16 | 2014-11-26 | 安徽大学 | Clock generating method and clock generating circuit for CMOS (complementary metal oxide semiconductor) without crystal oscillator |
| CN103888136A (en) * | 2012-12-20 | 2014-06-25 | 澜起科技（上海）有限公司 | No-crystal clock generation system of broadcast system-on-chip |
| CN103888136B (en) * | 2012-12-20 | 2017-01-25 | 澜起科技（上海）有限公司 | No-crystal clock generation system of broadcast system-on-chip |
| CN103973266A (en) * | 2013-01-31 | 2014-08-06 | 新唐科技股份有限公司 | Oscillator correction circuit and method and integrated circuit |
| CN103973266B (en) * | 2013-01-31 | 2016-08-10 | 新唐科技股份有限公司 | Oscillator correction circuit and method and integrated circuit |
| CN104008222A (en) * | 2013-02-22 | 2014-08-27 | 国际商业机器公司 | Setting switch size and transition pattern in a resonant clock distribution system |
| CN104008222B (en) * | 2013-02-22 | 2017-11-21 | 国际商业机器公司 | Set the switch size and transformation pattern in resonant clock compartment system |
| CN107196656A (en) * | 2016-03-15 | 2017-09-22 | 联发科技（新加坡）私人有限公司 | A kind of signal calibration circuit and signal calibration method |
| CN107196656B (en) * | 2016-03-15 | 2020-11-06 | 联发科技（新加坡）私人有限公司 | Signal calibration circuit and signal calibration method |
| CN107291148A (en) * | 2016-03-31 | 2017-10-24 | 大唐恩智浦半导体有限公司 | Sinusoidal wave generating device |
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