CN202495446U - 一种新型结构晶闸管 - Google Patents

一种新型结构晶闸管 Download PDF

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CN202495446U
CN202495446U CN2012200727402U CN201220072740U CN202495446U CN 202495446 U CN202495446 U CN 202495446U CN 2012200727402 U CN2012200727402 U CN 2012200727402U CN 201220072740 U CN201220072740 U CN 201220072740U CN 202495446 U CN202495446 U CN 202495446U
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main electrode
lead wire
thyristor
lead
outer lead
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赵振华
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WUXI ROUM SEMICONDUCTOR TECHNOLOGY Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

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  • Thyristors (AREA)

Abstract

本实用新型涉及一种新型结构的晶闸管，含有两根主电极和一根栅极，主电极一的外引线与引线框架散热板直接连接，主电极二的外引线和栅极外引线；其特征是：所述的主电极一的外引线与引线框架散热板的连接部，设有往栅极方向的弯曲部；主电极二的外引线在根部设有横向加长焊接区，横向加长焊接区上设有多根内引线连接到引线框架的主电极一键合区上；所述主电极一键合区面积是栅极键合区的2~4倍。本实用新型的引线框架为非对称结构，加大主电极的键合位置面积，使主电极的内引线可以增加到多根，从而加大了晶闸管内引线的电流容量，有利于电子设备的稳定性和可靠性。

Description

一种新型结构晶闸管
技术领域
本实用新型属于一种电力电子器件，尤其是一种适用于机电设备中马达控制的晶闸管。
背景技术
晶闸管是一种三端器件：两根主电极和一根栅极。晶闸管和一般的半导体器件相同，内部采用键合工艺进行引线连接。现有技术中，晶闸管采用对称引线框架，主电极的键合位置有限，无法键合多根粗铝线，导致晶闸管的电流容量受到限制。
为了提高功率器件内引线的电流容量，现在已经出现了铜带/铜片结构的内引线，可以大幅度提高功率器件内引线的电流容量。但是，采用铜带/铜片结构的内引线，功率器件制造厂，需要大幅度技术改造，投资大，回收慢。
而铝线和铜片的导电能力差别，可以通过增加铝线数量来弥补。
实用新型内容
从背景技术可知，实践中，有许许多多产品不需要采用铜带/铜片结构的内引线，在原有的铝线结构下，增加1~2根粗铝线，就有足够的电流容量。
本实用新型的目的就在于，发明一种主电极引线键合区上能够键合更多铝线的新型结构的晶闸管。
本实用新型的晶闸管，含有两根主电极和一根栅极，主电极一的外引线与引线框架散热板直接连接，引线框架散热板与芯片背面以焊料连接，主电极二的外引线和栅极外引线通过内引线连接到各自的键合区；键合区设置在引线框架散热板上；其特征是：所述的主电极一的外引线与引线框架散热板的连接部，设有往栅极方向的弯曲部；主电极二的外引线在根部设有横向加长焊接区，横向加长焊接区上设有多根内引线连接到引线框架的主电极二键合区上；所述主电极二键合区面积是栅极键合区的2~4倍。 
优选的：所述的主电极二键合区呈“                                                
Figure 2012200727402100002DEST_PATH_IMAGE001
”形，栅极键合区设置在右下角缺口处。
进一步优选：所述的连接横向加长焊接区和主电极二键合区的内引线设有2根。
本实用新型将晶闸管的引线框架设计成非对称结构，加大主电极的键合位置面积，使主电极的内引线可以增加到多根，从而加大了晶闸管内引线的电流容量。
附图说明
图1，采用TO-220型封装的晶闸管结构图;
图2，采用TO-251/252型封装的晶闸管结构图。
具体实施方式
本实用新型有两种结构，如图1、2所示。附图1为TO-220封装的晶闸管结构，图2为TO-251/252封装的晶闸管结构，两者仅是外形结构不同，内部结构相同，本实用新型结构可以适用这两类封装形式。
外层是塑封体，内部结构具有引线框架散热板4、芯片、焊料、内引线，外引线有一个栅极3和主电极一外引线1和主电极二外引线2，外引线延伸到塑封体外面，成为该器件的脚。芯片与引线框架散热板4的粘结用焊料，芯片上的电极与外引线的连接是内引线，内引线与芯片和外引线的连接采用用键合工艺，键合的具体点就是键合点。 
主电极一的外引线1与引线框架散热板4连接，其连接处设置一个向栅极侧的弯曲部11，用来给主电极二的外引线2腾出空间，这样，主电极二的外引线的根部设置有横向加长焊接区21，明显的，由于空间的增加，这个区域比栅极外引线3根部的焊接区要大。
同时，主电极二键合区5为“
Figure 635045DEST_PATH_IMAGE001
”形，面积大于设置在缺角处的栅极的键合区7。主电极二键合区5上键合两根内引线6到主电极二的外引线2上，栅极键合区7上，键合1根内引线。由于面积有保证，在电流要求更高的情况下，主电极二键合区5上还可以键合更多数量的内引线。
制造工艺流程与一般塑封功率器件相同，先装片，使用焊料将芯片焊接到引线框架上，然后键合，将内引线使芯片与外引线连接好，然后塑封、固化，然后对外引线电镀锡，改善外引线的易焊性，然后切筋，使每个半成品分离，然后进行测试分类。

Claims (3)

1. 一种新型结构的晶闸管，含有两根主电极和一根栅极，主电极一的外引线（1）与引线框架散热板（4）直接连接，引线框架散热板（4）与芯片背面以焊料连接，主电极二的外引线（2）和栅极外引线（3）通过内引线连接到各自的键合区；键合区设置在引线框架散热板上，其特征是：所述的主电极一的外引线（1）与引线框架散热板（4）的连接部，设有往栅极方向的弯曲部（11）；主电极二的外引线（2）在根部设有横向加长焊接区（21），横向加长焊接区（21）上设有多根内引线（6）连接到引线框架的主电极二键合区（5）上；所述主电极二键合区（5）面积是栅极键合区（7）的2~4倍。
2.根据权利要求1所述的晶闸管，其特征是：所述的主电极二键合区（5）呈“                                                
Figure 2012200727402100001DEST_PATH_IMAGE001
”形，栅极键合区（7）设置在右下角缺口处。
3.根据权利要求1所述的晶闸管，其特征是：所述的横向加长焊接区（21）上设置的内引线（6）为两根。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103824834A (zh) * 2014-03-03 2014-05-28 无锡新洁能股份有限公司 一种具有改进型封装结构的半导体器件及其制造方法
CN107275308A (zh) * 2017-06-30 2017-10-20 深圳赛意法微电子有限公司 半导体封装装置、半导体引线框架及其切筋方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103824834A (zh) * 2014-03-03 2014-05-28 无锡新洁能股份有限公司 一种具有改进型封装结构的半导体器件及其制造方法
CN103824834B (zh) * 2014-03-03 2016-06-15 无锡新洁能股份有限公司 一种具有改进型封装结构的半导体器件及其制造方法
CN107275308A (zh) * 2017-06-30 2017-10-20 深圳赛意法微电子有限公司 半导体封装装置、半导体引线框架及其切筋方法

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