CN202420316U - Detonator delay time tester - Google Patents
Detonator delay time tester Download PDFInfo
- Publication number
- CN202420316U CN202420316U CN2011205117206U CN201120511720U CN202420316U CN 202420316 U CN202420316 U CN 202420316U CN 2011205117206 U CN2011205117206 U CN 2011205117206U CN 201120511720 U CN201120511720 U CN 201120511720U CN 202420316 U CN202420316 U CN 202420316U
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- China
- Prior art keywords
- circuit
- delay time
- single chip
- detonator delay
- time test
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- Expired - Lifetime
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Abstract
The utility model discloses a detonator delay time tester, which consists of a power circuit, and a detonator delay time testing circuit, a blasting switch circuit, a single chip circuit, a communication circuit and a display output circuit that are connected with the output end of the power circuit, wherein the output end of the blasting switch circuit is connected with the single chip circuit; the single chip circuit is in two-way connection with the detonator delay time testing circuit; the single chip circuit is in two-way connection with the communication circuit; and the output end of the communication circuit is connected with the display output circuit. The detonator delay time tester adopts the single chip to control, the required device has a small size and is low in energy consumption, and the produced instrument also has a small size; and the detonator delay time tester realizes intelligent control, has the advantages of low cost and high cost performance, is simple to manufacture and maintain, and can realize the computation display of the auxiliary function computation value and particular value.
Description
Technical field
The utility model relates to a kind of time test appearance, relates in particular to a kind of detonator delay time test appearance.
Background technology
Existing detonator delay time test appearance is to adopt the high-speed cmos Design of Digital Integrated Circuit, and the calculation display of miscellaneous function calculated value, particular value is difficult to realize, and this kind tester is when making; The use components and parts are many; Processing, production process complicacy, volume is big, and cost of manufacture is high; The components and parts power consumption is high during the tester operation, and after use a period of time, fault rate is high, because device is many, causes maintenance difficulty big.
Summary of the invention
The purpose of the utility model is the deficiency to prior art, the detonator delay time test that a kind of volume is little, low in energy consumption, cost performance is high, easy to maintenance appearance is provided, and can realizes the calculation display of miscellaneous function calculated value, particular value.
For accomplishing above-mentioned purpose; The technical scheme that the utility model adopts is: a kind of detonator delay time test appearance; By power circuit; And the detonator delay time test circuit that is connected with power circuit output end, blow out on-off circuit, single chip circuit, communicating circuit, display output circuit and form, the said on-off circuit output of blowing out connects single chip circuit, and said single chip circuit is connected with the detonator delay time test circuit is two-way; Said single chip circuit is connected with telecommunication circuit is two-way, and the output of telecommunication circuit connects display output circuit.
Operation principle: the working power that complete machine is provided by power circuit; Give skip signal of single chip circuit by blowing out circuit during work; Single chip circuit goes interfering signal to handle after receiving skip signal; By single chip circuit output low level signal controlling detonator delay time test circuit (being the time started of detonator conducting high level), receive the end signal (being the signal of pressure sensor) of detonator delay time test circuit by single chip circuit.Carry out the A/D conversion to the analog signal that receives then, data and storage realize that by single chip circuit control telecommunication circuit display output circuit shows output.
The beneficial effect of the utility model: by single chip circuit control, mostly required device is surface mount elements, and volume is little, and is low in energy consumption, and the instrument overall volume of being produced is small and exquisite; Realized intelligent control by single chip circuit, design cost is low, and cost performance is high, makes easy to maintenance; Can realize the calculation display of miscellaneous function calculated value, particular value.
Description of drawings
Below in conjunction with embodiment the utility model is described in detail.
Fig. 1: be the theory diagram of the utility model;
Fig. 2: be the utility model single chip circuit wiring diagram;
Fig. 3: be the utility model detonator delay time test circuit wiring schematic diagram;
Fig. 4: for the utility model is blown out the on-off circuit wiring schematic diagram.
The specific embodiment
Like Fig. 1,2,3, shown in 4; A kind of detonator delay time test appearance; By power circuit, and the detonator delay time test circuit that is connected with power circuit output end, blow out on-off circuit, single chip circuit, communicating circuit, display output circuit and form, the said on-off circuit output of blowing out connects single chip circuit; Said single chip circuit is connected with the detonator delay time test circuit is two-way; Said single chip circuit is connected with telecommunication circuit is two-way, and the output of telecommunication circuit connects display output circuit, and the working power of complete machine is provided by power circuit.
The said on-off circuit of blowing out is made up of often open button SW1, capacitor C 1 and the resistance R 8 of not locking, and it is parallelly connected with capacitor C 1 often to open button SW1, the node one end ground connection after the parallel connection, a terminating resistor R8, resistance R 8 another termination+3V.
Said detonator delay time test circuit comprises: rectifier bridge, filter capacitor C2 that D1, D2, D3, D4 bridge joint are formed, FET M1, M2, the L1A of operational amplifier L1; Operational amplifier U2A, U2B; D/A chip U6, the U3A of reverse buffer U3, U3F, U3E, U3D, photoelectrical coupler G1, G2; Resistance R 0, R4-R7, R11-R16, R18, R34, R40-R43, R50-R54, R56, LG; Capacitor C 10-C13, C21, LED light, diode D9, sensor CGQ, photoelectric tube GDG form;
The rectifier bridge of being made up of external transformer, D1, D2, D3, D4 bridge joint adds filter capacitor C2 and forms high-tension circuit;
When pinning when blowing out switch, single-chip microcomputer receives one the high level saltus step is arranged is low level signal and handles, and single-chip microcomputer P6.6 pin output low level TD picks up counting simultaneously; TD becomes high level through the U3A not gate; Obtain low level TDKZ through optocoupler G1, not conducting of M2, KZ is a high level; FET M1 conducting, high voltage is through LG detonator ground connection; DIN, SCLK, CX1 are respectively the output signal of single-chip microcomputer P6.5, P6.6, P6.3 pin, DIN; SCLK, CX1 signal convert signal DIN1, SCLK1 into through not gate U3F, U3E, U3D and photoelectrical coupler respectively; CX11 connects with 1,2,3 pins of D/A chip U6 respectively; Single-chip microcomputer is through control DIN, and SCLK, CX1 signal realize controlling the output OUTA of D/A chip U6, promptly by the time of Single-chip Controlling output safety initiation current with the output of control electric current; The effect of photoelectrical coupler G1, G2 is that single-chip microcomputer and high pressure are isolated;
In order to detect the quality of M1, can be through observing LED light, when not blowing out, LED light is bright, and 2, the 3 pin conductings of M1 are described, and M1 is bad, has played the effect of holding circuit like this;
By U2A, the U2B of operational amplifier, resistance R 4, R5, R6, R7, R54, capacitor C 10, diode D9, sensor CGQ, photoelectric tube GDG forms signal receiving circuit; Sensor CGQSR signal inputs to single-chip microcomputer pin P1.0 through being adjusted to more satisfactory waveform JSXH, and its sensitivity can be regulated through the resistance of resistance R 54.
Said communicating circuit adopts the direct communication modes of interface.
Single chip circuit carries out the A/D conversion to the analog signal that receives, and data and storage realize that by single chip circuit control telecommunication circuit display output circuit shows output.
The equipment that described display output circuit comprises transmission circuit and is used to show output, the equipment of said demonstration output comprises display, printer etc.
Claims (3)
1. detonator delay time test appearance; It is characterized in that: by power circuit; And the detonator delay time test circuit that is connected with power circuit output end, blow out on-off circuit, single chip circuit, communicating circuit, display output circuit and form, the said on-off circuit output of blowing out connects single chip circuit, and said single chip circuit is connected with the detonator delay time test circuit is two-way; Said single chip circuit is connected with telecommunication circuit is two-way, and the output of telecommunication circuit connects display output circuit.
2. detonator delay time test appearance according to claim 1; It is characterized in that: the said on-off circuit of blowing out is made up of often open button SW1, capacitor C 1 and the resistance R 8 of not locking; It is parallelly connected with capacitor C 1 often to open button SW1; Node one end ground connection after the parallel connection, a terminating resistor R8, resistance R 8 another termination+3V.
3. detonator delay time test appearance according to claim 1 is characterized in that: said detonator delay time test circuit comprises: rectifier bridge, filter capacitor C2 that D1, D2, D3, D4 bridge joint are formed, FET M1, M2; The L1A of operational amplifier L1, operational amplifier U2A, U2B, D/A chip U6; The U3A of reverse buffer U3, U3F, U3E, U3D; Photoelectrical coupler G1, G2, resistance R 0, R4-R7, R11-R16, R18, R34, R40-R43, R50-R54, R56, LG, capacitor C 10-C13, C21; LED light, diode D9, sensor CGQ, photoelectric tube GDG form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205117206U CN202420316U (en) | 2011-12-09 | 2011-12-09 | Detonator delay time tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205117206U CN202420316U (en) | 2011-12-09 | 2011-12-09 | Detonator delay time tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202420316U true CN202420316U (en) | 2012-09-05 |
Family
ID=46745073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205117206U Expired - Lifetime CN202420316U (en) | 2011-12-09 | 2011-12-09 | Detonator delay time tester |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202420316U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103134398A (en) * | 2013-02-08 | 2013-06-05 | 前进民爆股份有限公司 | Method and time measuring instrument for measuring detonation delaying of digital electronic detonator through mechanics |
| CN103134397A (en) * | 2013-02-08 | 2013-06-05 | 前进民爆股份有限公司 | Method and time-measurement instrument of optically measuring time delay of digital electronic detonator powder explosion detonation |
| CN105571413A (en) * | 2015-12-25 | 2016-05-11 | 中国电子科技集团公司第五十四研究所 | Method and equipment for measuring delay time in millisecond magnitude of electronic detonator at high precision |
-
2011
- 2011-12-09 CN CN2011205117206U patent/CN202420316U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103134398A (en) * | 2013-02-08 | 2013-06-05 | 前进民爆股份有限公司 | Method and time measuring instrument for measuring detonation delaying of digital electronic detonator through mechanics |
| CN103134397A (en) * | 2013-02-08 | 2013-06-05 | 前进民爆股份有限公司 | Method and time-measurement instrument of optically measuring time delay of digital electronic detonator powder explosion detonation |
| CN103134398B (en) * | 2013-02-08 | 2015-06-24 | 前进民爆股份有限公司 | Method and time measuring instrument for measuring detonation delaying of digital electronic detonator through mechanics |
| CN103134397B (en) * | 2013-02-08 | 2015-06-24 | 前进民爆股份有限公司 | Method and time-measurement instrument of optically measuring time delay of digital electronic detonator powder explosion detonation |
| CN105571413A (en) * | 2015-12-25 | 2016-05-11 | 中国电子科技集团公司第五十四研究所 | Method and equipment for measuring delay time in millisecond magnitude of electronic detonator at high precision |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: CHINA COAL TECHNOLOGY ENGINEERING GROUP HUAIBEI EX Free format text: FORMER NAME: INST. OF DEMOLITION TECH., COAL SCIENCE AND TECH. GENERAL RESEARCH INST. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 235039 Anhui Province, Huaibei City Xiangshan District East Road No. 116 Patentee after: Huaibei blasting technology research institute company limited of Zhong Meike work group Address before: 235039 Anhui Province, Huaibei City Xiangshan District East Road No. 116 Patentee before: Blasting Technology Research Institute, Coal Science and Technology General Research Institute |
|
| CX01 | Expiry of patent term |
Granted publication date: 20120905 |
|
| CX01 | Expiry of patent term |