CN202363453U - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
- Publication number
- CN202363453U CN202363453U CN 201120486671 CN201120486671U CN202363453U CN 202363453 U CN202363453 U CN 202363453U CN 201120486671 CN201120486671 CN 201120486671 CN 201120486671 U CN201120486671 U CN 201120486671U CN 202363453 U CN202363453 U CN 202363453U
- Authority
- CN
- China
- Prior art keywords
- chip
- base plate
- semiconductor chip
- semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
The utility model discloses a semiconductor packaging structure. The semiconductor packaging structure comprises a semiconductor chip, a base plate and a chip bracket, wherein the upper surface of the semiconductor chip is provided with an electric connecting area and a non-electric connecting area; a plurality of chip pads are connected below the electric connecting area; the chip pads are connected with base plate pads by a plurality of middle elastic conducting elements, and the base plate pads are arranged on the base plate corresponding to the chip pads; the base plate is also provided with the chip bracket made of insulating materials, and the chip bracket corresponds to the non-electric connecting area of the semiconductor chip and supports the semiconductor chip by an adhesive layer; a moisture-absorbing layer material is filled between the semiconductor chip and the base plate; and the lower surface of the base plate is also provided with a ball gird array for providing input or output for external signals. The semiconductor packaging structure disclosed by the utility model is novel in conception and reasonable in design, and has wide market value and large market potential.
Description
Technical field
The utility model relates to the semiconductor packaging field, particularly a kind of semiconductor package.
Background technology
Along with electronic installation to compact tight demand and development trend, the IC encapsulation technology makes the encapsulation kenel demand of flip chip continue to raise also in order to cooperate high I/O number, high heat radiation and the microminiaturized high standard requirement of package dimension.
Because the thermal expansion coefficient difference property of structural materials such as existing flip chip packaging structure chips and substrate is bigger; Make flip chip packaging structure in operating process, be subject to the thermal-mechanical stresses influence that thermal cycle produces; This thermal-mechanical stresses is after being absorbed by tin ball pad, welding tin ball and tin ball pad as contact; Be very easy to cause inefficacy, chip be full of cracks and the chip edge edge of pad to cause linearities such as the demoulding, and then influence the reliability of flip chip packaging structure.
Have in the prior art to adopt to add elastomeric material such as epoxy resin between welding tin sphere gap and chip and substrate increasing the absorption of thermal-mechanical stresses, and reduce because of the thermal expansion coefficient difference lock and cause Problem of Failure; Also there is the welding lead that adopts substrate and chip utilization bending to replace welding tin ball, and utilizes the bending place of welding lead that one restoring force is provided,, but all exist different shortcoming and defect in order to the thermal-mechanical stresses of absorption because of thermal expansion coefficient difference lock bad student.
Therefore, prior art awaits improving and improving.
Summary of the invention
For solving the aforementioned problems in the prior, the purpose of the utility model provides a kind of solution influences the semiconductor package of reliability because of thermal expansion coefficient difference causes demoulding etc.
The utility model is realized above-mentioned purpose through following technological means: a kind of semiconductor package; Comprise semiconductor chip, substrate and chip set; Described semiconductor chip upper surface is provided with one and is electrically connected a district and a non-electric-connecting district, and this is electrically connected the below, district and connects a plurality of chip pad; These a plurality of chip pad are arranged at the substrate weld pad on the substrate through elastic conductive component connection in the middle of a plurality of corresponding to a plurality of chip pad; Also be provided with the chip set processed by insulating material on the described substrate, this chip set is corresponding to the non-electric-connecting district of semiconductor chip, through adhesion layer in order to the support semiconductor chip; Be filled with hygroscopic material between described semiconductor chip and the substrate; The lower surface of described substrate also is provided with one the BGA that external signal is inputed or outputed is provided.
Compared with prior art; The beneficial effect of the utility model is: because the semiconductor package that adopts the technique scheme lock to provide; The restoring force that utilizes a plurality of middle elastic conductive components to be had absorbs the thermal-mechanical stresses that is produced in the operating process; Under the prerequisite that does not influence the design of semiconductor package I/O pin number and density, reach pad inefficacy, chip be full of cracks and the demoulding etc. avoiding causing and influence the semiconductor package reliability problems because of thermal expansion coefficient difference.The utility model is novel, reasonable in design, has market value and huge market potential widely.
Description of drawings
Accompanying drawing 1 is the utility model semiconductor package structural representation.
Each label is respectively among the figure: (1) semiconductor chip, (2) substrate, (3) chip set, (4) chip pad, elastic conductive component in the middle of (5), (6) substrate weld pad, (7) hygroscopic material, (8) BGA, (9) adhesion layer.
Embodiment
Below in conjunction with accompanying drawing the utility model is done further to specify:
Referring to Fig. 1, a kind of semiconductor package of the utility model comprises semiconductor chip 1, substrate 2 and chip set 3, and described semiconductor chip 1 upper surface is provided with one and is electrically connected a district and a non-electric-connecting district, and this is electrically connected the below, district and connects a plurality of chip pad 4; These a plurality of chip pad 4 are arranged at the substrate weld pad 6 on the substrate 2 through 5 connections of elastic conductive component in the middle of a plurality of corresponding to a plurality of chip pad 4; Also be provided with the chip set 3 processed by insulating material on the described substrate 2, this chip set 3 is corresponding to the non-electric-connecting district of semiconductor chip 1, through adhesion layer 9 in order to support semiconductor chip 1; Be filled with hygroscopic material 7 between described semiconductor chip 1 and the substrate 2; The lower surface of described substrate 2 also is provided with one the BGA 8 that external signal is inputed or outputed is provided.
The above; It only is the preferred embodiment of the utility model; Be not that the utility model is done any pro forma restriction; Any professional and technical personnel of being familiar with possibly utilize the technology contents of above-mentioned announcement to change or be modified to the equivalent embodiment of equivalent variations; But all the utility model technical scheme contents that do not break away from, all still belong in the scope of the utility model technical scheme any simple modification, equivalent variations and modification that above embodiment did according to the technical spirit of the utility model.
Claims (1)
1. a semiconductor package comprises semiconductor chip, substrate and chip set, it is characterized in that: described semiconductor chip upper surface is provided with one and is electrically connected a district and a non-electric-connecting district, and this is electrically connected the below, district and connects a plurality of chip pad; These a plurality of chip pad are arranged at the substrate weld pad on the substrate through elastic conductive component connection in the middle of a plurality of corresponding to a plurality of chip pad; Also be provided with the chip set processed by insulating material on the described substrate, this chip set is corresponding to the non-electric-connecting district of semiconductor chip, through adhesion layer in order to the support semiconductor chip; Be filled with hygroscopic material between described semiconductor chip and the substrate; The lower surface of described substrate also is provided with one the BGA that external signal is inputed or outputed is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120486671 CN202363453U (en) | 2011-11-30 | 2011-11-30 | Semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120486671 CN202363453U (en) | 2011-11-30 | 2011-11-30 | Semiconductor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202363453U true CN202363453U (en) | 2012-08-01 |
Family
ID=46574616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120486671 Expired - Fee Related CN202363453U (en) | 2011-11-30 | 2011-11-30 | Semiconductor packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202363453U (en) |
-
2011
- 2011-11-30 CN CN 201120486671 patent/CN202363453U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120801 Termination date: 20121130 |