CN202309716U

CN202309716U - Optical fiber-based high-speed real-time communication card

Info

Publication number: CN202309716U
Application number: CN2011204007961U
Authority: CN
Inventors: 韩建朝; 张广拓; 王琳; 文飞鸽
Original assignee: 707th Research Institute of CSIC
Current assignee: 707th Research Institute of CSIC
Priority date: 2011-10-20
Filing date: 2011-10-20
Publication date: 2012-07-04
Anticipated expiration: 2021-10-20

Abstract

The utility model relates to an optical fiber-based high-speed real-time communication card which is characterized by comprising a photoelectric signal converter, a high-speed serial-parallel conversion module, an FPGA (Field Programmable Gate Array) module, a receiving end FIFO (First In First Out) buffer, a sending end FIFO buffer, a storage and a PCI (Programmable Communication Interface) bridging module, wherein one end of the photoelectric signal converter is connected with an optical fiber network; the other end of the photoelectric signal converter is connected with one end of the high-speed serial-parallel conversion module; the high-speed serial-parallel conversion module is connected with a receiving end FPGA module and a sending end FPGA module; the receiving end FPGA module is also connected with a main FPGA module and the receiving end FIFO buffer; the sending end FPGA module is also connected with the main FPGA module and the sending end FIFO buffer; and the main FPGA module is connected with the storage and the PCI bridging module. The optical fiber-based high-speed real-time communication card is reasonable in design, is capable of greatly increasing the instantaneity and the efficiency as well as the reliability of data transmission in a navigation information processing system, and has the characteristics of high and stable rate of information throughput, certainty and predictability of transmission delay, high efficiency of information utilization, and the like.

Description

A kind of high-speed real-time address card based on optical fiber

Technical field

The utility model belongs to optical-fibre communications field, especially a kind of high-speed real-time address card based on optical fiber.

Background technology

The various complicacy of information in the ship navigation system.Along with the development of China's national defense cause, also increasingly high to the requirement of navigation information real-time, this will differentiate boat information processing system can transmit and the various information of treatment types at a high speed, in real time.And there are following shortcoming in the information transmission technology that is adopted in the current navigation system such as Ethernet, CAN bus etc. aspect message transmission: (1) transmission of Information speed is not high; (2) receive the restriction of present used bus transfer mechanism, message transmission is uncertain time of delay; (3) complicated communications protocol has reduced bus communication efficient.

Summary of the invention

The purpose of the utility model is to overcome the deficiency of prior art, and a kind of high-speed real-time address card based on optical fiber that can improve navigation information transmission rate and communication efficiency and stable performance is provided.

The utility model solves its technical problem and takes following technical scheme to realize:

A kind of high-speed real-time address card based on optical fiber; Comprise photoelectric signal converter, high speed string and modular converter, main FPGA module, receiving terminal FPGA module, transmitting terminal FPGA module, receiving terminal fifo buffer, transmitting terminal fifo buffer, memory and PCI bridge module; Photoelectric signal converter one end is connected with optical networking; An end of modular converter is connected this photoelectric signal converter other end with going here and there also at a high speed; This is gone here and there at a high speed and modular converter is connected with receiving terminal FPGA module and transmitting terminal FPGA module; Receiving terminal FPGA module also is connected with main FPGA module, receiving terminal fifo buffer simultaneously, and transmitting terminal FPGA module also is connected with main FPGA module, transmitting terminal fifo buffer simultaneously, and this main FPGA module also is connected with memory and PCI bridge module.

And described memory is the SDRAM module of 128MB, and described receiving terminal fifo buffer, transmitting terminal fifo buffer are the fifo buffer of 4K.

And; Described main FPGA module adopts the EP1K30 fpga chip; Described receiving terminal FPGA module, transmitting terminal FPGA module all adopt the EP1K10 fpga chip; Described photoelectric signal converter adopts the FTLF8519 transducer of 2.125Gb/s to carry out the mutual conversion of photosignal, and described high speed string and modular converter adopt 16 high speed strings and modular converter to carry out the mutual conversion of serial signal and parallel signal, and described PCI bridge module adopts the PCI9656 bridging chip.

The advantage and the good effect of the utility model are:

The utility model has been realized the high speed communication function of 2.125Gb/s between a plurality of navigator as transmission medium and through photoelectric signal converter, high speed string and modular converter and FPGA module with optical fiber; Real time of data transmission, high efficiency and reliability in the navigation information processing system have greatly been improved; Upgrade to other node reception through the data change of test shows from a node; Reach 680ns, realized real high-speed real-time.Simultaneously, the real time information communication network that adopts the utility model to make up has the rate of information throughput certainty and characteristics such as predictability, using efficiency of information height high and stable, transmission delay.

Description of drawings

Fig. 1 is the circuit block diagram of the utility model;

Fig. 2 is that the utility model application system connects sketch map.

Embodiment

Below in conjunction with accompanying drawing the utility model embodiment is done further detailed description:

A kind of high-speed real-time address card based on optical fiber; As shown in Figure 1; Comprise photoelectric signal converter, high speed string and modular converter, main FPGA module, receiving terminal FPGA module, transmitting terminal FPGA module, receiving terminal fifo buffer, transmitting terminal fifo buffer, memory and PCI bridge module; Photoelectric signal converter one end is connected with optical networking; An end of modular converter is connected this photoelectric signal converter other end with going here and there also at a high speed, and this is gone here and there at a high speed and modular converter is connected with receiving terminal FPGA module and transmitting terminal FPGA module, and receiving terminal FPGA module also is connected with main FPGA module, receiving terminal fifo buffer simultaneously; Transmitting terminal FPGA module also is connected with main FPGA module, transmitting terminal fifo buffer simultaneously, and this main FPGA module also is connected with memory and PCI bridge module.

In the present embodiment; Main FPGA module, receiving terminal FPGA module, transmitting terminal FPGA module adopt big capacity, the high-performance EP1K Series FPGA programming device of ALTERA company; Wherein, Main FPGA module adopts the EP1K30FPGA chip to realize the basic principle and the overall logic control of high-speed real-time communication, and receiving terminal FPGA module, transmitting terminal FPGA module all adopt the EP1K10 fpga chip to realize the input and output control of information respectively.Owing to adopt optical fiber as transmission medium; Therefore; Optical networking need carry out the high-speed transitions of the signal of telecommunication and light signal through photoelectric signal converter; The FTLF8519 transducer that photoelectric signal converter has adopted speed to reach 2.125Gb/s is guaranteed the high efficiency changed, and string and modular converter are parallel signal to data transaction at a high speed to utilize 16.Because it is high that optical signal transmission speed ratio internal bus transmission rate is wanted, so the fifo buffer that between receiving terminal FPGA module and main FPGA module, transmitting terminal FPGA module and main FPGA module, is respectively equipped with a 4K is with the raising efficiency of transmission.In order to realize the memory function of data, to storing, memory has adopted the SDRAM chip of 128MB to main FPGA module through memory module.Because this address card adopts the cpci bus framework, aspect the cpci bus interface, the PCI bridge module has selected for use the PCI9656 bridging chip of PLX company to realize the seamless link with the 66MHz cpci bus.

This high-speed real-time address card is inserted in the computer in use, and links together through optical networking and to carry out many high-speed real-time information communications between the remote main frame, and the communication network that is constituted can be loop network or stelliform connection topology configuration.As shown in Figure 2; After being inserted into this high-speed real-time address card in the computer; In a plurality of local hosts, expand the memory headroom of an identical address; When local host to the address card under it on the data of designated address space when changing, the data instant in the appropriate address space of remote communication card is followed variation.The core of this high-speed real-time address card is to utilize the advantage of FPGA on data processing, by the memory function of SDRAM, has realized the renewal of local data, and makes the data in real time in appropriate address space on other node obtain upgrading through optical fiber as transmission medium.

The message processing flow of this high-speed real-time address card is:

1, DRP data reception process

The data of other node arrive this node through Optical Fiber Transmission in the network; Data-signal at first converts the signal of telecommunication through the 2.125Gb/s optical-electrical converter into by light signal; Signal rate still is 2.125Gb/s; Convert parallel signal into through 16 high speed strings and modular converter, the transmission rate of parallel signal is: 2.125Gbps/16bit=132.8125Mbps, and data get into receiving terminal FPGA module then; Because external signal transmission rate (132.8125Mbps) is higher than inner cpci bus transmission rate (66MHz); So signal demand becomes the laggard FPGA of the becoming owner of module of slow speed signal through the receiving terminal fifo buffer of 4K, behind the memory address that main FPGA module need deposit in from PCI bridge module acquired information deposit data in the SDRAM of 128MB.

2, data transmission procedure

Local host at first needs updated information to write the specific address space of SDRAM through PCI bridge module handle; Main FPGA module is taken out information data from the SDRAM appropriate address; Give the transmitting terminal fifo buffer; The transmitting terminal fifo buffer is transferred to transmitting terminal FPGA module after converting slow speed signal (66MHz) into high speed signal (132.8125Mbps); Signal converts serial data into through 16 serial/parallel transducers then, and the transmission rate after the conversion becomes: 132.8125*16bit=2.125Gbps, and the optical signal transmission that changes 2.125Gb/s into through optical-electrical converter is in high-speed real-time address card network.The high-speed real-time address card of other node receives this information through corresponding DRP data reception process, thereby has accomplished the immediate updating of information.

In the utility model, main FPGA module, receiving terminal FPGA module, transmitting terminal FPGA module realize different functions respectively, and the function of above-mentioned module is described respectively below.

1, the main FPGA module core component that is the utility model has been realized the basic principle of high-speed real-time address card and the logic control of data transmission procedure.Major function comprises: (1) will need data updated to write or read corresponding SDRAM address space through the reading and writing data requirement of bridging chip response cpci bus interface; (2) judge the sending module state at any time, in time will need data updated to be transferred to sending module; (3) judge the state of receiver module at any time, in time deposit the data that receive in corresponding SDRAM address space; (4) SDRAM address space read/write collision mechanism management, when cpci bus and receiver module simultaneously will be to same SDRAM address space write datas, conflict management mechanism was write preferential selective reception module one side earlier; When detect to be sent or the packet that receives in contain fallacious message or junk information, then with detected data packet discarding.

2, receiving terminal FPGA module mainly is responsible for the reception processing of information, and under main FPGA module controls, serial/parallel transducer, receiving terminal fifo buffer is carried out logic control.

3, transmitting terminal FPGA module mainly is responsible for the transmission of information, and under main FPGA control, parallel/serial transfer process and transmitting terminal fifo buffer is carried out logic control.

In order to verify the effect of the utility model, this high-speed real-time address card has been carried out a series of tests, concrete test environment and test result are following:

(1) test environment

Use the address card of two nodes to test, continuous two nodes with the high speed fibre of 2.125Gb baud rate, the computer of two nodes adopts pci bus and cpci bus respectively.The pci bus computer CPU is Intel Core2, dominant frequency 2.8GHz, in save as 2GB; The cpci bus computer is Intel PentiumM, dominant frequency 1.6Ghz, DDR internal memory 512M.

(2) test result

If a node is made server, send the identical data of size to the circulation of another one node, it is zero-time that node 1 begins to send data, node 2 sense datas are the termination time, record start time and termination time, can calculate transmission of Information speed.Test result is seen table 1.

Table 1 test result

Sequence number	The read-write number of times	Read-write total time (s)	Transmission rate (Mb/s)
				1	500	11.750	638.32
2	500	11.735	639.12
				3	500	11.735	639.12
4	500	11.750	638.32
				5	500	11.860	632.40
6	1000	23.906	627.44
				7	1000	23.547	637.04
8	1000	23.891	627.84
				9	1000	23.547	637.04
10	1000	24.078	622.96

Through last table, can find out traditional obviously the improving of transmission of Information speed ratio like Ethernet, CAN bus transfer rate.

It is emphasized that; The described embodiment of the utility model is illustrative; Rather than it is determinate; Therefore the utility model is not limited to the embodiment described in the embodiment, every by those skilled in the art according to other execution modes that the technical scheme of the utility model draws, belong to the scope of the utility model protection equally.

Claims

1. high-speed real-time address card based on optical fiber; It is characterized in that: comprise photoelectric signal converter, high speed string and modular converter, main FPGA module, receiving terminal FPGA module, transmitting terminal FPGA module, receiving terminal fifo buffer, transmitting terminal fifo buffer, memory and PCI bridge module; Photoelectric signal converter one end is connected with optical networking; An end of modular converter is connected this photoelectric signal converter other end with going here and there also at a high speed; This is gone here and there at a high speed and modular converter is connected with receiving terminal FPGA module and transmitting terminal FPGA module; Receiving terminal FPGA module also is connected with main FPGA module, receiving terminal fifo buffer simultaneously, and transmitting terminal FPGA module also is connected with main FPGA module, transmitting terminal fifo buffer simultaneously, and this main FPGA module also is connected with memory and PCI bridge module.

2. a kind of high-speed real-time address card based on optical fiber according to claim 1 is characterized in that: described memory is the SDRAM module of 128MB, and described receiving terminal fifo buffer, transmitting terminal fifo buffer are the fifo buffer of 4K.

3. a kind of high-speed real-time address card according to claim 1 and 2 based on optical fiber; It is characterized in that: described main FPGA module adopts the EP1K30 fpga chip; Described receiving terminal FPGA module, transmitting terminal FPGA module all adopt the EP1K10 fpga chip; Described photoelectric signal converter adopts the FTLF8519 transducer of 2.125Gb/s to carry out the mutual conversion of photosignal; Described high speed string and modular converter adopt 16 high speed strings and modular converter to carry out the mutual conversion of serial signal and parallel signal, and described PCI bridge module adopts the PCI9656 bridging chip.