CN202307877U - Wiring structure - Google Patents
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- CN202307877U CN202307877U CN201120449942XU CN201120449942U CN202307877U CN 202307877 U CN202307877 U CN 202307877U CN 201120449942X U CN201120449942X U CN 201120449942XU CN 201120449942 U CN201120449942 U CN 201120449942U CN 202307877 U CN202307877 U CN 202307877U
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Abstract
The utility model provides a wiring structure comprising: a semiconductor substrate; a first dielectric layer arranged on the semiconductor substrate; a contact hole formed on the first dielectric layer; a first metal layer covering a bottom and a sidewall of the contact hole and covering an upper surface of the first dielectric layer; a first opening formed on the first metal layer; a second dielectric layer covering a bottom and a sidewall of the first opening and covering an upper surface of the first metal layer; a through hole formed on the second dielectric layer; a second metal layer covering a bottom and a sidewall of the through hole and covering an upper surface of the second dielectric layer; and a second opening formed on the second metal layer. The wiring structure of the utility model satisfies requirements from a technology platform closing to 1.5 [mu]m and therebelow to planarization without adopting process such as SOG (Spin On Glass coating) planarization, adhesive etchback SOG planarization and so on.
Description
Technical field
The utility model relates to semiconductor device and semiconductor process techniques field, relates in particular to a kind of wire structures that closes on the no SOG of submicron order (1.5 μ m and following).
Background technology
In integrated circuit fabrication process, often adopt SiO
2Form dielectric layer to isolate different metal layers Deng insulating material, prevent different metal layer and other conductive layer break-through conduction level.The thickness of dielectric layer is generally between
to
, specifically can select according to the requirement of different withstand voltage and parasitic parameters.Because the thickness of dielectric layer is thicker relatively; The difference in height of adding perforate and preceding road metal level causes the subregion shoulder height too high, make occur that step coverage is not good in following process and the utilization process, process abnormality, parameter lost efficacy and integrity problem.In order to eliminate the harmful effect that shoulder height is brought; Spin-coating glass (SOG; Spin On Glass coating) planarization, band glue return carves planarization and chemico-mechanical polishing process quilts such as (CMP) is widely used in the modern semiconductors manufacture process, particularly below submicron order and close on the little regular technology of submicron order particularly important.
Fig. 1 shows the generalized section of a kind of wire structures of the prior art, comprising: Semiconductor substrate 10; Cover on first dielectric layer, 11, the first dielectric layers 11 on the Semiconductor substrate 10 and be formed with perforate; The first metal layer 12 covers first dielectric layer 11 and fills perforate wherein, also is formed with perforate on the first metal layer 12; Second dielectric layer 13 covers the first metal layer 12 and fills perforate wherein, also is formed with perforate on second dielectric layer 13; Second metal level 14 covers second dielectric layer 13 and fills perforate wherein.Because in closing on submicron order 1.5 μ m and following technique platform thereof; Climbing pattern for the pattern of perforate, metal level, dielectric layer, passivation layer has high requirements; If shoulder height Tai Gaotai is steep, so since the thin film deposition characteristic can cause the thickness of metal level, dielectric layer, passivation layer to approach partially even the crack occur at the step side place.Cause in follow-up cleaning cleaning solution such as acid solution can corrode dielectric layer, the metal level of lower floor along the crack; May cause preceding road metal disappearance; Through hole is process abnormality such as conducting over the ground, thereby brings testing yield to descend and problems such as chip reliability hidden danger.
The SOG flatening process is that the liquid solvent that contains dielectric material is coated in wafer surface uniformly with the mode of rotary coating, to fill up the hole of dielectric layer deposited depression, afterwards again through Overheating Treatment, can remove solvent, wafer surface stay curing like SiO
2Deng dielectric material.In production technology, the SOG flatening process comprises that mainly SOG coating, SOG reflux, SOG returns steps such as quarter.The wire structures that adopts the SOG planarization to form is as shown in Figure 2, comprising: Semiconductor substrate 20; First dielectric layer 21 covers on Semiconductor substrate 20 and its and is formed with perforate; The first metal layer 22 covers first dielectric layer 21 and fills perforate wherein, also is formed with perforate on the first metal layer 22; SOG packed layer 25, the recess that is filled in said the first metal layer 22 with and on perforate in; Second dielectric layer 23 also is formed with perforate on covering the first metal layer 22 and SOG packed layer 25, the second dielectric layers 23; Second metal level 24 covers second dielectric layer 23 and fills the perforate on it.
Band glue returns and carves flatening process is other a kind of flatening process, mainly may further comprise the steps: deposit one deck earlier
About SiO
2Layer is then at SiO
2Photoresist on the layer about coating 1.0 μ m; Adopt etching apparatus afterwards,, adopt CF like Lam4520 etc.
4, CHF
3, O
2Deng etching gas, adjustment gas flow and power are with SiO
2Be adjusted into 1: 1 with the etching selection ratio of photoresist, form SiO after the etching in the pit
2Fill; Carry out the deposition of subsequent film afterwards again, so just can form comparatively smooth dielectric layer pattern, cover and filling capacity thereby can have good dielectric layer.
The SOG flatening process; Particularly being with glue to return to carve the SOG flatening process to increase multistep processing step and corresponding apparatus, and the cost of employed SOG material is higher in the SOG flatening process, and storage and application process require strict to temperature, humidity etc.; Cause SOG flatening process processing cost higher; Be easy to generate film simultaneously and split, technological problemses such as the SOG moisture absorption, via aperture occur, be unfavorable for the stability of controlling manufacturing cost and processing quality; Return with glue simultaneously and carve the SOG flatening process also need increase costliness when increasing processing step equipment, also be unfavorable for the control of cost.
The utility model content
The technical problem that the utility model will solve provides a kind of wire structures; Do not adopting SOG planarization, band glue to return under the prerequisite of carving technologies such as SOG planarization; Satisfy and to close on submicron order 1.5 μ m and following technique platform thereof demand, and help reducing cost planarization.
For solving the problems of the technologies described above, the utility model provides a kind of wire structures, comprising:
Semiconductor substrate;
Be positioned at first dielectric layer on the said Semiconductor substrate;
Be formed at the contact hole on said first dielectric layer;
The first metal layer, said the first metal layer cover the bottom and the sidewall of said contact hole, and cover the upper surface of said first dielectric layer;
Be formed at first opening on the said the first metal layer;
Second dielectric layer, said second dielectric layer covers the bottom and the sidewall of said first opening, and covers the upper surface of said the first metal layer;
Be formed at the through hole on said second dielectric layer;
Second metal level, said second metal level covers the bottom and the sidewall of said through hole, and covers the upper surface of said second dielectric layer;
Be formed at second opening on said second metal level.
Alternatively; The sidewall of said contact hole comprises the upper side wall and the lower wall of joining up and down; The angle of said upper side wall and the said first dielectric layer upper surfaces level direction is 30 ° to 60 °, and the angle of said lower wall and said Semiconductor substrate upper surfaces level direction is 85 ° to 90 °.
Alternatively, said first opening is a bowl-mouth shape, and the sidewall of said first opening comprises the curved wall and the flat sidewall of joining up and down, and wherein the vertical height of curved wall accounts for 25% to 40% of said the first metal layer gross thickness.
Alternatively, the thickness of said second dielectric layer is
Alternatively; The ratio of thickness and the thickness of second dielectric layer that covers said first open bottom that covers second dielectric layer of said first opening sidewalls is 0.6～0.8; The ratio of thickness and the thickness of second dielectric layer that covers said the first metal layer upper surface that covers second dielectric layer of said first opening sidewalls is 0.45～0.65, and the ratio of thickness and the thickness of second dielectric layer that covers said the first metal layer upper surface that covers second dielectric layer of said first open bottom is 0.6～0.9.
Alternatively, the angle of the upper surfaces level direction of said through-hole side wall and said Semiconductor substrate is 55 ° to 70 °.
Alternatively, said second opening is a bowl-mouth shape, and the sidewall of said second opening comprises the curved wall and the flat sidewall of joining up and down, and wherein the vertical height of curved wall accounts for 20% to 35% of the said second metal level gross thickness.
Alternatively, said wire structures also comprises:
Passivation layer, said passivation layer cover the bottom and the sidewall of said second opening, and cover the upper surface of said second metal level and second dielectric layer.
Alternatively; Said passivation layer is a laminated construction, comprising: the first non-impurity-doped silica glass layer, be positioned at phosphorosilicate glass layer on the said first non-impurity-doped silica glass layer, be positioned at the second non-impurity-doped silica glass layer on the said phosphorosilicate glass layer and be positioned at the silicon nitride layer on the second non-impurity-doped silica glass layer.
Compared with prior art, the utlity model has following advantage:
In the wire structures of the utility model embodiment; Contact hole on first dielectric layer is an inclined hole; Its sidewall comprises the upper side wall and the lower wall of joining up and down; Wherein the angle of the upper side wall and the first dielectric layer upper surfaces level direction is 30 ° to 60 °, and the angle of lower wall and said Semiconductor substrate upper surfaces level direction is 85 ° to 90 °, helps improving the step appearance of covering the first metal layer above that; And first opening on the first metal layer be shaped as bowl-mouth shape; Help covering the formation of the climbing pattern of second dielectric layer above that, thereby can under the prerequisite that does not adopt the SOG flatening process, satisfy step coverage, the isoparametric requirement of step appearance, also help reducing cost simultaneously.
Further, second opening shape on second metal level among the utility model embodiment is the rim of a bowl shape, helps improving the passivation layer step appearance that covers on it.
In addition, the passivation layer of the utility model embodiment adopts silica-silicon nitride multi-layer compound structure, has scratch resistance, anti-humidity, high-compactness, low membrane stress, higher gettering ability, step covering preferably and good advantages such as photoelectric properties.
Description of drawings
Fig. 1 is the cross-sectional view of a kind of wire structures in the prior art;
Fig. 2 is the cross-sectional view of another kind of wire structures in the prior art;
Fig. 3 is the schematic flow sheet of formation method of the wire structures of the utility model embodiment;
Fig. 4 to Figure 13 is the cross-sectional view of each step in the formation method of wire structures of the utility model embodiment.
Embodiment
The wire structures of prior art forms in the technology, often adopt method such as SOG flatening process to fill the depression in anterior layer dielectric layer, the metal level, but this class methods technology is comparatively complicated, and is unfavorable for the control of cost.
Present embodiment is under the prerequisite that does not adopt the SOG flatening process; Through adopting the inclined hole contact hole and falling trapezoidal through-hole structure; And the metal level opening of bowl-mouth shape improves the climbing pattern of each rete; To satisfy step coverage, the isoparametric requirement of step appearance, also help reducing cost simultaneously.
Below in conjunction with specific embodiment and accompanying drawing the utility model is described further, but should limit the protection range of the utility model with this.
Fig. 3 shows the schematic flow sheet of formation method of the wire structures of present embodiment, comprising:
Step S31 provides Semiconductor substrate, is formed with first dielectric layer on the said Semiconductor substrate;
Step S32 forms contact hole on said first dielectric layer;
Step S33, the deposition the first metal layer, said the first metal layer covers the bottom and the sidewall of said contact hole, and covers the upper surface of said first dielectric layer;
Step S34 carries out etching to said the first metal layer, to form first opening above that;
Step S35 deposits second dielectric layer, and said second dielectric layer covers the bottom and the sidewall of said first opening, and covers the upper surface of said the first metal layer;
Step S36 carries out etching to said second dielectric layer, on said second dielectric layer, forms through hole;
Step S37, deposition second layer metal layer, said second metal level covers the bottom and the sidewall of said through hole, and covers the upper surface of said second dielectric layer;
Step S38 carries out etching to said second metal level, to form second opening above that;
Step S39, the deposit passivation layer covers the bottom and the sidewall of said second opening, and covers the upper surface of said second metal level and second dielectric layer
Fig. 4 to Figure 13 shows the corresponding generalized section of each step in the formation method of wire structures of present embodiment, is elaborated below in conjunction with Fig. 3 and Fig. 4 to Figure 13.
In conjunction with Fig. 3 and Fig. 4, execution in step S31 provides Semiconductor substrate 40, is formed with first dielectric layer 41 on the Semiconductor substrate 40.
Wherein, Semiconductor substrate 40 can be silicon substrate, germanium silicon substrate, III-V group element compound substrate or well known to a person skilled in the art other semiconductive material substrate that what adopt in the present embodiment is silicon substrate.More specifically, what adopt in the present embodiment is silicon substrate, can be formed with semiconductor device such as MOS field-effect transistor, bipolar transistor in the Semiconductor substrate 40.First dielectric layer 41 can adopt the silex glass of silica, doping etc.
In conjunction with Fig. 3, Fig. 5 and Fig. 6; Wherein Fig. 6 is the partial enlarged drawing of contact hole 42 among Fig. 5; Execution in step S32 forms contact hole 42 on first dielectric layer 41, the sidewall of contact hole 42 comprises upper side wall 42a and the lower wall 42b that joins up and down; The angle theta 1 of upper side wall 42a and first dielectric layer, 41 upper surfaces level directions is 30 ° to 60 °, and the angle theta 2 of lower wall 42b and Semiconductor substrate 40 upper surfaces level directions is 85 ° to 90 °.
The forming process of contact hole 42 can adopt dry etching to add the wet method etching and realize, forms contact hole 42 and can clean the surface of first dielectric layer 41 afterwards.
Contact hole 42 adopts above-mentioned shape, and the rete that helps subsequent deposition forms the climbing pattern, improves step coverage.
In conjunction with Fig. 3 and Fig. 7, execution in step S33, deposition the first metal layer 43, the first metal layer 43 covers the bottom and the sidewall of contact hole 42, and covers the upper surface of first dielectric layer 41.In the present embodiment, the first metal layer 43 is a laminated construction, comprises the Al/Si alloy-layer 43a that covers on first dielectric layer, 41 upper surfaces and is positioned at the Al/Si/Cu alloy-layer 43b on the Al/Si alloy-layer 43a.
The gross thickness of the first metal layer 43 is that
reflectivity is between 210～250%.
Concrete, Al/Si alloy-layer 43a contacts with Semiconductor substrate 40, helps reducing contact resistance, reduces cut-in voltage.Si accounts for 0.5% among the Al/Si/Cu alloy-layer 43b, and Cu accounts for 1%, and all the other are Al, can reduce effectively that silicon is separated out and electromigration, improves the performance of entire device.
In conjunction with Fig. 3 and Fig. 8, execution in step S34 carries out etching to the first metal layer 43, to form first opening 44 above that.
The sidewall of first opening 44 comprises curved wall 44a and the flat sidewall 44b that joins up and down; Wherein curved wall 44a is that wet-etching technology forms; Its vertical height a accounts for 25% to 40% of the first metal layer 43 gross thickness, and the thickness a of the first metal layer 43 that is promptly corroded in the wet etching process accounts for 25% to 40% of the first metal layer 43 gross thickness.
In conjunction with Fig. 3 and Fig. 9, execution in step S35 deposits second dielectric layer, 45, the second dielectric layers 45 and covers the bottom and the sidewall of first opening 44, and covers the upper surface of the first metal layer 43.
As a preferred embodiment; Second dielectric layer 45 adopts liquid tetraethoxysilane deposition to form; Compare with traditional diffusion furnace tube SiCL4 deposit; Have higher mobility, very high step coverage and clearance filling capability, via etch is shaped as trapezoidally simultaneously, helps improving the step appearance of subsequent metal layer and passivation layer.。And in traditional small size technology; After forming dielectric layer, also need carry out the SOG flatening process; But SOG is owing to receive the restriction of conditions such as temperature, humidity, stand-by period; Occur problems such as film splits easily, receive equipment, technology and cost restriction simultaneously, if but adopt traditional silane (SiH
4) deposition, then occur the crack easily and cause technology and security risk.
Concrete; In the present embodiment, the technological parameter that adopts liquid tetraethoxysilance deposition to form second dielectric layer 45 is: the pressure in the deposit cavity is 5.0～7.0Torr, and depositing temperature is 350～450 ℃; Radio-frequency power is 350～450W, and in deposition process, feeds an amount of helium and oxygen.
In the present embodiment; The thickness of second dielectric layer 45 is 1.4～4.5 for
its refractive index; Film thickness uniformity is in 3%; Etch rate is that
is more concrete; The ratio of thickness c and the thickness b of second dielectric layer 45 that covers first opening, 44 bottoms that covers second dielectric layer 45 of first opening, 44 sidewalls is 0.6～0.8; The ratio of thickness c and the thickness d of second dielectric layer 45 that covers the first metal layer 43 upper surfaces that covers second dielectric layer 45 of first opening, 44 sidewalls is 0.45～0.65, and the ratio of thickness b and the thickness d of second dielectric layer 45 that covers the first metal layer 43 upper surfaces that covers second dielectric layer 45 of first opening, 44 bottoms is 0.6～0.9.
Combine Fig. 3 and Figure 10 afterwards, execution in step S36 carries out etching to said second dielectric layer 45, on second dielectric layer 45, forms through hole 46.The bottom-exposed of through hole 46 goes out the upper surface of the first metal layer 43.The forming process of through hole 46 can comprise: the positive glue that adopts 1.8～2.2 μ m thickness; Form the photoresist figure through steps such as even glue, exposure, development, postdevelopment bakes; Adopt dry etching to combine endpoint Detection to form through hole 46 afterwards, carry out again afterwards that dry method is removed photoresist, reprocessing, bath etc.Wherein, The temperature of postdevelopment bake is 145～155 ℃, compares with traditional baking temperature, and the high-temperature baking of this step can be so that the photoresist of step position can form good adhesiveness; Be difficult for producing crepe rubber, simultaneously also can be so that the photoresist figure forms inverted trapezoidal structure preferably; In the dry etching process, vacuum degree is 0.7～0.9Torr, and feeds a certain proportion of O
2And CHF
3
The angle theta 3 of upper surfaces level direction of sidewall and the first metal layer 43 of trapezoidal through hole 46 of falling is 55 ° to 70 °, helps the follow-up climbing that is formed on the metal level on second dielectric layer 45.
Combine Fig. 3 and Figure 11 afterwards, execution in step S36 deposits second metal level, 47, the second metal levels 47 and covers the bottom and the sidewall of through hole 46, and covers the upper surface of second dielectric layer 45.
Before forming second metal level 47, can carry out the RF backwash, radio-frequency power is 850KW, the time is 100～140 seconds, thereby with aluminium oxide and other Impurity removals of the first metal layer 43 upper surfaces, thereby improve the binding ability between the two metal layers.
In the present embodiment; The material of second metal level 47 is the Al/Si/Cu alloy-layer; Depositing temperature is 240～260 ℃; Power is 7～9KW, chamber pressure position 2～4Torr, and the thickness of formed second metal level 47 is 190～230% for
reflectivity.
Combine Fig. 3 and Figure 12 afterwards; Execution in step S38; Second metal level 47 is carried out etching, form second opening 48, its forming process mainly comprises wet etching and dry etching; More specifically comprise: adopt the positive glue of 1.8～2.2 μ m, through baking before even glue, exposure, development, the etching, beat that glue, wet etching, the preceding baking of dry etching, dry etching, bath, dry method remove photoresist, reprocessing.Concrete; What adopt in the wet etching process is the aluminium corrosive liquid; Temperature is 29～31 ℃, and the thickness that wet etching corroded accounts for 20～35% of second metal level, 47 gross thickness, and promptly the vertical height of the curved wall on second opening, 48 tops accounts for 20～35% of second metal level, 47 gross thickness; In the dry etching, the etching gas of employing mainly contains CF
4, BCl
3And an amount of N
2And O
2Deng.Second opening 48 of bowl-mouth shape helps the spreadability of follow-up level, can form good climbing pattern.
Combine Fig. 3 and Figure 13 afterwards, execution in step S39, deposit passivation layer 49 covers the bottom and the sidewall of second opening 48, and covers the upper surface of second metal level 47 and second dielectric layer 45.In the present embodiment; Passivation layer 49 is a laminated construction, specifically comprises: the first non-impurity-doped silica glass layer (USG), be positioned at phosphorosilicate glass layer (PSG) on the first non-impurity-doped silica glass layer, be positioned at the second non-impurity-doped silica glass layer on this phosphorosilicate glass layer and be positioned at the silicon nitride layer on this second non-impurity-doped silica glass layer.Wherein, the thickness of a USG layer removes photoresist etc. for the forming process of
passivation layer 49 can comprise preceding baking, exposure, development, post bake, dry etching, dry method for the thickness of
silicon nitride layer for the thickness of
the 2nd USG layer for the thickness of
PSG layer.
So far, the formed wire structures of present embodiment is shown in figure 13, comprising: Semiconductor substrate 40; Be positioned at first dielectric layer 41 on the Semiconductor substrate 40; Be formed at the contact hole on first dielectric layer 41; The first metal layer 43, the first metal layer 43 covers the bottom and the sidewall of contact hole, and covers the upper surface of first dielectric layer 41; Be formed at first opening on the first metal layer 43; Second dielectric layer, 45, the second dielectric layers 45 cover the bottom and the sidewall of first opening, and cover the upper surface of the first metal layer 43; Be formed at the through hole on second dielectric layer 45; Second metal level, 47, the second metal levels 47 cover the bottom and the sidewall of through hole, and cover the upper surface of second dielectric layer 45; Be formed at second opening 48 on second metal level 47; Passivation layer 49 covers the bottom and the sidewall of second opening 48, and covers the upper surface of second metal level 47 and second dielectric layer 48.
Wherein, the sidewall of contact hole comprises the upper side wall and the lower wall of joining up and down, and the angle of upper side wall and first dielectric layer, 41 upper surfaces level directions is 30 ° to 60 °, and the angle of lower wall and Semiconductor substrate 40 upper surfaces level directions is 85 ° to 90 °; First opening and second opening are bowl-mouth shape; Through hole is for falling trapezoidal shape; The sidewall of first opening and second opening comprises the curved wall and the flat sidewall of joining up and down; Preferably; For first opening; The vertical height of curved wall accounts for 25% to 40% of the first metal layer 43 gross thickness, and for second opening, the vertical height of curved wall accounts for 20% to 35% of second metal level, 47 gross thickness.
About the more detail parameters and the content of this wire structures, see also the detailed process of the formation method of wire structures in the foregoing description, repeat no more here.
Need to prove; Though have two metal layers in the formed wire structures in the present embodiment; But those skilled in the art should it is understandable that, in practical application, can form the metal level of other quantity as required; As 1 layer, 3 layers etc., and passivation layer is formed on the metal level of the superiors.
To sum up, the foregoing description is through the optimization to the opening pattern on contact hole shape looks, the first metal layer, second metal level, and to second dielectric layer and on the optimization of through hole pattern; Can be under 1.5 μ m technique platforms; Develop the wire structures and the process of the no SOG planarization of satisfying 1.2 μ m process conditions, can solve in the prior art contact hole ground floor metal level bigger than normal, that the dielectric layer fracture causes and be corroded, open problems such as short circuit, power supply electric leakage, through hole be logical over the ground, improved reliability of products; Can improve transistorized little current amplification factor; Improve the photoelectric properties of chip, promote the product yield, reduce product cost; When promoting properties of product and reliability, also improved the benefit of enterprise.
Though the utility model with preferred embodiment openly as above; But it is not to be used for limiting the utility model; Any those skilled in the art are in spirit that does not break away from the utility model and scope; Can make possible change and modification, so the protection range of the utility model should be as the criterion with the scope that the utility model claim is defined.
Claims (9)
1. a wire structures is characterized in that, comprising:
Semiconductor substrate;
Be positioned at first dielectric layer on the said Semiconductor substrate;
Be formed at the contact hole on said first dielectric layer;
The first metal layer, said the first metal layer cover the bottom and the sidewall of said contact hole, and cover the upper surface of said first dielectric layer;
Be formed at first opening on the said the first metal layer;
Second dielectric layer, said second dielectric layer covers the bottom and the sidewall of said first opening, and covers the upper surface of said the first metal layer;
Be formed at the through hole on said second dielectric layer;
Second metal level, said second metal level covers the bottom and the sidewall of said through hole, and covers the upper surface of said second dielectric layer;
Be formed at second opening on said second metal level.
2. the formation method of wire structures according to claim 1; It is characterized in that; The sidewall of said contact hole comprises the upper side wall and the lower wall of joining up and down; The angle of said upper side wall and the said first dielectric layer upper surfaces level direction is 30 ° to 60 °, and the angle of said lower wall and said Semiconductor substrate upper surfaces level direction is 85 ° to 90 °.
3. wire structures according to claim 1; It is characterized in that; Said first opening is a bowl-mouth shape, and the sidewall of said first opening comprises the curved wall and the flat sidewall of joining up and down, and wherein the vertical height of curved wall accounts for 25% to 40% of said the first metal layer gross thickness.
4. wire structures according to claim 1; It is characterized in that the thickness of said second dielectric layer is
5. according to each described wire structures in the claim 1 to 4; It is characterized in that; The ratio of thickness and the thickness of second dielectric layer that covers said first open bottom that covers second dielectric layer of said first opening sidewalls is 0.6～0.8; The ratio of thickness and the thickness of second dielectric layer that covers said the first metal layer upper surface that covers second dielectric layer of said first opening sidewalls is 0.45～0.65, and the ratio of thickness and the thickness of second dielectric layer that covers said the first metal layer upper surface that covers second dielectric layer of said first open bottom is 0.6～0.9.
6. wire structures according to claim 1 is characterized in that, the angle of the upper surfaces level direction of said through-hole side wall and said Semiconductor substrate is 55 ° to 70 °.
7. wire structures according to claim 1; It is characterized in that; Said second opening is a bowl-mouth shape, and the sidewall of said second opening comprises the curved wall and the flat sidewall of joining up and down, and wherein the vertical height of curved wall accounts for 20% to 35% of the said second metal level gross thickness.
8. wire structures according to claim 1 is characterized in that, also comprises:
Passivation layer, said passivation layer cover the bottom and the sidewall of said second opening, and cover the upper surface of said second metal level and second dielectric layer.
9. wire structures according to claim 8; It is characterized in that; Said passivation layer is a laminated construction, comprising: the first non-impurity-doped silica glass layer, be positioned at phosphorosilicate glass layer on the said first non-impurity-doped silica glass layer, be positioned at the second non-impurity-doped silica glass layer on the said phosphorosilicate glass layer and be positioned at the silicon nitride layer on the second non-impurity-doped silica glass layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120449942XU CN202307877U (en) | 2011-11-14 | 2011-11-14 | Wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120449942XU CN202307877U (en) | 2011-11-14 | 2011-11-14 | Wiring structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202307877U true CN202307877U (en) | 2012-07-04 |
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ID=46376718
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104377180A (en) * | 2014-11-24 | 2015-02-25 | 苏州晶方半导体科技股份有限公司 | Silicon through hole structure and forming method thereof |
-
2011
- 2011-11-14 CN CN201120449942XU patent/CN202307877U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104377180A (en) * | 2014-11-24 | 2015-02-25 | 苏州晶方半导体科技股份有限公司 | Silicon through hole structure and forming method thereof |
| CN104377180B (en) * | 2014-11-24 | 2018-09-28 | 苏州晶方半导体科技股份有限公司 | Through-silicon via structure and forming method thereof |
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