CN202282343U - Semiconductor packaging piece - Google Patents

Semiconductor packaging piece Download PDF

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Publication number
CN202282343U
CN202282343U CN 201120351130 CN201120351130U CN202282343U CN 202282343 U CN202282343 U CN 202282343U CN 201120351130 CN201120351130 CN 201120351130 CN 201120351130 U CN201120351130 U CN 201120351130U CN 202282343 U CN202282343 U CN 202282343U
Authority
CN
China
Prior art keywords
chip
semiconductor
lead frame
chip carrier
package part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 201120351130
Other languages
Chinese (zh)
Inventor
陈庠稀
陈思翰
谢兴友
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHENZHEN ZHONGXINGHUA ELECTRONICS CO LTD
Original Assignee
SHENZHEN ZHONGXINGHUA ELECTRONICS CO LTD
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHENZHEN ZHONGXINGHUA ELECTRONICS CO LTD filed Critical SHENZHEN ZHONGXINGHUA ELECTRONICS CO LTD
Priority to CN 201120351130 priority Critical patent/CN202282343U/en
Application granted granted Critical
Publication of CN202282343U publication Critical patent/CN202282343U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor packaging piece comprises a lead frame, a semiconductor chip, and a packaging glue; wherein the lead frame comprises a chip holder formed by a heat conducting metal, the chip holder is provided with an upper surface and a lower surface; the semiconductor chip is fixed on the upper surface of the chip holder and is electrically connected with the lead frame; and the packaging glue is used for encapsulating the lead frame and the semiconductor chip, and enables the lower surface of the chip holder to expose outside. According to the semiconductor packaging piece of the utility model, the semiconductor packaging piece comprises the chip holder formed by the heat conducting metal, the packaging glue encapsulates the lead frame and the semiconductor chip fixed on the upper surface of the chip holder, and enables the lower surface of the chip holder to expose outside, in this way, when the semiconductor chip drives, the heat can radiate outside the semiconductor packaging piece through the chip holder, therefore, the semiconductor packaging piece of the utility model has a low packaging cost.

Description

Semiconductor package part
[technical field]
The utility model relates to semiconductor package part, particularly relates to a kind of semiconductor package part with radiator structure.
[background technology]
Along with the function of the electronic building brick trend of complicacy and volume miniaturization thereof day by day, the integrated circuit of electronic building brick also increases because of the heat that work produces thereupon, thereby has shortened the life-span of semiconductor chip.And traditional semiconductor package part increases fin usually in order to make the semiconductor chip can be not overheated in semiconductor package part, but has but increased the cost of encapsulation.
[utility model content]
Based on this, be necessary the packages part that provides a kind of packaging cost low.
A kind of semiconductor package part comprises:
Lead frame has the chip carrier that is made up of heat-conducting metal, and said chip carrier has upper surface and lower surface;
Semiconductor chip is fixed in the upper surface of said chip carrier, electrically connects with said lead frame; And
Packaging plastic is used to seal said lead frame and semiconductor chip, and the lower surface of said chip carrier is exposed.
In a preferred embodiment, said semiconductor package part also comprises the bonding metal layer that said semiconductor chip is fixed in the upper surface of said chip carrier.
In a preferred embodiment, said semiconductor package part also comprises the coating layer of the lower surface that is covered in said chip carrier.
In a preferred embodiment, said lead frame also comprises the pin that electrically connects, is positioned at said chip carrier both sides with said semiconductor chip, and said pin is partially encapsulated in said packaging plastic.
In a preferred embodiment, said pin and said semiconductor chip electrically connect through the metal connecting line.
Above-mentioned semiconductor package part has the chip carrier that is made up of heat-conducting metal; Packaging plastic is sealed lead frame and the semiconductor chip that is fixed on the upper surface of chip carrier; And the lower surface of chip carrier exposed, during semiconductor chips drive, just can heat be dispersed into the outside of semiconductor package part through chip carrier; Therefore, above-mentioned semiconductor package part has lower packaging cost.
[description of drawings]
Fig. 1 is the generalized section of the semiconductor package part of an execution mode.
[embodiment]
Below in conjunction with accompanying drawing and embodiment this is used novel further explain.
As shown in Figure 1, the semiconductor package part 100 of an execution mode comprises lead frame 110, semiconductor chip 120, bonding metal layer 130, packaging plastic 140 and coating layer 150.
Lead frame 110 comprises chip carrier 112 and pin 114.Chip carrier 112 is made up of heat-conducting metal, and this heat-conducting metal can be copper, copper alloy or iron-nickel alloy, is preferably copper.Chip carrier 112 has upper surface 1122 and lower surface 1124.Pin 114 is positioned at the both sides of chip carrier 112.
Semiconductor chip 120 is fixed in the upper surface 1122 of chip carrier 112, electrically connects with lead frame 110.Pin 114 electrically connects through metal connecting line 122 with semiconductor chip 120.Metal connecting line 122 is preferably wire jumper.Metal connecting line 122 is preferably two, and its two ends are connected with semiconductor chip 120 and pin 114 respectively through the mode of welding.
Bonding metal layer 130 is fixed in semiconductor chip 120 upper surface 1122 of chip carrier 112.The material of bonding metal layer 130 is the metallic colloid with performances such as desirable viscosity, flowability and conductivity, is preferably elargol.
Packaging plastic 140 is used to seal lead frame 110 and semiconductor chip 120, and the lower surface 1124 of chip carrier 112 is exposed.Pin 114 is partially encapsulated in packaging plastic.The material of packaging plastic 140 can be preferably the epoxies packaging plastic, for example epoxy encapsulation glue for epoxies packaging plastic, silicone based packaging plastic, polyurethane encapsulation glue and ultraviolet photo-curing packaging plastic etc.
Coating layer 150 is covered in the lower surface 1124 of chip carrier 112.The material of coating layer 150 is good heat conductivity, has the non-copper metal of antioxygenic property, is preferably tin.The thickness of coating layer 150 is less than 100 dusts.Can directly tin be covered in the lower surface 1124 of chip carrier 112 through the mode of electroplating, thereby form coating layer 150, coating layer 150 can prevent the copper oxidation.
Above-mentioned semiconductor package part 100 has the chip carrier 112 that is made up of heat-conducting metal; Packaging plastic 140 is sealed lead frame 110 and the semiconductor chip 120 that is fixed on the upper surface 1122 of chip carrier 112; And the lower surface 1124 of chip carrier 112 exposed, when semiconductor chip 120 drives, just can heat be dispersed into the outside of semiconductor package part 100 through chip carrier 112; Therefore, above-mentioned semiconductor package part 100 has lower packaging cost.
In addition, above-mentioned semiconductor package part 100 need not outer radiation fin just can reach radiating effect, and simple in structure, the life-span is longer.
The above embodiment has only expressed several kinds of execution modes of the utility model, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the utility model claim.Should be pointed out that for the person of ordinary skill of the art under the prerequisite that does not break away from the utility model design, can also make some distortion and improvement, these all belong to the protection range of the utility model.Therefore, the protection range of the utility model patent should be as the criterion with accompanying claims.

Claims (5)

1. a semiconductor package part is characterized in that, comprising:
Lead frame has the chip carrier that is made up of heat-conducting metal, and said chip carrier has upper surface and lower surface;
Semiconductor chip is fixed in the upper surface of said chip carrier, electrically connects with said lead frame; And
Packaging plastic is used to seal said lead frame and semiconductor chip, and the lower surface of said chip carrier is exposed.
2. semiconductor package part according to claim 1 is characterized in that, said semiconductor package part also comprises the bonding metal layer that said semiconductor chip is fixed in the upper surface of said chip carrier.
3. semiconductor package part according to claim 1 is characterized in that said semiconductor package part also comprises the coating layer of the lower surface that is covered in said chip carrier.
4. semiconductor package part according to claim 1 is characterized in that, said lead frame also comprises the pin that electrically connects, is positioned at said chip carrier both sides with said semiconductor chip, and said pin is partially encapsulated in said packaging plastic.
5. semiconductor package part according to claim 4 is characterized in that, said pin and said semiconductor chip electrically connect through the metal connecting line.
CN 201120351130 2011-09-19 2011-09-19 Semiconductor packaging piece Expired - Fee Related CN202282343U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201120351130 CN202282343U (en) 2011-09-19 2011-09-19 Semiconductor packaging piece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201120351130 CN202282343U (en) 2011-09-19 2011-09-19 Semiconductor packaging piece

Publications (1)

Publication Number Publication Date
CN202282343U true CN202282343U (en) 2012-06-20

Family

ID=46228500

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201120351130 Expired - Fee Related CN202282343U (en) 2011-09-19 2011-09-19 Semiconductor packaging piece

Country Status (1)

Country Link
CN (1) CN202282343U (en)

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120620

Termination date: 20120919