CN202275838U - Solar cell and back electrode structure thereof - Google Patents
Solar cell and back electrode structure thereof Download PDFInfo
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- CN202275838U CN202275838U CN 201120364427 CN201120364427U CN202275838U CN 202275838 U CN202275838 U CN 202275838U CN 201120364427 CN201120364427 CN 201120364427 CN 201120364427 U CN201120364427 U CN 201120364427U CN 202275838 U CN202275838 U CN 202275838U
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- 239000000758 substrate Substances 0.000 claims abstract description 124
- 239000004020 conductor Substances 0.000 claims abstract description 88
- 238000002161 passivation Methods 0.000 claims abstract description 74
- 239000004065 semiconductor Substances 0.000 claims description 60
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005245 sintering Methods 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000004411 aluminium Substances 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
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- 238000005516 engineering process Methods 0.000 description 3
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- 238000010248 power generation Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
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- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 239000013081 microcrystal Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
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- 229910000632 Alusil Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
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- 238000007740 vapor deposition Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/542—Dye sensitized solar cells
Abstract
The utility model relates to a back electrode structure of a solar cell. The back electrode structure comprises a substrate, a passivation layer and a plurality of conductive materials. The passivation layer is arranged on the substrate, and the passivation layer comprises a plurality of open holes. The conductive materials are arranged on the passivation layer at intervals and arranged corresponding to the open holes, and the conductive materials are connected with the substrate through the open holes. The back electrode structure disclosed by the utility model can increase the degree of electrical connection between the substrate and a back electrode, avoid the formation of cavities between the substrate and the conductive materials and further upgrade the conductivity of the back electrode. The utility model further discloses the solar cell applying the back electrode structure of the solar cell.
Description
Technical field
The utility model is about a kind of solar cell and backplate structure thereof.
Background technology
Because the oil fuel in the whole world is petered out at present; Therefore the energy that people actively seek and exploitation substitutes; Like solar power generation, wind power generation and hydroelectric power generation ... Deng, and wherein with the topmost technological development direction of being utilized as of solar energy, reason is that sunlight can be radiated at each area, the whole world; And solar energy can not pollute environment in the process of changing; For instance, convert in the process of electric energy, need not cause the problem of greenhouse effect through consuming other energy at solar energy.But solar energy converting is the mechanism design that the conversion efficiency of electric energy but is subject to the whole solar cell system easily.
Basic solar cell framework can be divided into P-N diode (PN Diode), anti-reflecting layer (Antireflection) and front metal electrode (Front contact metal), reach back metal electrode four parts such as (Back contact metal).
Wherein, the processing procedure mode of backplate is with the method for aluminium glue with screen painting (Screen Printing) or vapor deposition, on the half-finished surface of wafer, produces conductive electrode, behind the high temperature sintering as back surface field (BSF), to increase the carrier collection efficiency.Yet, point out in the document that back surface field still can't effectively reduce surperficial recombination rate (SRV), therefore in order to reduce the complex effect of carrier electric current, effective ways can be provided with a passivation layer between substrate and backplate.Because the setting of passivation layer makes substrate and backplate directly to electrically connect, therefore must on passivation layer, produce perforate through physics or chemical mode, make substrate and backplate congruent melting and reach mutual electric connection with the mode of sintering again.
In known technology; The aluminium glue that one deck is set is at passivation layer; In sintering, aluminium molecule and silicon molecule can reach the temperature that a congruent melting (eutectic) is formed, and this moment, two kinds of materials can flow melting mutually under the factor each other; That is the silicon molecule of silicon substrate can flow to aluminium glue, and the aluminium molecule in the aluminium glue can flow to silicon substrate simultaneously.And the mobile factor that balances each other in addition of material itself; Two kinds of materials can be got back to composition originally when being lower than eutectic temperature; But because silicon molecule flowing velocity in aluminium glue is very slow, make the molecule that flows at temperature-fall period can't flow back to former one's respective area fast, cause silicon substrate and the aluminium glue junction of part after curing can produce a plurality of cavities; The electric connection degree that this not only reduces substrate and backplate also makes solar cell integrated efficient reduce.
Therefore; How a kind of solar cell and backplate structure thereof are provided; It is when increasing substrate and backplate electric connection degree; Also can avoid between substrate and backplate, forming the cavity, and then promote the photoelectric conversion efficiency of solar cell, become the emphasis problem of solar energy manufacturing industry.
The utility model content
The purpose of the utility model can increase substrate and backplate and electrically connect degree for a kind of rear surface of solar cell electrode structure is provided, and also can avoid forming the cavity between substrate and electric conducting material, to promote the conductance of backplate.
The utility model can adopt following technical scheme to realize.
A kind of rear surface of solar cell electrode structure of the utility model comprises a substrate, a passivation layer and a plurality of electric conducting material.Passivation layer is arranged on substrate, and passivation layer has a plurality of perforates.Said electric conducting material is arranged on passivation layer at interval, and corresponding said perforate setting, and said electric conducting material connects substrate through said perforate.
In an embodiment of the utility model, substrate is N type semiconductor substrate or P type semiconductor substrate.
In an embodiment of the utility model, the said perforate of passivation layer has one first width, first width greater than 50 μ m less than 300 μ m.
In an embodiment of the utility model, said electric conducting material has one second width, and less than 500 μ m, second width is more than or equal to first width greater than 50 μ m for second width.
In an embodiment of the utility model, said electric conducting material have one the height, the height greater than 5 μ m less than 40 μ m.
In addition, a kind of solar cell of the utility model comprises a substrate, two passivation layers and a plurality of electric conducting material.Substrate has a first surface and a second surface, and said passivation layer is separately positioned on the first surface and the second surface of substrate, and one of them passivation layer has a plurality of perforates.Said electric conducting material is arranged on the passivation layer with said perforate at interval, and said electric conducting material connects substrate through said perforate.
In an embodiment of the utility model, substrate is N type semiconductor substrate or P type semiconductor substrate.
In an embodiment of the utility model, the said perforate of passivation layer has one first width, first width greater than 50 μ m less than 300 μ m.
In an embodiment of the utility model, said electric conducting material has one second width, and less than 500 μ m, second width is more than or equal to first width greater than 50 μ m for second width.
In an embodiment of the utility model, said electric conducting material have one the height, the height greater than 5 μ m less than 40 μ m.
Hold the above; The rear surface of solar cell electrode structure of the utility model, the passivation layer through having perforate and the setting of electric conducting material make the electric conducting material that is arranged on surface backlight behind high temperature sintering; Can be connected with substrate, to reach the purpose that forms back surface field.It should be noted that the passivation layer on surface backlight forms a plurality of perforates, continuing is arranged on said passivation layer with electric conducting material, makes substrate and electric conducting material when sintering, can merge each other, reaches preferable electric connection; And after substrate and electric conducting material curing, also can avoid between substrate and electric conducting material, forming the cavity, and then promote the conductance of backplate.
Description of drawings
Fig. 1 is the sketch map according to a kind of rear surface of solar cell electrode structure of the utility model preferred embodiment;
Fig. 2 is the flow process generalized section of making according to the rear surface of solar cell electrode structure of the utility model; And
Fig. 3 is the sketch map according to a kind of solar cell of the utility model preferred embodiment.
The main element symbol description:
1: the rear surface of solar cell electrode structure
11,21: substrate
111,211,221: first surface
112,212,222: second surface
12,23,24: passivation layer
121,241: perforate
13,25,26: electric conducting material
2: solar cell
22: semiconductor layer
D1, d3: first width
D2, d4: second width
H, h1: highly
Embodiment
Below will a kind of solar cell and backplate structure thereof according to the utility model preferred embodiment be described with reference to correlative type, wherein components identical will be explained with the components identical symbol.
Please with reference to Fig. 1 and shown in Figure 2, Fig. 1 is the sketch map of a kind of rear surface of solar cell electrode structure of the utility model preferred embodiment, and Fig. 2 is the flow process generalized section of making according to the utility model rear surface of solar cell electrode structure.What must specify is, the proportionate relationship of each structure among Fig. 1 and Fig. 2 shows for ease and explains, thus possibly not be inconsistent in the ratio of practical structures, at this for reference only but not be restricted.Rear surface of solar cell electrode structure 1 comprises a substrate 11, a passivation layer 12 and a plurality of electric conducting material 13.
A plurality of electric conducting materials 13 are arranged on passivation layer 12 at interval.Utilization is arranged on passivation layer 12 such as but not limited to modes such as screen painting (Screen printing), coatings with said electric conducting material 13.It should be noted that; The said perforate 121 of the said electric conducting material 13 corresponding passivation layers 12 of present embodiment is provided with; The aspect of electric conducting material 13 can be such as but not limited to linear, dotted line shape, oblique line striated, round point shape or poroid etc., because the said perforate of present embodiment 121 is an example with the strip, therefore said electric conducting material 13 also is formed on passivation layer 12 with the aspect of strip; And for being arranged on passivation layer 12 at interval, to form local wire mark.It should be noted that be arranged on collinear a plurality of electric conducting material 13 can be continuous or discontinuous, that is; Said electric conducting material 13 can segment identifier at a distance from and linear array be arranged on passivation layer 12; Or be arranged on passivation layer 12 with the continuous lines strip, wherein, the separated spacing of segment identifier can be different because of design or demand; And be designed to different length or aspect, also can the electric conducting material 13 of different aspects be arranged on same row or be connected.In addition, the electric conducting material 13 of present embodiment is pastel or jelly, and its material is example with the aluminium glue, also can be tin indium oxide, nickel, copper, titanium, aluminium or tin.Moreover the said electric conducting material 13 of present embodiment has one second a width d2 and a height h, and wherein, the second width d2 is more than or equal to the first width d1, and the scope of the second width d2 is less than 500 μ m greater than 80 μ m.And the scope of height h is less than 30 μ m greater than 5 μ m.
Because; Be arranged on the said electric conducting material 13 and the disconnected setting of substrate of passivation layer 12; For said electric conducting material 13 can be electrically connected through said perforate 121 and substrate 11, therefore, a plurality of electric conducting materials 13 are set after passivation layer 12; Substrate 11 and said electric conducting material 13 are carried out sintering, in order to the electric conducting material 13 of sintering glue or pasty state.Volatilizable solvent in the said electric conducting material 13 is removed in the action of sintering, is for example toasting sintering under 570~840 ℃ the temperature, so that 13 metallization of said electric conducting material.More detailed; The action of sintering is sintered base plate 11 and said electric conducting material 13; When sintering reaches certain temperature (for example 577 ℃); Promptly can produce the phenomenon of congruent melting, then the molecular structure of substrate 11 and said electric conducting material 13 will change, and make the said perforate 121 that penetrates passivation layer 12 at substrate 11 and said electric conducting material 13 merge each other and be connected.Height h that it should be noted that the said electric conducting material 13 of present embodiment is relevant with the quantity that the silicon atom of substrate 11 diffuses into said electric conducting material 13.
Then, solidify substrate 11 and electric conducting material 13.As shown in Figure 1, it also is the sketch map of rear surface of solar cell electrode after curing.The said perforate 121 that said electric conducting material 13 after the curing penetrates passivation layer 12 is connected with substrate 11, and then reaches the structure that can form local back surface field.In addition,, make substrate 11 and said electric conducting material 13 when sintering, can merge each other because present embodiment is formed on passivation layer 12 with the mode of local wire mark with said electric conducting material 13; And after curing, can avoid forming the cavity between substrate 11 and said electric conducting material 13, and then promote the conductance of backplate.Wherein, form alusil alloy in the junction of substrate 11 and said electric conducting material 13, significantly to improve conductivity.
Please with reference to shown in Figure 3, it is the sketch map of a kind of solar cell of the utility model.What must specify is, the proportionate relationship of each structure among Fig. 3 shows for ease and explains, thus possibly not be inconsistent in the ratio of practical structures, at this for reference only but not be restricted.Solar cell 2 comprises a substrate 21, at least one semiconductor layer 22, two passivation layers 23,24 and a plurality of electric conducting materials 25,26.
Substrate 21 is a silicon substrate, and its silicon substrate is divided into monocrystalline silicon substrate, polycrystalline silicon substrate, amorphous silicon substrate or microcrystal silicon substrate again.Substrate 21 is N type semiconductor substrate or P type semiconductor substrate, and substrate 21 in the present embodiment is an example with the P type semiconductor substrate.Substrate 21 has a first surface 211 and a second surface 212, and first surface 211 can be light incident surface, and second surface 212 is surface backlight.
Semiconductor layer 22 is arranged on the first surface 211 of substrate 21, and semiconductor layer 22 also has a first surface 221 and a second surface 222, and first surface 221 is a light incident surface, and the second surface 222 of semiconductor layer 22 is connected with the first surface 211 of substrate 21.Semiconductor layer 22 in the present embodiment is an example with a n type semiconductor layer, and in fact semiconductor layer 22 can be N type or P type semiconductor substrate according to substrate 21, and is p type semiconductor layer or n type semiconductor layer.When substrate 21 is the N type semiconductor substrate, then with on P type semiconductor diffuse to the N type semiconductor substrate, to form a p type semiconductor layer on the N type semiconductor substrate; When substrate 21 is the P type semiconductor substrate, then with on N type semiconductor diffuse to the P type semiconductor substrate, to form a n type semiconductor layer on the P type semiconductor substrate.When P type and n type semiconductor layer contacted with each other, the electronics in the n type semiconductor layer can pour in the p type semiconductor layer, to fill up the electric hole in it.Near P-N connects face, because of the combination again in electronics-electric hole forms a carrier exhaustion region, and in P type and the n type semiconductor layer also because of having negative, positive electric charge respectively, therefore form an internal electric field.When solar irradiation was mapped to the P-N structure, to produce electronics-electric hole right because of absorbing sunlight for P type and n type semiconductor layer.By the internal electric field that exhaustion region provided, can let the semiconductor layer 22 interior electronics that produce in battery, flow.
The first surface 221 of semiconductor layer 22 carries out structuring to be handled.With the monocrystalline silicon substrate is that example is with KOH solution isotropic etching (anisotropic etching); And the first surface 221 of alligatoring semiconductor layer 22; Uneven in the residual size of first surface 221 like the structure as the pyramid; Make its incident light will pass through first surface 221 reflection for the second time of semiconductor layer 22 at least, therefore reduce the probability that the incident light first reflection just turns back.
Two passivation layers 23,24 are separately positioned on the first surface 221 of semiconductor layer 22 and the second surface 212 of substrate 21.Because the refraction coefficient difference of air and silicon is very big; Have obvious light reflection situation during the interface of light through air and silicon; Therefore the passivation layer 23,24 with silicon nitride (SiN) material is coated on substrate 21 and semiconductor layer 22; With the minimizing reflection of incident light, and can reduce complex centre (recombination center), and then promote photoelectric conversion efficiency.Since the first surface 221 of semiconductor layer 22 because of structuring handle form as pyramid as the structure of shape, in order to do making structure that passivation layer 23 also forms shape as the pyramid at semiconductor layer 22, the probability of just turning back with reduction incident light first reflection.
The passivation layer 24 that is arranged on the second surface 212 of substrate 21 has a plurality of perforates 241.Present embodiment is provided with said perforate 241 with the mode of laser (1aser) or etching (etching) on passivation layer 24.Wherein, the jelly that contains phosphoric acid, hydrofluoric acid or nitric acid is used in etching usually, utilizes the mode partially perforation of wire mark.The aspect of said perforate 241 can be such as but not limited to linear, dotted line shape, oblique line striated, round point shape or poroid etc.Said perforate 241 can be the equi-spaced apart setting, also can be not equi-spaced apart setting.What need explanation is, be arranged on collinear said perforate 241 can be continuous or discontinuous, that is; Said perforate 241 can segment identifier at a distance from and linear array be arranged on passivation layer 24; Or be arranged on passivation layer 24 with continuous lines strip or strip, wherein, the separated spacing of segment identifier can be different because of design or demand; And be designed to different length or shape, also can the passivation layer 24 of different aspects or shape be arranged on same row or be connected.In the present embodiment, said perforate 241 is with the equi-spaced apart setting, and said perforate 241 is a strip.Wherein, said perforate 241 all penetrates passivation layer 24 and links to each other with substrate 21.In addition, the said perforate 241 of present embodiment has one first width d3, and the scope of the first width d3 is that 50 μ m are less than 300 μ m.
At the first surface 221 of semiconductor layer 22 and the second surface 212 of substrate 21 a plurality of electric conducting materials 25,26 are set respectively.Wherein, present embodiment is arranged on the material elargol for example of said electric conducting material 25 of the first surface 221 of semiconductor layer 22; And be arranged on the material aluminium glue for example of said electric conducting material 26 of the second surface 212 of substrate 21, also can be tin indium oxide, nickel, copper, titanium, aluminium or tin.It should be noted that; The said perforate 241 of the said electric conducting material 26 corresponding passivation layers 24 of present embodiment is provided with; The aspect of electric conducting material 26 can be for example but is not limit at linear, dotted line shape, oblique line striated, round point shape or poroid etc., because the said perforate of present embodiment 241 is an example with the strip, therefore said electric conducting material 26 also is formed on passivation layer 24 with the aspect of strip; And for being arranged on passivation layer 24 at interval, to form local wire mark.It should be noted that be arranged on collinear a plurality of electric conducting material 26 can be continuous or discontinuous, that is; Said electric conducting material 26 can segment identifier at a distance from and linear array be arranged on passivation layer 24; Or be arranged on passivation layer 24 with the continuous lines strip, wherein, the separated spacing of segment identifier can be different because of design or demand; And be designed to different length or aspect, also can the electric conducting material 26 of different aspects be arranged on same row or be connected.In addition, the said electric conducting material 26 of present embodiment has one second a width d4 and a height h1, and wherein, the second width d4 is more than or equal to the first width d3, and the scope of the second width d4 is less than 500 μ m greater than 50 μ m.And the scope of height h1 is less than 40 μ m greater than 5 μ m.
Be arranged on said electric conducting material 25,26 and the substrate 21 and the semiconductor layer 22 disconnected settings of passivation layer 23,24; For said electric conducting material 25,26 can be electrically connected with substrate 21 and semiconductor layer 22; Therefore; A plurality of electric conducting materials 25,26 are set to be located at passivation layer 23, after 24, substrate 21, semiconductor layer 22 and electric conducting material 25,26 to be carried out sintering.Utilize co-sintered (co-firing) processing procedure to be able to make front electrode and backplate, in order to do making electric conducting material 25,26 and substrate 21 and semiconductor layer 22 electrically connect.When substrate 21 and semiconductor layer 22 changed the light that absorbs into electronics, substrate 21 and semiconductor layer 22 were collected to electric conducting material 25,26 with the electronics that is produced.At last, through the binding of electric conducting material 25,26 and external loading, will pass through electron transport that light, electric conversion reaction produced to extraneous.
Then, solidify substrate 21, semiconductor layer 22 and said electric conducting material 25,26.Substrate 21, semiconductor layer 22 and electric conducting material 25,26 are lowered the temperature or cooled off, up to the temperature of reducing to room temperature, to solidify substrate 21, semiconductor layer 22 and electric conducting material 25,26.
In sum; Solar cell of the utility model and backplate structure thereof, the passivation layer through having perforate and the setting of electric conducting material make the electric conducting material that is arranged on surface backlight behind high temperature sintering; Can be connected with substrate, to reach the purpose that forms back surface field.It should be noted that; The passivation layer that is arranged on surface backlight forms a plurality of perforates through laser or etched mode, and the mode that continues with local wire mark is arranged on said passivation layer with electric conducting material, makes substrate and electric conducting material when sintering; Can merge each other, reach preferable electric connection; And after substrate and electric conducting material curing, can avoid between substrate and electric conducting material, forming the cavity, and then promote the conductance of backplate.
Compare with known technology; Solar cell of the utility model and backplate structure thereof; Not only can reduce the setting of electric conducting material, reduce cost, avoid between substrate and electric conducting material, forming the cavity; Improve the conductance of backplate, and then promote the photoelectric conversion efficiency and the performance of whole solar cell.
The above only is an illustrative, and non-limiting.Any spirit and category that does not break away from the utility model, and to its equivalent modifications of carrying out or change, all should be included in the claim institute restricted portion.
Claims (10)
1. a rear surface of solar cell electrode structure is characterized in that, comprising:
One substrate;
One passivation layer is arranged on said substrate, and said passivation layer has a plurality of perforates; And
A plurality of electric conducting materials are arranged on said passivation layer at interval, and corresponding said perforate setting, and said electric conducting material connects said substrate through said perforate.
2. rear surface of solar cell electrode structure according to claim 1 is characterized in that, said substrate is N type semiconductor substrate or P type semiconductor substrate.
3. rear surface of solar cell electrode structure according to claim 1 is characterized in that, the said perforate of said passivation layer has one first width, said first width greater than 50 μ m less than 300 μ m.
4. rear surface of solar cell electrode structure according to claim 3 is characterized in that, said electric conducting material has one second width, and less than 500 μ m, said second width is more than or equal to said first width greater than 50 μ m for said second width.
5. rear surface of solar cell electrode structure according to claim 1 is characterized in that, said electric conducting material have one the height, said height greater than 5 μ m less than 40 μ m.
6. a solar cell is characterized in that, comprising:
One substrate has a first surface and a second surface;
Two passivation layers are separately positioned on the said first surface and the said second surface of said substrate, and one of them said passivation layer has a plurality of perforates; And
A plurality of electric conducting materials are arranged on the said passivation layer with said perforate at interval, and said electric conducting material connects said substrate through said perforate.
7. solar cell according to claim 6 is characterized in that, said substrate is N type semiconductor substrate or P type semiconductor substrate.
8. solar cell according to claim 6 is characterized in that, the said perforate of said passivation layer has one first width, said first width greater than 50 μ m less than 300 μ m.
9. solar cell according to claim 8 is characterized in that, said electric conducting material has one second width, and less than 500 μ m, said second width is more than or equal to said first width greater than 50 μ m for said second width.
10. solar cell according to claim 6 is characterized in that, said electric conducting material have one the height, said height greater than 5 μ m less than 40 μ m.
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CN 201120364427 CN202275838U (en) | 2011-09-27 | 2011-09-27 | Solar cell and back electrode structure thereof |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103985769A (en) * | 2013-02-07 | 2014-08-13 | 茂迪股份有限公司 | solar cell and module thereof |
CN111129176A (en) * | 2019-12-20 | 2020-05-08 | 浙江爱旭太阳能科技有限公司 | Method for producing a solar cell and solar cell |
-
2011
- 2011-09-27 CN CN 201120364427 patent/CN202275838U/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103985769A (en) * | 2013-02-07 | 2014-08-13 | 茂迪股份有限公司 | solar cell and module thereof |
CN103985769B (en) * | 2013-02-07 | 2017-03-01 | 茂迪股份有限公司 | Solar cell and module thereof |
CN111129176A (en) * | 2019-12-20 | 2020-05-08 | 浙江爱旭太阳能科技有限公司 | Method for producing a solar cell and solar cell |
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Address after: No. 7, No. 3 Road, Xinzhu City, Hsinchu Science Industrial Park, Taiwan, China Patentee after: United Renewable Energy Co., Ltd. Address before: No. 7, No. 3 Road, Xinzhu City, Hsinchu Science Industrial Park, Taiwan, China Patentee before: Neo Solar Power Corporation |
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Granted publication date: 20120613 |