CN202268899U - 32e1 electric port collecting card - Google Patents
32e1 electric port collecting card Download PDFInfo
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- CN202268899U CN202268899U CN2011203536883U CN201120353688U CN202268899U CN 202268899 U CN202268899 U CN 202268899U CN 2011203536883 U CN2011203536883 U CN 2011203536883U CN 201120353688 U CN201120353688 U CN 201120353688U CN 202268899 U CN202268899 U CN 202268899U
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Abstract
The utility model provides a 32E1 electric port collecting card including a 4E1 interface chip, a time slot exchange chip, an FPGA (Field Programmable Gate Array), a digital signal processing chip and an embedded processor. An input terminal of the 4E1 interface chip connects with an E1 line in a high-resistance multiple-connection manner. The 4E1 interface chip connects with the time slot exchange chip. An address bus, a data bus, and a control bus together of the 4E1 interface chip connect with address buses, data buses and control buses together of the time slot exchange chip, the FPGA, the DSP (Digital Signal Processor) and the embedded processor. The time slot exchange chip connects with the FPGA. The FPGA connects with the DSP. The DSP connects with an expanding SDRAM. The DSP connects with the embedded processor. The embedded processor connects with the computer through a network interface. A debugging signal of the embedded processor connects with a serial port interface circuit of the computer through a serial port interface. The 32E1 electric port collecting card in the utility model has an advantage of large capacity and can realize functions of voice monitoring and signal preprocessing of a 32E1 one-way line.
Description
Technical field
The utility model relates to a kind of 32E1 electricity mouthful capture card.
Background technology
Along with the continuous development of the communication technology, communication network is complicated day by day.Signaling is the nerve of communication network, supports and control the normal operation of communication network.Signaling System Number 7 is present domestic topmost interoffice signaling, on fixed network, mobile network, has all obtained extensive employing.No.7 signalling system is to adopt maximum common channel signal technology in the digital communication network; Along with popularizing of Signaling System Number 7; The traffic carrying capacity of Signaling System Number 7 constantly increases; Particularly online at mobile signaling protocol, original 64kbps signaling link can not adapt to the demand that traffic carrying capacity increases fully, and the application quantity of ISDN PRI trunk interface and digital junction A interface increases greatly.
The utility model content
Existing signaling acquisition system capacity is little in order to overcome, the deficiency of autgmentability difference, and the utility model provides a kind of power system capacity big, the 32E1 electricity mouthful capture card of favorable expandability.
32E1 electricity mouthful capture card comprises 4E1 interface chip, time gas exchange chip, field programmable gate array (FPGA), digital signal processing chip (DSP) and flush bonding processor;
The input of described 4E1 interface chip is connected with the E1 line through the high resistant multiple connection; The 8Mbps code stream I/O end of described 4E1 interface chip is connected with the I/O end of described time gas exchange chip; The address bus of described 4E1 interface chip, data/address bus and control bus link to each other with address bus, data/address bus and the control bus of described time gas exchange chip, FPGA, DSP and flush bonding processor respectively; The code stream output of described time gas exchange chip is connected with the serial code stream input of described FPGA; The synchronous signal output end EDMA of described FPGA is connected with the parallel data input EMIFA of described DSP; The I/O end EMIFB of described DSP is connected with the I/O end that extends out SDRAM; The output code flow MCBSP mouth of described DSP is connected with described FPGA, and the PCI/HPI multiplexing port of described DSP is connected with the local bus port of described flush bonding processor; Described flush bonding processor is connected with computer through network interface, and the debug signal of described flush bonding processor is connected with described computer by serial interface circuit through the serial interface circuit.
Further, be provided with E1 system clock synchronizer in the described capture card, the synchronizing clock signals that described clock synchronizer produces is imported described 4E1 interface chip, time gas exchange chip, FPGA and DSP respectively.
Further, described flush bonding processor is connected with the gigabit network interface of described computer through the gigabit networking interface circuit.
Perhaps, described flush bonding processor is connected with the 100-M network Ethernet of described computer through 100,000,000 network interface circuits.
In the utility model; The 4E1 interface chip links to each other with time gas exchange chip, FPGA, DSP and flush bonding processor respectively; Can not only support maximum 1024 unidirectional 64kbps signaling links, can also support 32 unidirectional high speed 2Mbps signaling links, the 64E1 signal that receives carried out self adaptation amplify; Can sort by time of reception to all channel datas, and Message Signal Unit is sent through Ethernet; This capture card is also supported voice collecting, the stack of 2048 passages simultaneously, and sends through Ethernet.
The capacity that the utlity model has is big, can realize the audio monitoring and the signaling preprocessing function of 32E1 one-way line, can be through the advantage of kilomega network effected real-time communication.
Description of drawings
Fig. 1 is the master-plan block diagram of the utility model.
Fig. 2 is the circuit block diagram of the utility model.
Embodiment
Embodiment one
With reference to Fig. 1,2
32E1 electricity mouthful capture card comprises 4E1 interface chip, time gas exchange chip, field programmable gate array (FPGA), digital signal processing chip (DSP) and flush bonding processor;
The input of described 4E1 interface chip is connected with the E1 line through the high resistant multiple connection; The 8Mbps code stream I/O end of described 4E1 interface chip is connected with the I/O end of described time gas exchange chip; The address bus of described 4E1 interface chip, data/address bus and control bus link to each other with address bus, data/address bus and the control bus of described time gas exchange chip, FPGA, DSP and flush bonding processor respectively; The code stream output of described time gas exchange chip is connected with the serial code stream input of described FPGA; The synchronous signal output end EDMA of described FPGA is connected with the parallel data input EMIFA of described DSP; The I/O end EMIFB of described DSP is connected with the I/O end that extends out SDRAM; The output code flow MCBSP mouth of described DSP is connected with described FPGA, and the PCI/HPI multiplexing port of described DSP is connected with the local bus port of described flush bonding processor; Described flush bonding processor is connected with computer through network interface, and the debug signal of described flush bonding processor is connected with described computer by serial interface circuit through the serial interface circuit.
Be provided with E1 system clock synchronizer in the described capture card, the synchronizing clock signals that described clock synchronizer produces is imported described 4E1 interface chip, time gas exchange chip, FPGA and DSP respectively.
Described flush bonding processor is connected with the gigabit network interface of described computer through the gigabit networking interface circuit.
In the utility model; The 4E1 interface chip links to each other with time gas exchange chip, FPGA, DSP and flush bonding processor respectively; Can not only support maximum 1024 unidirectional 64kbps signaling links, can also support 32 unidirectional high speed 2Mbps signaling links, the 64E1 signal that receives carried out self adaptation amplify; Can sort by time of reception to all channel datas, and Message Signal Unit is sent through Ethernet; This capture card is also supported voice collecting, the stack of 2048 passages simultaneously, and sends through Ethernet.
It is big that present embodiment has a capacity, can realize the audio monitoring and the signaling preprocessing function of 32E1 one-way line, can be through the advantage of kilomega network effected real-time communication.
Embodiment two
Present embodiment is with the difference of embodiment one: described flush bonding processor is connected with the 100-M network Ethernet of described computer through 100,000,000 network interface circuits.All the other structures are all identical.
It is big that present embodiment has a capacity, can realize the audio monitoring and the signaling preprocessing function of 32E1 one-way line, can realize the advantage of real-time communication through 100-M network Ethernet.
The described content of this specification embodiment only is enumerating the way of realization of utility model design; The protection range of the utility model should not be regarded as and only limit to the concrete form that embodiment states, the protection range of the utility model also reach in those skilled in the art according to the utility model design the equivalent technologies means that can expect.
Claims (4)
1.32E1 electricity mouthful capture card is characterized in that: comprise 4E1 interface chip, time gas exchange chip, field programmable gate array (FPGA), digital signal processing chip (DSP) and flush bonding processor;
The input of described 4E1 interface chip is connected with the E1 line through the high resistant multiple connection; The 8Mbps code stream I/O end of described 4E1 interface chip is connected with the I/O end of described time gas exchange chip; The address bus of described 4E1 interface chip, data/address bus and control bus link to each other with address bus, data/address bus and the control bus of described time gas exchange chip, FPGA, DSP and flush bonding processor respectively; The code stream output of described time gas exchange chip is connected with the serial code stream input of described FPGA; The synchronous signal output end EDMA of described FPGA is connected with the parallel data input EMIFA of described DSP; The I/O end EMIFB of described DSP is connected with the I/O end that extends out SDRAM; The output code flow MCBSP mouth of described DSP is connected with described FPGA, and the PCI/HPI multiplexing port of described DSP is connected with the local bus port of described flush bonding processor; Described flush bonding processor is connected with computer through network interface, and the debug signal of described flush bonding processor is connected with described computer by serial interface circuit through the serial interface circuit.
2. 32E1 electricity mouthful capture card as claimed in claim 1; It is characterized in that: be provided with E1 system clock synchronizer in the described capture card, the synchronizing clock signals that described clock synchronizer produces is imported described 4E1 interface chip, time gas exchange chip, FPGA and DSP respectively.
3. according to claim 1 or claim 2 32E1 electricity mouthful capture card, it is characterized in that: described flush bonding processor is connected with the gigabit network interface of described computer through the gigabit networking interface circuit.
4. according to claim 1 or claim 2 32E1 electricity mouthful capture card, it is characterized in that: described flush bonding processor is connected with the 100-M network Ethernet of described computer through 100,000,000 network interface circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203536883U CN202268899U (en) | 2011-09-20 | 2011-09-20 | 32e1 electric port collecting card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203536883U CN202268899U (en) | 2011-09-20 | 2011-09-20 | 32e1 electric port collecting card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202268899U true CN202268899U (en) | 2012-06-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203536883U Expired - Fee Related CN202268899U (en) | 2011-09-20 | 2011-09-20 | 32e1 electric port collecting card |
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| Country | Link |
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| CN (1) | CN202268899U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104020691A (en) * | 2014-06-11 | 2014-09-03 | 哈尔滨工业大学 | Signal acquisition board suitable for multiple bus protocols and multiple expansion interfaces |
| CN107750431A (en) * | 2015-06-16 | 2018-03-02 | 阿海珐核能公司 | Field programmable gate array including multiple functional blocks and the control device for power set |
-
2011
- 2011-09-20 CN CN2011203536883U patent/CN202268899U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104020691A (en) * | 2014-06-11 | 2014-09-03 | 哈尔滨工业大学 | Signal acquisition board suitable for multiple bus protocols and multiple expansion interfaces |
| CN107750431A (en) * | 2015-06-16 | 2018-03-02 | 阿海珐核能公司 | Field programmable gate array including multiple functional blocks and the control device for power set |
| CN107750431B (en) * | 2015-06-16 | 2021-12-10 | 阿海珐核能公司 | Field programmable gate array comprising a plurality of functional blocks and control device for a power plant |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120606 Termination date: 20180920 |
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| CF01 | Termination of patent right due to non-payment of annual fee |