CN202210280U - Serial data transmission system - Google Patents
Serial data transmission system Download PDFInfo
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- CN202210280U CN202210280U CN2011203567858U CN201120356785U CN202210280U CN 202210280 U CN202210280 U CN 202210280U CN 2011203567858 U CN2011203567858 U CN 2011203567858U CN 201120356785 U CN201120356785 U CN 201120356785U CN 202210280 U CN202210280 U CN 202210280U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The utility model discloses a serial data transmission system. The serial data transmission system comprises a sending end for sending data, a receiving end for receiving the data sent by the sending end, a first connecting capacitor which is connected between the sending end and the receiving end, and a second connecting capacitor which is connected between the sending end and the receiving end, wherein the sending end comprises a sending end driving unit and an amplitude detection unit which is connected with the sending end driving unit; the sending end driving unit outputs a pair of differential signals according to a received data signal; and the amplitude detection unit detects the amplitude change of the differential signals output by the sending end driving unit and outputs an indication signal which indicates whether the sending end is connected with the receiving end normally. The serial data transmission system is simple in structure, high in anti-jamming capability and low in power consumption.
Description
Technical field
The utility model relates to a kind of data transmission system, refers to a kind of serial data transmission system with amplitude detection unit especially.
Background technology
In serial data transmission system; In the time will carrying out high speed data transfer; Whether the receiving end that the transmitting terminal of one electronic equipment need detect the other side is connected normally with the transmitting terminal of this electronic equipment, has only transmitting terminal when electronic equipment to detect to be connected with the other side's receiving end just can begin to carry out high speed data transfer after normal.
Therefore requiring the transmitting terminal of electronic equipment will have one can detect receiving end and whether connect normal testing circuit.Because peripheral circuit variation is bigger in serial data transmission system; Especially the existence of parasitic circuit etc. on AC coupling device, the plate in the plate path, and the existence of factor such as the uncertain impedance design of receiving end are when the design testing circuit; Just require system that high antijamming capability is arranged; Judge scope accurately, and as far as possible little on power consumption, use with the low-power consumption of satisfying development in the future.
Summary of the invention
In view of above content, be necessary to provide a kind of simple in structure, serial data transmission system that antijamming capability is strong and low in energy consumption with amplitude detection unit.
A kind of serial data transmission system; Comprise one be used to send data transmitting terminal, be used to receive receiving end, that said transmitting terminal sends data and be connected in first between said transmitting terminal and the said receiving end and be connected electric capacity and one and be connected in second between said transmitting terminal and the said receiving end and be connected electric capacity; Said transmitting terminal comprises the amplitude detection unit that a transmitting terminal driver element and links to each other with said transmitting terminal driver element; Said transmitting terminal driver element is exported a pair of differential signal according to the data-signal that receives; Said amplitude detection unit detects the changes in amplitude of said transmitting terminal driver element output differential signal, and exports one and indicate said transmitting terminal whether to be connected normal indicator signal with said receiving end.
Preferably; Said amplitude detection unit comprises the comparer that reference voltage end, that an amplitude detection circuit, a generating circuit from reference voltage, link to each other with said generating circuit from reference voltage links to each other with said amplitude detection circuit and said reference voltage end; Said amplitude detection circuit detects the changes in amplitude of said transmitting terminal driving circuit output differential signal; And export the magnitude of voltage that is directly proportional with the differential signal changes in amplitude to said comparer; The size of the magnitude of voltage of the more said amplitude detection circuit output of said comparer and the magnitude of voltage of said reference voltage end; And export and indicate said transmitting terminal whether to be connected normal indicator signal with said receiving end, said receiving end comprises one first resistance and one second resistance that is connected in parallel.
Preferably; Said transmitting terminal driver element comprises the 4th resistance that the 3rd resistance and one that second FET, that first FET, that one first current source, links to each other with said first current source links to each other with said first current source links to each other with said first FET links to each other with said second FET; Said amplitude detection circuit comprises the 4th electric capacity that the 3rd electric capacity and one that the tenth resistance, one that the 9th resistance, one that the 8th resistance, one that the 7th resistance, one that the 6th resistance, one that the 4th FET that the 3rd FET, that one the 4th current source, one the 5th current source, link to each other with said first FET and said the 3rd resistance links to each other with said second FET and said the 4th resistance, the 5th resistance, one that one the 8th FET, links to each other with said the 4th current source link to each other with said the 5th current source links to each other with said the 4th FET links to each other with said the 3rd FET links to each other with said the 3rd FET links to each other with said the 4th FET links to each other with said the 5th resistance links to each other with said the 6th resistance, and said generating circuit from reference voltage comprises the 6th electric capacity that the 5th electric capacity and one that the 16 resistance, one that the 15 resistance, one that the 14 resistance, one that the 13 resistance, one that the 12 resistance, one that the 11 resistance, one that the 7th FET, that the 6th FET, that one second current source, one the 3rd current source, one the 5th FET, link to each other with said the 5th FET links to each other with said the 5th FET and said the 6th FET links to each other with said the 5th FET links to each other with said the 6th FET links to each other with said second current source links to each other with said the 3rd current source is Xiang Lianed with said the 13 resistance links to each other with said the 14 resistance links to each other with said the 15 resistance links to each other with said the 16 resistance.
Preferably; The common power end that connects of one end of one end of said first current source, an end of said second current source, an end of said the 3rd current source, an end of said the 4th current source, an end of said the 5th current source, an end of said the 7th resistance, an end of said the 8th resistance, said the 11 resistance and an end of said the 12 resistance; The source class of said first FET and the common other end that is connected said first current source of the source class of said second FET; The common differential data that receives a pair of input of the grid of the grid of said first FET and said second FET; The drain electrode of said first FET is connected the grid of an end of electric capacity, said the 3rd FET with an end, said first of said the 3rd resistance and an end of said the 9th resistance links to each other; The drain electrode of said second FET is connected the grid of an end of electric capacity, said the 4th FET with an end, said second of said the 4th resistance and an end of said the tenth resistance links to each other, and a pair of differential signal of the common output of the drain electrode of the drain electrode of said first FET and said second FET is to the grid of said the 3rd FET and the grid of said the 4th FET.
Preferably; The other end of the said first connection electric capacity links to each other with an end of said second resistance; The other end of the said second connection electric capacity links to each other with an end of said first resistance; The drain electrode of said the 3rd FET links to each other with the other end of said the 8th resistance; The drain electrode of said the 4th FET links to each other with the other end of said the 7th resistance; The common detection voltage end that connects of one end of one end of the drain electrode of the source class of the source class of said the 3rd FET, said the 4th FET, said the 8th FET, said the 5th resistance, an end of said the 6th resistance, said the 3rd electric capacity and an end of said the 4th electric capacity, the other end of said the 5th resistance links to each other with the other end of said the 4th current source, and the other end of said the 6th resistance links to each other with the other end of said the 5th current source.
Preferably; The other end of said the 9th resistance is connected the grid of said the 5th FET and the grid of said the 6th FET jointly with the other end of said the tenth resistance; And export a common mode signal to the grid of said the 5th FET and the grid of said the 6th FET; The drain electrode of said the 5th FET links to each other with the other end of said the 11 resistance; The drain electrode of said the 6th FET links to each other with the other end of said the 12 resistance, and the source class of the source class of said the 5th FET, said the 6th FET, the drain electrode of said the 7th FET, an end of said the 15 resistance, an end of said the 16 resistance, an end of said the 5th electric capacity and an end of said the 6th electric capacity connect jointly.
Preferably; The grid of said the 7th FET links to each other with the grid of said the 8th FET; And connect a voltage end jointly, and an end of said the 13 resistance links to each other with the other end of said second current source, and an end of said the 14 resistance links to each other with the other end of said the 3rd current source; The other end of said the 13 resistance is connected said reference voltage end jointly with the other end of said the 15 resistance, and the other end of said the 14 resistance links to each other with the other end of said the 16 resistance.
Preferably; The common earth terminal that connects of the source class of the source class of the other end of the other end of the other end of the other end of the other end of the other end of the other end of the other end of said first resistance, said second resistance, said the 3rd resistance, said the 4th resistance, said the 3rd electric capacity, said the 4th electric capacity, said the 5th electric capacity, said the 6th electric capacity, said the 7th FET and said the 8th FET; One normal phase input end of said comparer links to each other with said detection voltage end; One inverting input links to each other with said reference voltage end, and whether the said transmitting terminal of output terminal output indication is connected normal indicator signal with said receiving end.
Relative prior art; The utility model serial data transmission system detects the transmitting terminal transmission changes in amplitude that data produced through amplitude detection unit; Produce the detection magnitude of voltage that is directly proportional with the transmission changes in amplitude that data produced; And detect transmitting terminal and whether be connected normally with receiving end through comparing with reference voltage level, simple in structure, antijamming capability is strong and low in energy consumption.
Description of drawings
Fig. 1 is the system architecture diagram of the utility model serial data transmission system preferred embodiments.
Fig. 2 is the system chart of amplitude detection unit in the utility model serial data transmission system preferred embodiments.
Fig. 3 is the physical circuit figure of the utility model serial data transmission system preferred embodiments.
Embodiment
See also Fig. 1 and Fig. 3, the utility model serial data transmission system preferred embodiments comprises that a transmitting terminal, a receiving end, are connected in first between this transmitting terminal and this receiving end and are connected capacitor C 1 and and are connected in second between this transmitting terminal and this receiving end and are connected capacitor C 2.This transmitting terminal comprises the amplitude detection unit that a transmitting terminal driver element and links to each other with this transmitting terminal driver element, and this receiving end comprises one first resistance R 1 and one second resistance R 2 that is connected in parallel.
This transmitting terminal driver element is exported a pair of differential signal tx_on, tx_op according to the data-signal that receives; This amplitude detection unit detects the changes in amplitude of this transmitting terminal driver element output signal tx_on, tx_op; And export one and be used to indicate this transmitting terminal whether to be connected normal indicator signal with this receiving end; This first connects capacitor C 1 and second is connected capacitor C 2 and is ac coupling capacitor with this, is used for the isolated DC signal, only allows AC signal to pass through.This first resistance R 1 is the loaded impedance of this receiving end with this second resistance R 2, this first resistance R 1 and these second resistance R, 2 common grounds.
See also Fig. 2, Fig. 2 is the system chart of amplitude detection unit in the utility model serial data transmission system preferred embodiments.Please consult Fig. 3 simultaneously, this amplitude detection unit comprises the comparator C OMP that reference voltage end Vref, that an amplitude detection circuit, a generating circuit from reference voltage, link to each other with this generating circuit from reference voltage links to each other with this amplitude detection circuit and this reference voltage end Vref.This amplitude detection circuit is used to detect the changes in amplitude of this transmitting terminal driving circuit output differential signal; And export the magnitude of voltage that is directly proportional with the changes in amplitude of differential signal to this comparator C OMP; The reference voltage that this generating circuit from reference voltage is used to produce needs is to this reference voltage end Vref; This comparator C OMP is used for relatively the size of magnitude of voltage with the magnitude of voltage of this reference voltage end Vref of this amplitude detection circuit output, and exports and be used to indicate this transmitting terminal whether to be connected normal indicator signal with this receiving end.
See also Fig. 3, Fig. 3 is the physical circuit figure of the utility model serial data transmission system preferred embodiments.Wherein, this transmitting terminal driver element comprises the 4th resistance R 4 that the 3rd resistance R 3 and that the second FET M2, that the first FET M1, that one first current source I1, links to each other with this first current source I1 links to each other with this first current source I1 links to each other with this first FET M1 links to each other with this second FET M2.This amplitude detection circuit comprises one the 4th current source I4, one the 5th current source I5, one the 3rd FET M3, one the 4th FET M4, one the 8th FET M8, one the 5th resistance R 5, one the 6th resistance R 6, one the 7th resistance R 7, one the 8th resistance R 8, one the 9th resistance R 9,1 the tenth resistance R 10, one the 3rd capacitor C 3 and one the 4th capacitor C 4.This generating circuit from reference voltage comprises one second current source I2, one the 3rd current source I3, one the 5th FET M5, one the 6th FET M6, one the 7th FET M7,1 the 11 resistance R 11,1 the 12 resistance R 12,1 the 13 resistance R 13,1 the 14 resistance R 14,1 the 15 resistance R 15,1 the 16 resistance R 16, one the 5th capacitor C 5 and one the 6th capacitor C 6.
The physical circuit annexation of the utility model serial data transmission system preferred embodiments is following: the common power end VDD that connects of an end of an end of the end of the end of the end of this first current source I1, this second current source I2, the end of the 3rd current source I3, the 4th current source I4, the end of the 5th current source I5, the 7th resistance R 7, an end of the 8th resistance R 8, the 11 resistance R 11 and an end of the 12 resistance R 12.The source class of this first FET M1 and the source class of this second FET M2 are connected the other end of this first current source I1 jointly; Common differential data DATA_P, the DATA_N that receives a pair of input of the grid of the grid of this first FET M1 and this second FET M2; The drain electrode of this first FET M1 and an end of the 3rd resistance R 3, this first is connected an end of capacitor C 1, the grid of the 3rd FET M3 and an end of the 9th resistance R 9 and links to each other; The drain electrode of this second FET M2 and an end of the 4th resistance R 4, this second is connected an end of capacitor C 2, the grid of the 4th FET M4 and an end of the tenth resistance R 10 and links to each other, and the drain electrode of the drain electrode of this first FET M1 and this second FET M2 is exported a pair of differential signal Tx_on, Tx_op jointly to the grid of the 3rd FET M3 and the grid of the 4th FET M4.The other end of this first connection capacitor C 1 links to each other with an end of this second resistance R 2, and the other end of this second connection capacitor C 2 links to each other with an end of this first resistance R 1.The drain electrode of the 3rd FET M3 links to each other with the other end of the 8th resistance R 8; The drain electrode of the 4th FET M4 links to each other with the other end of the 7th resistance R 7, the common detection voltage end Vdct that connects of an end of an end of the source class of the source class of the 3rd FET M3, the 4th FET M4, the drain electrode of the 8th FET M8, the 5th resistance R 5, an end of the 6th resistance R 6, the 3rd capacitor C 3 and an end of the 4th capacitor C 4.The other end of the 5th resistance R 5 links to each other with the other end of the 4th current source I4, and the other end of the 6th resistance R 6 links to each other with the other end of the 5th current source I5.The other end of the 9th resistance R 9 is connected the grid of the 5th FET M5 and the grid of the 6th FET M6 jointly with the other end of the tenth resistance R 10, and exports a common mode signal Tx_com to the grid of the 5th FET M5 and the grid of the 6th FET M6.The drain electrode of the 5th FET M5 links to each other with the other end of the 11 resistance R 11, and the drain electrode of the 6th FET M6 links to each other with the other end of the 12 resistance R 12.One end of one end of the drain electrode of the source class of the source class of the 5th FET M5, the 6th FET M6, the 7th FET M7, the 15 resistance R 15, an end of the 16 resistance R 16, the 5th capacitor C 5 and an end of the 6th capacitor C 6 connect jointly.The grid of the 7th FET M7 links to each other with the grid of the 8th FET M8, and connects a voltage end Vb jointly.One end of the 13 resistance R 13 links to each other with the other end of this second current source I2; One end of the 14 resistance R 14 links to each other with the other end of the 3rd current source I3; The other end of the 13 resistance R 13 is connected reference voltage end Vref jointly with the other end of the 15 resistance R 15, and the other end of the 14 resistance R 14 links to each other with the other end of the 16 resistance R 16.The common earth terminal GND that connects of the source class of the source class of the other end of the other end of the other end of the other end of the other end of the other end of the other end of the other end of this first resistance R 1, this second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5, the 6th capacitor C 6, the 7th FET M7 and the 8th FET M8.The normal phase input end of this comparator C OMP links to each other with this detection voltage end Vdct; One inverting input links to each other with this reference voltage end Vref; Whether this transmitting terminal of one output terminal OUT output indication is connected normal indicator signal with this receiving end; The voltage end of this comparator C OMP connects this power end VDD, and another voltage end of this comparator C OMP connects this earth terminal GND.
The principle of work of the utility model serial data transmission system preferred embodiments is following:
See also Fig. 3; Differential data DATA_P, DATA_N are for needing the serial data of transmitting terminal transmission in this serial data transmission system; When opening this amplitude detection unit, differential data DATA_P, DATA_N are the data to be tested of certain frequency, and its frequency can be regulated according to design demand.
The output amplitude of supposing differential signal Tx_on, Tx_op is respectively:
Its common mode voltage
is:
=
I1
R4; Wherein, Δ V is the magnitude of voltage that differential signal Tx_on, Tx_op depart from common mode, i.e. the amplitude of transmitting terminal output signal.
At this moment, the electric current sum that flows through the 3rd FET M3 and the 4th FET M4 is:
The magnitude of voltage Vdct that can be obtained detecting voltage end Vdct by this expression formula with the variation formula of Δ V is:
，
Promptly detect the magnitude of voltage Vdct of voltage end Vdct and the magnitude of voltage Δ V relation in direct ratio that differential signal Tx_on, Tx_op depart from common mode.
Wherein, K is a scale-up factor; It is worth K=
;
is the mobility of FET technology; Cox is the gate oxide thickness of FET technology;
is the breadth length ratio of the 3rd FET M3 and the 4th FET M4, and Vth is the threshold voltage of FET.
Can know that by above formula the magnitude of voltage Vdct that detects voltage end Vdct becomes big greatly with the magnitude of voltage Δ V change that differential signal Tx_on, Tx_op depart from common mode.
Suppose to be connected just often with receiving end when transmitting terminal detects transmitting terminal, the magnitude of voltage that differential signal Tx_on, Tx_op depart from common mode is Δ V1, and the magnitude of voltage that detects voltage end Vdct is Vdct1; When transmitting terminal detects transmitting terminal and receiving end malunion often, the magnitude of voltage that differential signal Tx_on, Tx_op depart from common mode is Δ V2, and the magnitude of voltage that detects voltage end Vdct is Vdct2, then:
, transmitting terminal is connected just often Δ V1=
I1
when detecting transmitting terminal with receiving end;
When transmitting terminal detects transmitting terminal and receiving end malunion often, Δ V2=
I1
R4;
Because Δ V1 < Δ V2, so Vdct1 < Vdct2.
In order to distinguish above two kinds of situation, make reference voltage level Vref that generating circuit from reference voltage produces between Δ V1 and Δ V2.
When detecting transmitting terminal, transmitting terminal is connected just often with receiving end, Vdct Vref, promptly the output terminal OUT of comparer is output as low level;
When transmitting terminal detects transmitting terminal and receiving end malunion often, Vdct>Vref, promptly the output terminal OUT of comparer is output as high level.
This shows that the level signal through comparator output terminal output can detect transmitting terminal and whether be connected normally with receiving end.
The utility model serial data transmission system detects the transmitting terminal transmission changes in amplitude that data produced through amplitude detection unit; It is the magnitude of voltage that differential signal Tx_on, Tx_op depart from common mode; Produce the detection magnitude of voltage that is directly proportional with the transmission changes in amplitude that data produced; And detect transmitting terminal and whether be connected normally with receiving end through comparing with reference voltage level, simple in structure, antijamming capability is strong and low in energy consumption.
Claims (8)
1. serial data transmission system; Comprise one be used to send data transmitting terminal, be used to receive receiving end, that said transmitting terminal sends data and be connected in first between said transmitting terminal and the said receiving end and be connected electric capacity and one and be connected in second between said transmitting terminal and the said receiving end and be connected electric capacity; It is characterized in that: said transmitting terminal comprises the amplitude detection unit that a transmitting terminal driver element and links to each other with said transmitting terminal driver element; Said transmitting terminal driver element is exported a pair of differential signal according to the data-signal that receives; Said amplitude detection unit detects the changes in amplitude of said transmitting terminal driver element output differential signal, and exports one and indicate said transmitting terminal whether to be connected normal indicator signal with said receiving end.
2. serial data transmission system as claimed in claim 1; It is characterized in that: said amplitude detection unit comprises the comparer that reference voltage end, that an amplitude detection circuit, a generating circuit from reference voltage, link to each other with said generating circuit from reference voltage links to each other with said amplitude detection circuit and said reference voltage end; Said amplitude detection circuit detects the changes in amplitude of said transmitting terminal driving circuit output differential signal; And export the magnitude of voltage that is directly proportional with the differential signal changes in amplitude to said comparer; The size of the magnitude of voltage of the more said amplitude detection circuit output of said comparer and the magnitude of voltage of said reference voltage end; And export and indicate said transmitting terminal whether to be connected normal indicator signal with said receiving end, said receiving end comprises one first resistance and one second resistance that is connected in parallel.
3. serial data transmission system as claimed in claim 2; It is characterized in that: said transmitting terminal driver element comprises the 4th resistance that the 3rd resistance and one that second FET, that first FET, that one first current source, links to each other with said first current source links to each other with said first current source links to each other with said first FET links to each other with said second FET; Said amplitude detection circuit comprises the 4th electric capacity that the 3rd electric capacity and one that the tenth resistance, one that the 9th resistance, one that the 8th resistance, one that the 7th resistance, one that the 6th resistance, one that the 4th FET that the 3rd FET, that one the 4th current source, one the 5th current source, link to each other with said first FET and said the 3rd resistance links to each other with said second FET and said the 4th resistance, the 5th resistance, one that one the 8th FET, links to each other with said the 4th current source link to each other with said the 5th current source links to each other with said the 4th FET links to each other with said the 3rd FET links to each other with said the 3rd FET links to each other with said the 4th FET links to each other with said the 5th resistance links to each other with said the 6th resistance, and said generating circuit from reference voltage comprises the 6th electric capacity that the 5th electric capacity and one that the 16 resistance, one that the 15 resistance, one that the 14 resistance, one that the 13 resistance, one that the 12 resistance, one that the 11 resistance, one that the 7th FET, that the 6th FET, that one second current source, one the 3rd current source, one the 5th FET, link to each other with said the 5th FET links to each other with said the 5th FET and said the 6th FET links to each other with said the 5th FET links to each other with said the 6th FET links to each other with said second current source links to each other with said the 3rd current source is Xiang Lianed with said the 13 resistance links to each other with said the 14 resistance links to each other with said the 15 resistance links to each other with said the 16 resistance.
4. serial data transmission system as claimed in claim 3; It is characterized in that: the common power end that connects of an end of an end of said first current source, an end of said second current source, an end of said the 3rd current source, an end of said the 4th current source, an end of said the 5th current source, an end of said the 7th resistance, an end of said the 8th resistance, said the 11 resistance and an end of said the 12 resistance; The source class of said first FET and the common other end that is connected said first current source of the source class of said second FET; The common differential data that receives a pair of input of the grid of the grid of said first FET and said second FET; The drain electrode of said first FET is connected the grid of an end of electric capacity, said the 3rd FET with an end, said first of said the 3rd resistance and an end of said the 9th resistance links to each other; The drain electrode of said second FET is connected the grid of an end of electric capacity, said the 4th FET with an end, said second of said the 4th resistance and an end of said the tenth resistance links to each other, and a pair of differential signal of the common output of the drain electrode of the drain electrode of said first FET and said second FET is to the grid of said the 3rd FET and the grid of said the 4th FET.
5. serial data transmission system as claimed in claim 4; It is characterized in that: the other end of the said first connection electric capacity links to each other with an end of said second resistance; The other end of the said second connection electric capacity links to each other with an end of said first resistance; The drain electrode of said the 3rd FET links to each other with the other end of said the 8th resistance; The drain electrode of said the 4th FET links to each other with the other end of said the 7th resistance; The common detection voltage end that connects of one end of one end of the drain electrode of the source class of the source class of said the 3rd FET, said the 4th FET, said the 8th FET, said the 5th resistance, an end of said the 6th resistance, said the 3rd electric capacity and an end of said the 4th electric capacity; The other end of said the 5th resistance links to each other with the other end of said the 4th current source, and the other end of said the 6th resistance links to each other with the other end of said the 5th current source.
6. serial data transmission system as claimed in claim 5; It is characterized in that: the other end of said the 9th resistance is connected the grid of said the 5th FET and the grid of said the 6th FET jointly with the other end of said the tenth resistance; And export a common mode signal to the grid of said the 5th FET and the grid of said the 6th FET; The drain electrode of said the 5th FET links to each other with the other end of said the 11 resistance; The drain electrode of said the 6th FET links to each other with the other end of said the 12 resistance, and the source class of the source class of said the 5th FET, said the 6th FET, the drain electrode of said the 7th FET, an end of said the 15 resistance, an end of said the 16 resistance, an end of said the 5th electric capacity and an end of said the 6th electric capacity connect jointly.
7. serial data transmission system as claimed in claim 6; It is characterized in that: the grid of said the 7th FET links to each other with the grid of said the 8th FET; And connect a voltage end jointly; One end of said the 13 resistance links to each other with the other end of said second current source; One end of said the 14 resistance links to each other with the other end of said the 3rd current source, and the other end of said the 13 resistance is connected said reference voltage end jointly with the other end of said the 15 resistance, and the other end of said the 14 resistance links to each other with the other end of said the 16 resistance.
8. serial data transmission system as claimed in claim 7; It is characterized in that: the common earth terminal that connects of the source class of the other end of the other end of said first resistance, said second resistance, the other end of said the 3rd resistance, the other end of said the 4th resistance, the other end of said the 3rd electric capacity, the other end of said the 4th electric capacity, the other end of said the 5th electric capacity, the other end of said the 6th electric capacity, said the 7th FET and the source class of said the 8th FET; One normal phase input end of said comparer links to each other with said detection voltage end; One inverting input links to each other with said reference voltage end, and whether the said transmitting terminal of output terminal output indication is connected normal indicator signal with said receiving end.
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| CN2011203567858U CN202210280U (en) | 2011-09-22 | 2011-09-22 | Serial data transmission system |
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| CN2011203567858U CN202210280U (en) | 2011-09-22 | 2011-09-22 | Serial data transmission system |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346720A (en) * | 2011-09-22 | 2012-02-08 | 四川和芯微电子股份有限公司 | Transmission system and method of serial data |
| CN102981991A (en) * | 2012-11-13 | 2013-03-20 | 四川和芯微电子股份有限公司 | Serial data transmission system and serial data transmission method |
| CN104994321A (en) * | 2015-06-29 | 2015-10-21 | 龙迅半导体科技(合肥)有限公司 | Transmission circuit and high-definition multimedia interface system |
| CN105375547A (en) * | 2014-08-29 | 2016-03-02 | 雅马哈发动机株式会社 | Charger |
| CN110763922A (en) * | 2019-11-01 | 2020-02-07 | 龙迅半导体（合肥）股份有限公司 | Differential reference voltage generation circuit, peak signal detection circuit, and electronic device |
-
2011
- 2011-09-22 CN CN2011203567858U patent/CN202210280U/en not_active Withdrawn - After Issue
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346720A (en) * | 2011-09-22 | 2012-02-08 | 四川和芯微电子股份有限公司 | Transmission system and method of serial data |
| CN102346720B (en) * | 2011-09-22 | 2014-07-30 | 四川和芯微电子股份有限公司 | Transmission system and method of serial data |
| CN102981991A (en) * | 2012-11-13 | 2013-03-20 | 四川和芯微电子股份有限公司 | Serial data transmission system and serial data transmission method |
| CN105375547A (en) * | 2014-08-29 | 2016-03-02 | 雅马哈发动机株式会社 | Charger |
| CN104994321A (en) * | 2015-06-29 | 2015-10-21 | 龙迅半导体科技(合肥)有限公司 | Transmission circuit and high-definition multimedia interface system |
| CN104994321B (en) * | 2015-06-29 | 2018-06-15 | 龙迅半导体（合肥）股份有限公司 | A kind of transmission circuit and high-definition media interface system |
| CN110763922A (en) * | 2019-11-01 | 2020-02-07 | 龙迅半导体（合肥）股份有限公司 | Differential reference voltage generation circuit, peak signal detection circuit, and electronic device |
| CN110763922B (en) * | 2019-11-01 | 2021-12-31 | 龙迅半导体（合肥）股份有限公司 | Differential reference voltage generation circuit, peak signal detection circuit, and electronic device |
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Address after: 610041 Sichuan city of Chengdu province high tech Zone Kyrgyzstan Road 33 block A No. 9 Patentee after: IPGoal Microelectronics (Sichuan) Co., Ltd. Address before: 402 room 7, building 610041, incubator Park, hi tech Zone, Sichuan, Chengdu Patentee before: IPGoal Microelectronics (Sichuan) Co., Ltd. |
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