CN202141876U

CN202141876U - Thin film transistor array substrate, liquid crystal display panel and liquid crystal display device

Info

Publication number: CN202141876U
Application number: CN201120234159U
Authority: CN
Inventors: 谢振宇
Original assignee: Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2011-07-05
Filing date: 2011-07-05
Publication date: 2012-02-08
Anticipated expiration: 2021-07-05

Abstract

Provided are a thin film transistor array substrate, a liquid crystal display panel and a liquid crystal display device. The thin film transistor array substrate comprises a substrate, a spacer arranged on the substrate and a protruded portion arranged on the substrate and located on the periphery of the spacer, wherein the height of the protruded portion is larger than that of the corresponding position for placing the spacer. The thin film transistor array substrate can effectively prevent the spacer from generating dislocation caused by the fact that the spacer is under external force action, and improve stability of the products under the condition that complexity of the process is not increased and aperture ratio of the products is not affected.

Description

A kind of thin-film transistor array base-plate and display panels and LCD

Technical field

The utility model relates to LCD Technology, relates in particular to a kind of thin-film transistor array base-plate and display panels and LCD.

Background technology

At present, about preventing the design of chock insulator matter dislocation, mainly contain three types: the first kind; Shape through the design chock insulator matter; Chock insulator matter is had prevent the function that misplaces, mainly be designed to special shape to chock insulator matter, such as the concavity structure; Make the concavity structure just in time corresponding to certain raised position of thin-film transistor array base-plate, form a kind of buckle structure; Second type, through etching or other technology, on thin-film transistor array base-plate, form groove, make chock insulator matter be stuck in the groove the inside, also can form a kind of buckle structure; The 3rd type, on thin-film transistor array base-plate, form a screens structure, generally be circular, utilize gate electrode or source-drain electrode to form.

Fig. 1 has provided the structural representation of a kind of active drive thin film transistors array base palte of the prior art, and Fig. 2 is the sectional structure synoptic diagram of the A-A direction of Fig. 1, and Fig. 3 is the sectional structure synoptic diagram of the B-B direction of Fig. 1.Active drive thin film transistors array base palte comprises: glass substrate 1, public electrode 2, gate electrode 3, gate insulator 4, active layer 5, n type semiconductor layer 6, source-drain electrode and data line 7, passivation layer 8, pixel electrode 9, chock insulator matter 10.On glass substrate 1, be provided with public electrode 2 and gate electrode 3; On glass substrate 1 and public electrode 2 and gate electrode 3, be provided with gate insulator 4, depositing semiconductor layers and doping semiconductor layer on gate insulator 4 form active layer 5 and n type semiconductor layer 6 through mask and etching technics; Sedimentary origin leaks metal level on the basis that forms active layer 5 and n type semiconductor layer 6; Form source-drain electrode and data line 7 through mask and etching technics, deposit passivation layer 8 on last basis then is through mask and etching technics; Raceway groove etc. is protected; 9 layers at last pixel deposition electrode, chock insulator matter 10 is arranged on the said passivation layer 8, with certain raised position formation buckle structure on the said passivation layer 8.

There is following shortcoming in the existing technology of chock insulator matter dislocation that prevents:

The first kind will design the chock insulator matter of given shape, and the technology more complicated for example is designed to " recessed " shape, needs special technology to form.In addition, about the size of chock insulator matter also can double, aperture opening ratio was affected;

Second type, the concavity structure also needs complicated technology, such as on passivation layer, forming groove, needs the gray-tone mask technology equally;

The 3rd type, form circular configuration through the source-drain electrode metal and can reduce effective display area, reduce aperture opening ratio.

The utility model content

Above-mentioned technical matters to the prior art existence; The utility model provides a kind of not to be increased process complexity and not to influence under the situation of product aperture opening ratio, effectively prevents owing to chock insulator matter receives thin-film transistor array base-plate and display panels and the LCD that the external force effect produces dislocation.

The utility model provides a kind of thin-film transistor array base-plate that prevents chock insulator matter dislocation, comprises that substrate and be arranged at the chock insulator matter on the said substrate also comprises:

Be arranged on the substrate, and be positioned at the jut around the said chock insulator matter, the height of said jut is greater than the height of the correspondence position of placing said chock insulator matter.

The utility model also provides a kind of display panels, comprises described thin-film transistor array base-plate.

The utility model also provides a kind of LCD, comprises described display panels.

A kind of thin-film transistor array base-plate and display panels and LCD that prevents the chock insulator matter dislocation that the utility model provides; On the prior art basis; Increased jut at thin-film transistor array base-plate; Limit chock insulator matter and produced dislocation receiving external force to do the time spent, thereby improved the stability of product.

Description of drawings

Fig. 1 is the structural representation of prior art active driving TFT array base palte;

Fig. 2 is the sectional structure synoptic diagram of the A-A direction of Fig. 1;

Fig. 3 is the sectional structure synoptic diagram of the B-B direction of Fig. 1;

Fig. 4 is the structural representation of the utility model embodiment one;

Fig. 5 is the sectional structure synoptic diagram of the A-A direction of Fig. 4;

Fig. 6 is the sectional structure synoptic diagram of the B-B direction of Fig. 4;

Fig. 7 is the structural representation that forms gate electrode and grid bonding jumper in the utility model production process;

Fig. 8 is the structural representation that forms semiconductor layer and source leakage bonding jumper in the utility model production process;

Fig. 9 is the structural representation of the utility model embodiment two.

Embodiment

The utility model provides a kind of thin-film transistor array base-plate and display panels and LCD; This thin-film transistor array base-plate is not increasing process complexity and is not influencing under the situation of product aperture opening ratio; Effectively prevent PS (Post Spacer; Cylindrical spacer) owing to receiving the problem that the external force effect produces dislocation, improved the stability of product.

The utility model provides a kind of thin-film transistor array base-plate, comprising: substrate and be arranged at the chock insulator matter on the said substrate also comprises:

Be provided with said jut in the both sides of said chock insulator matter.

Said jut be shaped as strip structure or " L " shape structure.

Said jut leaks bonding jumper by grid bonding jumper, semiconductor layer and source and constitutes.

Said grid bonding jumper is arranged on the deposition grid metal level of said substrate.

Said semiconductor layer is positioned on the gate insulator of said substrate, and said source is leaked the bonding jumper source that is arranged at and leaked on the metal level.

The thickness of said semiconductor layer is 2000A～3000A, and the thickness that bonding jumper is leaked in said source is 2000A～4000A.

As shown in Figure 4; Structural representation for the utility model embodiment one; Fig. 5 and Fig. 6 are respectively the sectional structure synoptic diagram of Fig. 4 in A-A and B-B direction; Comprise: the jut 11 that glass substrate 1, public electrode 2, grid 3, gate insulator 4, active layer 5, n type semiconductor layer 6, source are leaked metal level 7, passivation layer 8, pixel electrode 9, chock insulator matter 10 and be made up of grid bonding jumper 111, semiconductor layer 112 and source leakage bonding jumper 113; Jut is a list structure, and grid bonding jumper 111 is arranged on the deposition grid metal level of substrate.

The manufacture craft process of the utility model embodiment one:

Step 1, deposition grid metal level through mask and etching technics, forms grid 3, public electrode 2 and grid bonding jumper 111 on glass substrate 1;

Step 2, successive sedimentation gate insulator 4 on the glass substrate 1 of completing steps 1;

Step 3 is on the glass substrate 1 of completing steps 2, through mask and etching technics; On said gate insulator 4, form active layer 5 and n type semiconductor layer 6, source-drain electrode and data line 7, semiconductor layer 112 are positioned on the said gate insulator 4; Between grid line and public electrode, form amorphous silicon baffle layer and metal baffle layer simultaneously; Offer perforation at amorphous silicon baffle layer and metal baffle layer, it is corresponding with the grid line shrinkage pool to bore a hole, and the source is leaked bonding jumper 113 and is arranged at upper semiconductor layer 112.

Step 4, on the glass substrate 1 of completing steps 3, deposit passivation layer 8 and via hole.

Step 5 on the glass substrate 1 of completing steps 4, forms pixel electrode 9, and pixel electrode 9 connects source-drain electrode and data line 7 through via hole.

Gate insulator 4 is specially SiN _x, SiO _xOr SiO _xN _yMonofilm, perhaps be SiN _x, SiO _xOr SiO _xN _yOne of or composite membrane that combination in any constituted; Source-drain electrode and data line 7 are specially the monofilm of Mo, MoW or Cr, perhaps are one of Mo, MoW or Cr or composite membrane that combination in any constituted.

As shown in Figure 7; Leak the structural representation of bonding jumper for forming semiconductor layer and source in the utility model production process, deposition grid metal level on glass substrate 1 is through mask and etching technics; Form common electrode 2, gate electrode 3 and the grid bonding jumper 111 that constitutes jut 11.

As shown in Figure 8; Leak the structural representation of bonding jumper for forming semiconductor layer and source in the utility model production process; Deposition gate insulation layer 4 on the substrate of accomplishing above-mentioned technology; Active layer 5 leaks metal level 7 with ohmic contact layer 6 and source, through mask and etching technics, forms data line and source-drain electrode, the semiconductor layer 112 that constitutes jut 11, source leakage bonding jumper 113.

As shown in Figure 9, be the structural representation of the utility model embodiment two, the shape of one of which side projecture part is inequality, employing be " L " type structure, all the other are identical with such scheme.

The utility model provides a kind of thin-film transistor array base-plate that prevents the chock insulator matter dislocation on the prior art basis, has increased jut, makes chock insulator matter can not produce dislocation receiving under the external force effect, has improved the stability of product.

Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from the spirit and scope of the present invention.Like this, belong within the scope of the utility model claim and equivalent technologies thereof if these of the utility model are revised with modification, then the utility model also is intended to comprise these changes and modification interior.

Claims

1. thin-film transistor array base-plate comprises: substrate and be arranged at the chock insulator matter on the said substrate, it is characterized in that, and also comprise:

2. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, is provided with said jut in the both sides of said chock insulator matter.

3. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, said jut be shaped as list structure or " L " shape structure.

4. thin-film transistor array base-plate as claimed in claim 1 is characterized in that, said jut leaks bonding jumper by grid bonding jumper, semiconductor layer and source and constitutes.

5. thin-film transistor array base-plate as claimed in claim 4 is characterized in that, said grid bonding jumper is arranged on the deposition grid metal level of said substrate.

6. thin-film transistor array base-plate as claimed in claim 4 is characterized in that, said semiconductor layer is positioned on the gate insulator of said substrate, and said source is leaked the bonding jumper source that is arranged at and leaked on the metal level.

7. thin-film transistor array base-plate as claimed in claim 4 is characterized in that, the thickness of said semiconductor layer is 2000A～3000A, and the thickness that bonding jumper is leaked in said source is 2000A～4000A.

8. a display panels is characterized in that, comprises like arbitrary described thin-film transistor array base-plate among the claim 1-7.

9. a LCD is characterized in that, comprises display panels as claimed in claim 8.