CN202110529U - Fault-tolerant solid nonvolatile storage equipment and multi-channel fault-tolerant storage equipment - Google Patents
Fault-tolerant solid nonvolatile storage equipment and multi-channel fault-tolerant storage equipment Download PDFInfo
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- CN202110529U CN202110529U CN2011201020428U CN201120102042U CN202110529U CN 202110529 U CN202110529 U CN 202110529U CN 2011201020428 U CN2011201020428 U CN 2011201020428U CN 201120102042 U CN201120102042 U CN 201120102042U CN 202110529 U CN202110529 U CN 202110529U
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Abstract
The utility model relates fault-tolerant solid nonvolatile storage equipment, which comprises an interface controller, a flash controller, a solid nonvolatile storage chip array, a circuit board and at least one spare solid nonvolatile storage chip, wherein the spare solid nonvolatile storage chip is positioned on the circuit board. By arranging the spare nonvolatile storage chip in the fault-tolerant solid nonvolatile storage equipment, the production cost and the test cost of the equipment can be reduced, the yield of the equipment can be ensured, the purpose of prolonging the service life of the storage equipment can be achieved, and wide application of the solid nonvolatile storage equipment can be realized. The utility model also provides multi-channel fault-tolerant solid nonvolatile storage equipment.
Description
Technical field
The utility model relates to the mass data storage technical field, particularly relates to a kind of solid-state non-volatile memory apparatus and the fault-tolerant solid state, non-volatile memory of hyperchannel.
Background technology
At present, solid-state non-volatile memory apparatus is progressively accepted by vast memory device user, and it compares particularly hard disk of conventional memory device, has many superiority that it can not be compared, and for example reads and writes speed, performance, low-power consumption or the like.But it has limited the particularly application widely of solid state hard disc of this type of memory device than higher price and limited these shortcomings of storage times.
For present widely used solid-state non-volatile memory apparatus; Its expensive price mainly comes from expensive memory device; NAND type flash chip for example; This type memory device is because its special manufacturing process and strict Chip Packaging testing expense cause its overall price relatively more expensive, this be rear end equipment manufacturer can not determine and optimize.And limited for its storage times be because the cause of its technology manufacturing causes; The device fabrication commercial city of general rear end is through storage chip being done the wear leveling design; Realize the serviceable life of prolongation equipment, but can not satisfy the requirement of actual use far away as far as possible.
The utility model content
The technical matters that (one) will solve
To more than, the utility model adopts a kind of fault-tolerant solid-state non-volatile memory apparatus, can realize reducing the device fabrication testing expense, guarantees the yield of equipment, can also prolong memory device serviceable life simultaneously.
(2) technical scheme
In order to solve the problems of the technologies described above; The utility model provides a kind of fault-tolerant solid-state non-volatile memory apparatus; Comprise: interface controller, flash controller, solid state nonvolatile storage chip array and circuit board; The external host computer system of said interface controller, said interface controller, flash controller and circuit board are electrically connected successively, and said solid state nonvolatile storage chip array is arranged on the said circuit board; Said host computer system is through said interface controller, flash controller; Solid state nonvolatile storage chip array on the circuit board is carried out read-write operation, and said fault-tolerant solid-state non-volatile memory apparatus also comprises the subsequent use solid state nonvolatile storage chip of a slice at least; Said subsequent use solid state nonvolatile storage chip is positioned on the said circuit board.
Further, comprise fault diagnosis module, chip replacement module and bad piece logging modle in the said flash controller;
The failure chip that said fault diagnosis module monitoring occurs sends chip replacement module and bad piece logging modle with the address of said failure chip;
Said chip replacement module is given said subsequent use solid state nonvolatile storage chip with the address of said failure chip;
Flash controller no longer carries out read-write operation to the chip of the said address of record in the said bad piece logging modle.
Further, said flash controller comprises that threshold value is provided with module, chip monitoring modular, chip Switching Module;
Said threshold value is provided with and is provided with chip reading times threshold value in the module;
When the reading times of the said solid state nonvolatile storage chip of said chip monitoring module monitors, said reading times surpass said chip reading times threshold value, said solid state nonvolatile storage chip address is sent the chip Switching Module;
Said chip Switching Module exchanges said solid state nonvolatile storage chip address and said subsequent use solid state nonvolatile storage chip address.
Further, said flash controller also comprises the chip address logging modle,
When the reading times of the said solid state nonvolatile storage chip of said chip monitoring module monitors, said reading times surpass said chip reading times threshold value, the chip address logging modle is sent in the address of said solid state nonvolatile storage chip;
Said chip address logging modle record reading times surpasses the address of the solid state nonvolatile storage chip of said threshold value;
When said chip address logging modle has write down the address of whole said solid state nonvolatile storage chips, send instructions to said threshold value module and chip monitoring modular are set; Said threshold value is provided with module and resets threshold value; The reading times zero clearing of the solid state nonvolatile storage chip that the chip monitoring modular is monitored.
The utility model also provides a kind of hyperchannel fault-tolerant solid-state non-volatile memory apparatus; Comprise: interface controller, flash controller, M * N solid state nonvolatile storage chip array and circuit board; Said M and N are the integer more than or equal to 1; The external host computer system of said interface controller, said interface controller, flash controller and circuit board are electrically connected successively, and said M * N solid state nonvolatile storage chip array is arranged on the said circuit board; Said host computer system is through said interface controller, flash controller; M on the circuit board * N solid state nonvolatile storage chip array read with the unit of classifying as carry out read-write operation, the fault-tolerant solid-state non-volatile memory apparatus of said hyperchannel also comprises at least one subsequent use solid state nonvolatile storage chip alignment; Solid state nonvolatile storage chip number M in the said subsequent use solid state nonvolatile storage chip alignment, said subsequent use solid state nonvolatile storage chip alignment is positioned on the said circuit board.
Further, said flash controller comprises fault row diagnostic module, chip alignment replacement module and bad piece row logging modle;
The failure chip row that said fault row diagnostic module monitoring occurs are with the first address transmission chip alignment replacement module and the bad piece row logging modle of said failure chip row;
Said chip alignment replacement module is given said subsequent use solid state nonvolatile storage chip alignment with the first address of said failure chip row;
Said bad piece row logging modle writes down the address of said failure chip row, and flash controller no longer carries out read-write operation to said failure chip row.
Further, said flash controller comprises that the threshold value row are provided with module, chip alignment monitoring modular, chip alignment Switching Module;
Said threshold value row are provided with and are provided with chip alignment reading times threshold value in the module;
When the reading times of the said solid state nonvolatile storage chip alignment of said chip alignment monitoring module monitors, said reading times surpass said chip alignment reading times threshold value, the chip alignment Switching Module is sent in said solid state nonvolatile storage chip alignment address;
Said chip alignment Switching Module exchanges said solid state nonvolatile storage chip alignment address and said subsequent use solid state nonvolatile storage chip alignment first address.
Further, said flash controller also comprises chip alignment address logging modle,
When the reading times of the said solid state nonvolatile storage chip alignment of said chip alignment monitoring module monitors, said reading times surpass said chip reading times threshold value, the first address of said solid state nonvolatile storage chip alignment is sent chip alignment address logging modle;
Said chip alignment address logging modle record reading times surpasses the first address of the solid state nonvolatile storage chip alignment of said threshold value;
When said chip alignment address logging modle has write down the first address of whole said solid state nonvolatile storage chip alignments, send instructions to said threshold value row module and chip alignment monitoring modular are set; Said threshold value row are provided with module and reset chip alignment reading times threshold value; The reading times zero clearing of the solid state nonvolatile storage chip alignment that the chip alignment monitoring modular is monitored.
(3) beneficial effect
Increase the setting of slack storage chip on the board design of memory device that technique scheme provides; And through Module Design in the flash controller; When equipment finds that flash memory has fault in the production back end test; Use the slack storage chip to replace failure chip, thereby, also can not influence the yield that memory device is produced even guarantee that chip does not pass through packaging and testing; Simultaneously, when having in the equipment after flash chip reaches the access times threshold value that certain access times are default, will be replaced by spare chip, thereby, come the serviceable life of effective prolongation equipment through this replacement operation constantly.Adopt the setting that increases the slack storage chip through the utility model, come effectively to ensure the yield of non-volatile memory chip equipment, and can prolong the serviceable life of equipment.
Description of drawings
Fig. 1 is a solid-state non-volatile memory apparatus synoptic diagram in the prior art;
Fig. 2 is the synoptic diagram of single spare chip design of solid-state non-volatile memory apparatus among the utility model embodiment;
Fig. 3 is the solid-state non-volatile memory apparatus slack storage of a hyperchannel chip alignment meter synoptic diagram among the utility model embodiment;
Wherein, 1: subsequent use solid state nonvolatile storage chip, 2: subsequent use solid state nonvolatile storage chip alignment; 3: the solid state nonvolatile storage chip array.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the embodiment of the utility model is described in further detail.Following examples are used to explain the utility model, but are not used for limiting the scope of the utility model.
Fig. 1 is a solid-state non-volatile memory apparatus synoptic diagram in the prior art, and as shown in Figure 1, solid-state non-volatile memory apparatus mainly comprises interface controller, flash controller and the flash array of being made up of one or more flash memories.Wherein, Interface controller is mainly used in and instructs with main frame and data mutual; Flash controller is the control module of whole memory device; The control signal of control and interface controller and flash array and the transmission of data, flash array are that the storage medium chip of entire equipment is formed, and are the terminals of entire equipment information stores.
Fig. 2 is the synoptic diagram of single spare chip design of solid-state non-volatile memory apparatus among the utility model embodiment; As shown in Figure 2, a kind of fault-tolerant solid-state non-volatile memory apparatus comprises: interface controller, flash controller, solid state nonvolatile storage chip array 3 and circuit board; The external host computer system of said interface controller; Said interface controller, flash controller and circuit board are electrically connected successively, and said solid state nonvolatile storage chip array 3 is arranged on the said circuit board, and said host computer system is through said interface controller, flash controller; Solid state nonvolatile storage chip array on the circuit board 3 is carried out read-write operation
Said fault-tolerant solid-state non-volatile memory apparatus also comprises the subsequent use solid state nonvolatile storage chip 1 of a slice at least; Said subsequent use solid state nonvolatile storage chip 1 is positioned on the said circuit board.
In the present embodiment; The flash chip or the wafer of solid-state non-volatile memory apparatus flash chip that need not pass through test or not process encapsulation directly are welded on the printed circuit board (PCB) of said fault-tolerant solid-state non-volatile memory apparatus; Simultaneously, the position of many at least one spare chips of design or wafer on circuit board.Because flash chip that is welded or wafer be not through test or encapsulation; When in device detection procedure, finding to have chip or wafer to have fault maybe can not use; Just chip or the wafer reserved are replaced problematic chip through the configuration of flash controller; Be said flash controller when solid state nonvolatile storage chip battle array is carried out read-write operation on the circuit board; When certain described solid state nonvolatile storage chip breaks down; Fetch program can not carry out, and flash controller replaces with said subsequent use solid state nonvolatile storage chip 1 with the flash controller chip that breaks down, and can avoid the test cumbersome procedure after chip manufacturing is accomplished through being provided with of this subsequent use solid state nonvolatile storage chip 1; Remedy flash chip or wafer and do not have defective and problem, so that guarantee that the yield of entire equipment processing does not have great changes through packaging and testing.Because the replacement to spare chip realizes through flash controller automatically, for computing machine and user thereof, to the not influence of reading performance of said non-volatile memory chip equipment.
Comprise fault diagnosis module, chip replacement module and bad piece logging modle in the said flash controller; The failure chip that said fault diagnosis module monitoring occurs sends chip replacement module and bad piece logging modle with the address of said failure chip; Said chip replacement module is given said subsequent use solid state nonvolatile storage chip 1 with the address of said failure chip; Flash controller no longer carries out read-write operation to the chip of the said address of record in the said bad piece logging modle.The utility model is through being provided with fault diagnosis module in flash controller; Chip replacement module and bad piece logging modle can effectively be found out the said non-volatile memory chip that breaks down; And said subsequent use non-volatile memory chip and the said non-volatile memory chip that breaks down carried out the address exchange; When reading said failure chip again, said spare chip is pointed in the address, can realize the replacement to the said non-volatile memory chip that breaks down.
Because wherein the flash chip of the overwhelming majority is even without the process packaging and testing, its performance also can guarantee, therefore, is good in the test of most product after production.Said spare chip is not used to replace failure chip.Then, the said chip that is not replaced as spare chip will be used to do the prolongation service life of equipment and use.After said solid-state non-volatile memory apparatus flash chip reading times reaches certain appointment reading times threshold value; Through configuration to the flash memory control module; Use spare chip to replace the chip that reaches the reading times threshold value; Thereby assurance equipment still can normally use, so that reaches the purpose that prolongs service life of equipment.
Said flash controller comprises that threshold value is provided with module, chip monitoring modular, chip Switching Module; Said threshold value is provided with and is provided with chip reading times threshold value in the module; When the reading times of the said solid state nonvolatile storage chip of said chip monitoring module monitors, said reading times surpass said chip reading times threshold value, said solid state nonvolatile storage chip address is sent the chip Switching Module; Said chip Switching Module exchanges said solid state nonvolatile storage chip address and said subsequent use solid state nonvolatile storage chip 1 address.
Said threshold value is provided with module chips reading times threshold value through the program setting.Through the best reading times of the said non-volatile memory chip of verification experimental verification, as said chip reading times threshold value, when surpassing said reading times threshold value, spare chip will saidly surpass the chip of reading times threshold value and replace.Can realize that like this all non-volatile memory chips evenly use, can effectively prolong the average life of said chip array.
Said flash controller also comprises the chip address logging modle; The reading times of the said solid state nonvolatile storage chip of said chip monitoring module monitors; When said reading times surpasses said chip reading times threshold value, the chip address logging modle is sent in the address of said solid state nonvolatile storage chip; Said chip address logging modle record reading times surpasses the address of the solid state nonvolatile storage chip of said threshold value; When said chip address logging modle has write down the address of whole said solid state nonvolatile storage chips, send instructions to said threshold value module and chip monitoring modular are set; Said threshold value is provided with module and resets threshold value; The reading times zero clearing of the solid state nonvolatile storage chip that the chip monitoring modular is monitored.
After all chips have all reached the number of times that has read threshold setting and have been replaced, reset new threshold value again, once more all chips are replaced accordingly.For example in use, when one of them chip access times reaches threshold number, just can be replaced, when so just having a plurality of chips and reaching preset requirement gradually by spare chip; Replaced by spare chip, simultaneously, substituted chip is not to have gone out of use; In order to reach better optimize, a plurality of access times threshold values are set, when other chips are used higher access times; Can be replaced because of the chip that reaches some and be replaced by these again, like this, can better reach a kind of optimization; Constantly have by the chip of excessive use to be replaced, let other do not used a period of time, be replaced up again by the chip of frequent use; Therefore, overall equipment can significantly be increased service time, has prolonged the life-span of equipment effectively.
Equally, can also be designed to the replacement of whole passage for multichannel flash memory device or be that unit carries out fault-tolerant design with the passage.Fig. 3 is the solid-state non-volatile memory apparatus slack storage of a hyperchannel chip alignment meter synoptic diagram among the utility model embodiment.As shown in Figure 3; The utility model also provides a kind of hyperchannel fault-tolerant solid-state non-volatile memory apparatus; Comprise: interface controller, flash controller, 4 * 4 solid state nonvolatile storage chip array and circuit boards; The external host computer system of said interface controller, said interface controller, flash controller and circuit board are electrically connected successively, and said 4 * 4 solid state nonvolatile storage chip arrays are arranged on the said circuit board; Said host computer system is through said interface controller, flash controller; 4 * 4 solid state nonvolatile storage chip arrays on the circuit board are read with the unit of classifying as carry out read-write operation, the fault-tolerant solid-state non-volatile memory apparatus of said hyperchannel also comprises a subsequent use solid state nonvolatile storage chip alignment 2; Solid state nonvolatile storage chip number 4 in the said subsequent use solid state nonvolatile storage chip alignment 2, said subsequent use solid state nonvolatile storage chip alignment 2 is positioned on the said circuit board.
When solid-state non-volatile memory apparatus was carried out the passage read operation with the unit of classifying as, the first address of chip alignment was as searching the address of respective column, and the chip address distributing order is for arranging, so only the first address of affiliated chip alignment is carried out record continuously in the row.When searching respective column, get final product through reading the chip alignment first address.
Said flash controller comprises fault row diagnostic module, chip alignment replacement module and bad piece row logging modle;
The failure chip row that said fault row diagnostic module monitoring occurs are with the first address transmission chip alignment replacement module and the bad piece row logging modle of said failure chip row;
Said chip alignment replacement module is given said subsequent use solid state nonvolatile storage chip alignment 2 with the first address of said failure chip row;
Said bad piece row logging modle writes down the address of said failure chip row, and flash controller no longer carries out read-write operation to said failure chip row.
Find inoperable chip when fault row diagnostic module and list now; Through chip alignment replacement module and bad piece row logging modle; The failure chip row are replaced with the spare chip row; Promptly exchange, when reading said failure chip row once more, just can point to said spare chip row automatically, realized the replacement that failure chip is listed as through first address with above-mentioned two row.
Similar with reading of single chips, when said chip alignment reading times too much, must be big more to the consumption of chip alignment chips, so said chip alignment also is provided with corresponding reading times threshold value, when surpassing assign thresholds, it is replaced.
Said flash controller comprises that the threshold value row are provided with module, chip alignment monitoring modular, chip alignment Switching Module;
Said threshold value row are provided with and are provided with chip alignment reading times threshold value in the module;
When the reading times of the said solid state nonvolatile storage chip alignment of said chip alignment monitoring module monitors, said reading times surpass said chip alignment reading times threshold value, the chip alignment Switching Module is sent in said solid state nonvolatile storage chip alignment address;
Said chip alignment Switching Module exchanges said solid state nonvolatile storage chip alignment address and said subsequent use solid state nonvolatile storage chip alignment 2 first addresss.
When all chip alignment reading times have all reached the threshold value of access times,, replace use more again for being replaced the said chip alignment that surpasses the access times threshold value.
Said flash controller also comprises chip alignment address logging modle,
When the reading times of the said solid state nonvolatile storage chip alignment of said chip alignment monitoring module monitors, said reading times surpass said chip reading times threshold value, the first address of said solid state nonvolatile storage chip alignment is sent chip alignment address logging modle;
Said chip alignment address logging modle record reading times surpasses the first address of the solid state nonvolatile storage chip alignment of said threshold value;
When said chip alignment address logging modle has write down the first address of whole said solid state nonvolatile storage chip alignments, send instructions to said threshold value row module and chip alignment monitoring modular are set; Said threshold value row are provided with module and reset chip alignment reading times threshold value; The reading times zero clearing of the solid state nonvolatile storage chip alignment that the chip alignment monitoring modular is monitored.
Can find out that by above embodiment the utility model embodiment can increase spare chip through adopting, and has improved the optimum of memory device, and prolongs the serviceable life of memory device, effectively reduces cost when improving performance.
The above only is the preferred implementation of the utility model; Should be understood that; For those skilled in the art; Under the prerequisite that does not break away from the utility model know-why, can also make some improvement and replacement, these improvement and replacement also should be regarded as the protection domain of the utility model.
Claims (8)
1. fault-tolerant solid-state non-volatile memory apparatus; Comprise: interface controller, flash controller, solid state nonvolatile storage chip array and circuit board; The external host computer system of said interface controller, said interface controller, flash controller and circuit board are electrically connected successively, and said solid state nonvolatile storage chip array is arranged on the said circuit board; Said host computer system is through said interface controller, flash controller; Solid state nonvolatile storage chip array on the circuit board is carried out read-write operation, it is characterized in that
Said fault-tolerant solid-state non-volatile memory apparatus also comprises the subsequent use solid state nonvolatile storage chip of a slice at least; Said subsequent use solid state nonvolatile storage chip is positioned on the said circuit board.
2. fault-tolerant solid-state non-volatile memory apparatus according to claim 1 is characterized in that, comprises fault diagnosis module, chip replacement module and bad piece logging modle in the said flash controller;
The failure chip that said fault diagnosis module monitoring occurs sends chip replacement module and bad piece logging modle with the address of said failure chip;
Said chip replacement module is given said subsequent use solid state nonvolatile storage chip with the address of said failure chip;
Flash controller no longer carries out read-write operation to the chip of the said address of record in the said bad piece logging modle.
3. fault-tolerant solid-state non-volatile memory apparatus according to claim 1 and 2 is characterized in that said flash controller comprises that threshold value is provided with module, chip monitoring modular, chip Switching Module;
Said threshold value is provided with and is provided with chip reading times threshold value in the module;
When the reading times of the said solid state nonvolatile storage chip of said chip monitoring module monitors, said reading times surpass said chip reading times threshold value, said solid state nonvolatile storage chip address is sent the chip Switching Module;
Said chip Switching Module exchanges said solid state nonvolatile storage chip address and said subsequent use solid state nonvolatile storage chip address.
4. fault-tolerant solid-state non-volatile memory apparatus according to claim 3 is characterized in that said flash controller also comprises the chip address logging modle,
When the reading times of the said solid state nonvolatile storage chip of said chip monitoring module monitors, said reading times surpass said chip reading times threshold value, the chip address logging modle is sent in the address of said solid state nonvolatile storage chip;
Said chip address logging modle record reading times surpasses the address of the solid state nonvolatile storage chip of said threshold value;
When said chip address logging modle has write down the address of whole said solid state nonvolatile storage chips, send instructions to said threshold value module and chip monitoring modular are set; Said threshold value is provided with module and resets threshold value; The reading times zero clearing of the solid state nonvolatile storage chip that the chip monitoring modular is monitored.
5. fault-tolerant solid-state non-volatile memory apparatus of hyperchannel; Comprise: interface controller, flash controller, M * N solid state nonvolatile storage chip array and circuit board, said M and N are the integer more than or equal to 1, the external host computer system of said interface controller; Said interface controller, flash controller and circuit board are electrically connected successively; Said M * N solid state nonvolatile storage chip array is arranged on the said circuit board, and said host computer system is passed through said interface controller, flash controller, M on the circuit board * N solid state nonvolatile storage chip array is read with the unit of classifying as carry out read-write operation; It is characterized in that
The fault-tolerant solid-state non-volatile memory apparatus of said hyperchannel; Also comprise at least one subsequent use solid state nonvolatile storage chip alignment; Solid state nonvolatile storage chip number M in the said subsequent use solid state nonvolatile storage chip alignment, said subsequent use solid state nonvolatile storage chip alignment is positioned on the said circuit board.
6. the fault-tolerant solid-state non-volatile memory apparatus of hyperchannel according to claim 5 is characterized in that, said flash controller comprises fault row diagnostic module, chip alignment replacement module and bad piece row logging modle;
The failure chip row that said fault row diagnostic module monitoring occurs are with the first address transmission chip alignment replacement module and the bad piece row logging modle of said failure chip row;
Said chip alignment replacement module is given said subsequent use solid state nonvolatile storage chip alignment with the first address of said failure chip row;
Said bad piece row logging modle writes down the address of said failure chip row, and flash controller no longer carries out read-write operation to said failure chip row.
7. according to claim 5 or the fault-tolerant solid-state non-volatile memory apparatus of 6 described hyperchannels, it is characterized in that said flash controller comprises that the threshold value row are provided with module, chip alignment monitoring modular, chip alignment Switching Module;
Said threshold value row are provided with and are provided with chip alignment reading times threshold value in the module;
When the reading times of the said solid state nonvolatile storage chip alignment of said chip alignment monitoring module monitors, said reading times surpass said chip alignment reading times threshold value, the chip alignment Switching Module is sent in said solid state nonvolatile storage chip alignment address;
Said chip alignment Switching Module exchanges said solid state nonvolatile storage chip alignment address and said subsequent use solid state nonvolatile storage chip alignment first address.
8. the fault-tolerant solid-state non-volatile memory apparatus of hyperchannel according to claim 7 is characterized in that said flash controller also comprises chip alignment address logging modle,
When the reading times of the said solid state nonvolatile storage chip alignment of said chip alignment monitoring module monitors, said reading times surpass said chip reading times threshold value, the first address of said solid state nonvolatile storage chip alignment is sent chip alignment address logging modle;
Said chip alignment address logging modle record reading times surpasses the first address of the solid state nonvolatile storage chip alignment of said threshold value;
When said chip alignment address logging modle has write down the first address of whole said solid state nonvolatile storage chip alignments, send instructions to said threshold value row module and chip alignment monitoring modular are set; Said threshold value row are provided with module and reset chip alignment reading times threshold value; The reading times zero clearing of the solid state nonvolatile storage chip alignment that the chip alignment monitoring modular is monitored.
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| CN2011201020428U CN202110529U (en) | 2011-04-08 | 2011-04-08 | Fault-tolerant solid nonvolatile storage equipment and multi-channel fault-tolerant storage equipment |
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| CN2011201020428U CN202110529U (en) | 2011-04-08 | 2011-04-08 | Fault-tolerant solid nonvolatile storage equipment and multi-channel fault-tolerant storage equipment |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021471A (en) * | 2012-12-24 | 2013-04-03 | 上海新储集成电路有限公司 | Memory and memorizing method thereof |
| CN103279424A (en) * | 2013-05-15 | 2013-09-04 | 建荣集成电路科技(珠海)有限公司 | Damaged queue management device and method of Nand Flash |
| CN110187833A (en) * | 2019-05-22 | 2019-08-30 | 西安微电子技术研究所 | A kind of redundancy approach of the storage array of chip-scale |
-
2011
- 2011-04-08 CN CN2011201020428U patent/CN202110529U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021471A (en) * | 2012-12-24 | 2013-04-03 | 上海新储集成电路有限公司 | Memory and memorizing method thereof |
| CN103021471B (en) * | 2012-12-24 | 2016-08-03 | 上海新储集成电路有限公司 | A kind of memorizer and storage method thereof |
| CN103279424A (en) * | 2013-05-15 | 2013-09-04 | 建荣集成电路科技(珠海)有限公司 | Damaged queue management device and method of Nand Flash |
| CN110187833A (en) * | 2019-05-22 | 2019-08-30 | 西安微电子技术研究所 | A kind of redundancy approach of the storage array of chip-scale |
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| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: Chun Hing Road Xiangcheng Economic Development Zone in Suzhou City, Jiangsu Province, No. 50 215132 Patentee after: Suzhou eTron Polytron Technologies Inc Address before: 215132 Yong Qing Road, Huangqiao Industrial Park, Suzhou, Jiangsu, Xiangcheng District Patentee before: Suzhou Etron Electronics Co.,Ltd |
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| CX01 | Expiry of patent term |
Granted publication date: 20120111 |
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| CX01 | Expiry of patent term |