CN202093098U - Signal detection circuit - Google Patents
Signal detection circuit Download PDFInfo
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- CN202093098U CN202093098U CN2011202033730U CN201120203373U CN202093098U CN 202093098 U CN202093098 U CN 202093098U CN 2011202033730 U CN2011202033730 U CN 2011202033730U CN 201120203373 U CN201120203373 U CN 201120203373U CN 202093098 U CN202093098 U CN 202093098U
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Abstract
The utility model relates to a signal detection circuit which is used for detecting the rising and the dropping time of an input voltage signal; the signal detection circuit comprises a first reference voltage end, a second reference voltage end, a first comparator which is connected with the first reference voltage end, a second comparator which is connected with the second reference voltage end, a logic device which is connected with the first and the second comparators, and a capacitor which is connected with the logic device; the first comparator and the second comparator receive the input voltage signal together; the first reference voltage end is a minimum voltage input end of the input voltage signal; the second reference voltage end is a maximum voltage input end of the input voltage signal; and the signal output by the logic device is filtered by the capacitor, and a constant voltage which is in proportion to the rising and the falling time of the input voltage signal is output. The circuit has a simple structure and higher speed.
Description
Technical field
The utility model relates to a kind of testing circuit, refers to a kind of signal deteching circuit that is used for the detection signal rise and fall time especially.
Background technology
The rise and fall time of signal refers to signal and is carved into from zero the time and reaches steady-state value first or dropped to for zero constantly time from steady-state value.Usually rise and fall time is defined as response curve and rises to the required time of steady-state value 90% from 10% of steady-state value.
The existing method that is used for the rise and fall time of detection signal has a lot, for example come the rise and fall time of detection signal by computer programming, utilize assembly language to come the state of detection signal port, by the different instruction that the different conditions computer-chronograph sends, calculate the rise and fall time of signal.This shows that existing signal rise and fall time testing circuit and method are simple inadequately.
Summary of the invention
In view of above content, be necessary to provide a kind of simple in structure and can detect the signal deteching circuit of signal rise and fall time.
A kind of signal deteching circuit, be used to detect the rise and fall time of an input voltage signal, described signal deteching circuit comprises one first reference voltage end, one second reference voltage end, one first comparer that links to each other with described first reference voltage end, one second comparer that links to each other with described second reference voltage end, one logical device that links to each other with described first comparer and described second comparer and an electric capacity that links to each other with described logical device, the described input voltage signal of the common reception of described first comparer and described second comparer, the minimum voltage input end that described first reference voltage end is an input voltage signal, the ceiling voltage input end that described second reference voltage end is an input voltage signal, the signal of described logical device output carry out the proportional constant voltage of rise and fall time of output one magnitude of voltage and input voltage signal after the filtering by described electric capacity.
Preferably, described signal deteching circuit comprises that also one is used for the input signal end and that input voltage signal inputs to described first comparer and described second comparer is used to export the output signal end of constant voltage.
Preferably, described logical device be one with the door, described input signal end links to each other with a normal phase input end of described first comparer and an inverting input of described second comparer, described first reference voltage end links to each other with an inverting input of described first comparer, and described second reference voltage end links to each other with a normal phase input end of described second comparer.
Preferably, one output terminal of described first comparer and an output terminal of described second comparer link to each other with two input ends of door with described respectively, describedly link to each other the other end ground connection of described electric capacity with an end of described output signal end and described electric capacity with the output terminal of door.
Preferably, described logical device be one or the door, described input signal end links to each other with an inverting input of described first comparer and a normal phase input end of described second comparer, described first reference voltage end links to each other with a normal phase input end of described first comparer, and described second reference voltage end links to each other with an inverting input of described second comparer.
Preferably, one output terminal of described first comparer and an output terminal of described second comparer link to each other with two input ends described or door respectively, output terminal described or door links to each other the other end ground connection of described electric capacity with an end of described output signal end and described electric capacity.
Relative prior art, the utility model signal deteching circuit is converted to voltage signal by the rise and fall time with input signal, draws the rise and fall time of input signal, and circuit structure is simple and speed is very fast.
Description of drawings
Fig. 1 is the circuit diagram of the utility model signal deteching circuit better embodiment.
Fig. 2 is the circuit diagram of another embodiment of the utility model signal deteching circuit.
Embodiment
See also Fig. 1, the utility model signal deteching circuit better embodiment comprises an input signal end Vin, one first reference voltage end V1, one second reference voltage end V2, one first comparator C MP1, one second comparator C MP2, a logical device, a capacitor C and an output signal end Vout.In the present embodiment, this logical device be one with the door AND, this first comparator C MP1 and this second comparator C MP2 are high-speed comparator, have fast response characteristic.This first reference voltage end V1 is the minimum voltage input end of input signal end Vin input signal, and this second reference voltage end V2 is the ceiling voltage input end of input signal end Vin input signal.
The physical circuit annexation of the utility model signal deteching circuit better embodiment is as follows: this input signal end Vin links to each other with the normal phase input end of this first comparator C MP1 and the inverting input of this second comparator C MP2, this first reference voltage end V1 links to each other with the inverting input of this first comparator C MP1, this second reference voltage end V2 links to each other with the normal phase input end of this second comparator C MP2, the output end vo ut2 of the output end vo ut1 of this first comparator C MP1 and this second comparator C MP2 links to each other with two input ends of door AND with this respectively, should link to each other the other end ground connection of this capacitor C with an end of this output signal end Vout and this capacitor C with the output terminal of door AND.
The principle Analysis of the utility model signal deteching circuit better embodiment is as follows:
The low level signal of supposing this input signal end Vin input is VL, the high level signal of input is VH, the input voltage of this first reference voltage end V1 is VL+ (VH-VL) * 0.1, the input voltage of this second reference voltage end V2 is VH-(VH-VL) * 0.1, and this first reference voltage end V1 is the voltage input end of the input signal end Vin input signal amplitude of oscillation 10%, and this second reference voltage end V2 is the voltage input end of the input signal end Vin input signal amplitude of oscillation 90%.Wherein, concrete check point can be provided with as required.
When the voltage of this input signal end Vin input is lower than the voltage of this first reference voltage end V1 input, this output end vo ut1 output low level signal, this output end vo ut2 exports high level signal, this moment should with door AND output low level signal to this output signal end Vout; When the voltage of this input signal end Vin input is increased to the voltage of importing greater than this first reference voltage end V1 gradually, this output end vo ut1 and this output end vo ut2 all export high level signal, and should export high level signal to this output signal end Vout this moment with door AND; When the voltage of this input signal end Vin input is increased to the voltage of importing greater than this second reference voltage end V2, this output end vo ut1 exports high level signal, this output end vo ut2 output low level signal, this moment should with door AND output low level signal to this output signal end Vout.Promptly this output signal end Vout is high level at the voltage of this input signal end Vin input during greater than the voltage of this first reference voltage end V1 input and less than the voltage of this second reference voltage end V2 input only, all the other times are low level, when the rise and fall time of the voltage signal of this input signal end Vin input not simultaneously, the high level width of this output signal end Vout is also and then changing, and promptly the dutycycle of rise and fall time and this output signal end Vout output signal is proportional.Insert this capacitor C at this output signal end Vout and carry out filtering, thereby make one of this output signal end Vout output and the proportional constant voltage Vt of rise and fall time, suppose that scale-up factor is K, Vt=K*Tin then, wherein Tin is the rise and fall time of the voltage signal of this input signal end Vin input, thereby realized the rise and fall time of this input signal end Vin input signal is converted to magnitude of voltage, further obtained the function of the rise and fall time of input signal.
See also Fig. 2, Fig. 2 is the circuit diagram of another embodiment of the utility model signal deteching circuit.In another embodiment, this logical device be one or the door OR, all the other elements are all constant, but annexation difference, the physical circuit annexation is as follows: this input signal end Vin links to each other with the inverting input of this first comparator C MP1 and the normal phase input end of this second comparator C MP2, this first reference voltage end V1 links to each other with the normal phase input end of this first comparator C MP1, this second reference voltage end V2 links to each other with the inverting input of this second comparator C MP2, the output end vo ut2 of the output end vo ut1 of this first comparator C MP1 and this second comparator C MP2 respectively with this or the door OR two input ends link to each other, should or the door OR output terminal link to each other the other end ground connection of this capacitor C with an end of this output signal end Vout and this capacitor C.
The principle of work of another embodiment of the utility model signal deteching circuit is identical with the principle of work of signal deteching circuit better embodiment among Fig. 1, makes a concrete analysis of as follows:
When the voltage of this input signal end Vin input is lower than the voltage of this first reference voltage end V1 input, this output end vo ut1 exports high level signal, this output end vo ut2 output low level signal is somebody's turn to do this moment or door OR exports high level signal to this output signal end Vout; When the voltage of this input signal end Vin input is increased to the voltage of importing greater than this first reference voltage end V1 gradually, the equal output low level signal of this output end vo ut1 and this output end vo ut2, this moment should or door OR output low level signal to this output signal end Vout; When the voltage of this input signal end Vin input is increased to the voltage of importing greater than this second reference voltage end V2, this output end vo ut1 output low level signal, this output end vo ut2 exports high level signal, and should export high level signal to this output signal end Vout this moment with door AND.Promptly this output signal end Vout is low level at the voltage of this input signal end Vin input during greater than the voltage of this first reference voltage end V1 input and less than the voltage of this second reference voltage end V2 input only, all the other times are high level, when the rise and fall time of the voltage signal of this input signal end Vin input not simultaneously, the low level width of this output signal end Vout is also and then changing, and promptly the dutycycle of rise and fall time and this output signal end Vout output signal is proportional.Insert this capacitor C at this output signal end Vout and carry out filtering, thereby make one of this output signal end Vout output and the proportional constant voltage Vt of rise and fall time, suppose that scale-up factor is K, Vt=K*Tin then, wherein Tin is the rise and fall time of the voltage signal of this input signal end Vin input, thereby realized the rise and fall time of this input signal end Vin input signal is converted to magnitude of voltage, further obtained the function of the rise and fall time of input signal.
The utility model signal deteching circuit is converted to voltage signal by the rise and fall time with input signal, draws the rise and fall time of input signal, and circuit structure is simple and speed is very fast.
Claims (6)
1. signal deteching circuit, be used to detect the rise and fall time of an input voltage signal, it is characterized in that: described signal deteching circuit comprises one first reference voltage end, one second reference voltage end, one first comparer that links to each other with described first reference voltage end, one second comparer that links to each other with described second reference voltage end, one logical device that links to each other with described first comparer and described second comparer and an electric capacity that links to each other with described logical device, the described input voltage signal of the common reception of described first comparer and described second comparer, the minimum voltage input end that described first reference voltage end is an input voltage signal, the ceiling voltage input end that described second reference voltage end is an input voltage signal, the signal of described logical device output carry out the proportional constant voltage of rise and fall time of output one magnitude of voltage and input voltage signal after the filtering by described electric capacity.
2. signal deteching circuit as claimed in claim 1 is characterized in that: described signal deteching circuit comprises that also one is used for the input signal end and that input voltage signal inputs to described first comparer and described second comparer is used to export the output signal end of constant voltage.
3. signal deteching circuit as claimed in claim 2, it is characterized in that: described logical device be one with the door, described input signal end links to each other with a normal phase input end of described first comparer and an inverting input of described second comparer, described first reference voltage end links to each other with an inverting input of described first comparer, and described second reference voltage end links to each other with a normal phase input end of described second comparer.
4. signal deteching circuit as claimed in claim 3, it is characterized in that: an output terminal of described first comparer and an output terminal of described second comparer link to each other with two input ends of door with described respectively, describedly link to each other the other end ground connection of described electric capacity with an end of described output signal end and described electric capacity with the output terminal of door.
5. signal deteching circuit as claimed in claim 2, it is characterized in that: described logical device be one or the door, described input signal end links to each other with an inverting input of described first comparer and a normal phase input end of described second comparer, described first reference voltage end links to each other with a normal phase input end of described first comparer, and described second reference voltage end links to each other with an inverting input of described second comparer.
6. signal deteching circuit as claimed in claim 5, it is characterized in that: an output terminal of described first comparer and an output terminal of described second comparer link to each other with two input ends described or door respectively, output terminal described or door links to each other the other end ground connection of described electric capacity with an end of described output signal end and described electric capacity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202033730U CN202093098U (en) | 2011-06-16 | 2011-06-16 | Signal detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202033730U CN202093098U (en) | 2011-06-16 | 2011-06-16 | Signal detection circuit |
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| CN202093098U true CN202093098U (en) | 2011-12-28 |
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| CN2011202033730U Expired - Fee Related CN202093098U (en) | 2011-06-16 | 2011-06-16 | Signal detection circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102288835A (en) * | 2011-06-16 | 2011-12-21 | 四川和芯微电子股份有限公司 | Signal detection circuit and method |
| CN102590596A (en) * | 2012-03-09 | 2012-07-18 | 北京经纬恒润科技有限公司 | Circuit for detecting peak value of sine wave |
| CN102778610A (en) * | 2012-08-16 | 2012-11-14 | 漳州市东方智能仪表有限公司 | Pulse width measurement method and circuit |
| CN109474308A (en) * | 2018-12-19 | 2019-03-15 | 深圳易联凯科技有限公司 | A kind of signal demodulating system and method |
-
2011
- 2011-06-16 CN CN2011202033730U patent/CN202093098U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102288835A (en) * | 2011-06-16 | 2011-12-21 | 四川和芯微电子股份有限公司 | Signal detection circuit and method |
| CN102288835B (en) * | 2011-06-16 | 2013-06-19 | 四川和芯微电子股份有限公司 | Signal detection circuit and method |
| CN102590596A (en) * | 2012-03-09 | 2012-07-18 | 北京经纬恒润科技有限公司 | Circuit for detecting peak value of sine wave |
| CN102590596B (en) * | 2012-03-09 | 2014-06-04 | 北京经纬恒润科技有限公司 | Circuit for detecting peak value of sine wave |
| CN102778610A (en) * | 2012-08-16 | 2012-11-14 | 漳州市东方智能仪表有限公司 | Pulse width measurement method and circuit |
| CN109474308A (en) * | 2018-12-19 | 2019-03-15 | 深圳易联凯科技有限公司 | A kind of signal demodulating system and method |
| CN109474308B (en) * | 2018-12-19 | 2021-07-09 | 深圳易联凯科技有限公司 | Signal demodulation system and method |
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| C14 | Grant of patent or utility model | ||
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| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 610041 Sichuan city of Chengdu province high tech Zone Kyrgyzstan Road 33 block A No. 9 Patentee after: IPGoal Microelectronics (Sichuan) Co., Ltd. Address before: 402 room 7, building 610041, incubator Park, hi tech Zone, Sichuan, Chengdu Patentee before: IPGoal Microelectronics (Sichuan) Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111228 Termination date: 20140616 |
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| EXPY | Termination of patent right or utility model |