CN202084547U - Array substrate, liquid crystal plane and display equipment - Google Patents
Array substrate, liquid crystal plane and display equipment Download PDFInfo
- Publication number
- CN202084547U CN202084547U CN2011201844786U CN201120184478U CN202084547U CN 202084547 U CN202084547 U CN 202084547U CN 2011201844786 U CN2011201844786 U CN 2011201844786U CN 201120184478 U CN201120184478 U CN 201120184478U CN 202084547 U CN202084547 U CN 202084547U
- Authority
- CN
- China
- Prior art keywords
- array base
- base palte
- layer
- electrode
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Liquid Crystal (AREA)
Abstract
The utility model provides an array substrate. The array substrate comprises an underlay substrate, a common electrode, a grid line, a grid electrode, a grid insulation layer, an active layer, an N-type semiconductor layer, a source electrode, a drain electrode, a data wire layer, a passivated PVX layer, a pixel electrode, and a medium layer with a light reflecting function. The utility model also provides a liquid crystal plane employing the array substrate, and display equipment employing the liquid crystal plane. The array substrate, the liquid crystal plane and the display equipment can realize a semi-transmitting and semi-reflecting function; and the PVX layer can utilize surrounding lays to a certain degree, so that use of a back light source is reduced, the power consumption of a display component is reduced and the quality of a displayed picture can be improved.
Description
Technical field
The utility model relates to LCD (LCD) technical field, relates in particular to a kind of array base palte, liquid crystal panel and display device.
Background technology
Senior super dimension field switch technology (Advanced-Super Dimensional Switching; Be called for short: AD-SDS) the longitudinal electric field formation multi-dimensional electric field that produces of parallel electric field that is produced by pixel electrode edge in the same plane and pixel electrode layer and public electrode interlayer, make in the liquid crystal cell between pixel electrode, all aligned liquid-crystal molecules can both produce the rotation conversion directly over the electrode, thereby to have improved planar orientation be the liquid crystal operating efficiency and increased light transmission efficiency.Senior super dimension field switch technology can improve the TFT-LCD picture quality, has advantages such as high permeability, wide visual angle, high aperture, low aberration, low-response time, no water of compaction ripple (push Mura) ripple.
As shown in Figure 1, be the top plan view of the array base palte of AD-SDS pattern in the prior art,, obtain the cross-sectional view of the array base palte of AD-SDS pattern in the prior art as shown in Figure 2 along A-A direction cross section.The array base palte of prior art AD-SDS pattern comprises: public electrode 1, grid line and gate electrode 2, gate insulator 4, active layer 5, n type semiconductor layer 6, source-drain electrode and data line layer 7, passivation (PVX) layer 8 and pixel electrode 9.
Wherein, owing to need to load different signals between public electrode and the gate electrode, can not conducting between public electrode 1 and grid line and the gate electrode 2, therefore, existing technology is during by mask (mask) manufacturing figure, with this two-layer disconnection.
The longitudinal electric field that the pixel electrode edge is produced in the same plane parallel electric field and pixel electrode layer and public electrode interlayer produce of passing through of the array base palte of AD-SDS pattern forms multi-dimensional electric field in the prior art, make in the liquid crystal cell between pixel electrode, all aligned liquid-crystal molecules can both fully rotate directly over the electrode, thereby improved the liquid crystal operating efficiency, increased light transmission efficiency.
But the array base palte of AD-SDS pattern of the prior art provides light source to show by backlight often, is difficult to realize half-transmitting and half-reflecting.And if realize then can utilizing the light in the surrounding environment to a certain extent by half-transmitting and half-reflecting, thereby minimizing reduces the power consumption of display device to the use of backlight; Simultaneously, also can improve the display frame quality.
The utility model content
For addressing the above problem, the utility model embodiment provides a kind of array base palte, liquid crystal panel and display device, can realize half-transmitting and half-reflecting.
The utility model embodiment provides a kind of array base palte, comprising: underlay substrate, grid line and gate electrode, gate insulator, active layer, n type semiconductor layer, source-drain electrode and data line layer, passivation layer and pixel electrode; This array base palte also comprises: the dielectric layer with reflection action.
Wherein, described dielectric layer is between passivation layer and gate insulator.
Wherein, described dielectric layer is between underlay substrate and gate insulator.
Further, this array base palte also comprises: be positioned at the public electrode on the underlay substrate;
Described dielectric layer is between public electrode and underlay substrate.
Further, this array base palte also comprises: be positioned at the public electrode on the underlay substrate;
Described dielectric layer is between public electrode and gate insulator.
Wherein, described dielectric layer and the same one deck of described source-drain electrode, and described dielectric layer and described source-drain electrode adopt same material to be made.
Wherein, this array base palte also comprises the public electrode that is positioned on the underlay substrate, and described public electrode and described dielectric layer are positioned at same one deck, and are formed by same material, and this material is light tight metal, and described public electrode is the public electrode with gap structure.
Wherein, described dielectric layer is a metal level.
Wherein, described metal level is the strip metal layer.
Wherein, described metal level is by neodymium aluminium, aluminium, copper, molybdenum, tungsten molybdenum or chromium one or more monofilms that constitute or composite membrane wherein.
The utility model embodiment also provides a kind of liquid crystal panel, comprise color membrane substrates, array base palte and be filled in color membrane substrates and array base palte between liquid crystal, described array base palte is above-mentioned array base palte.
The utility model embodiment also provides a kind of display device, comprises above-mentioned liquid crystal panel.
The utility model embodiment by the dielectric layer with reflection action that is provided with on the underlay substrate in array base palte, thereby has realized a kind of array base palte of half-transmission half-reflection type.Realize half-transmitting and half-reflecting, utilized the light in the surrounding environment to a certain extent, thereby reduce use, reduced the power consumption of display device, also can provide the display frame quality simultaneously backlight.
Description of drawings
Fig. 1 is the top plan view of array base palte in the prior art;
Fig. 2 is the cross-sectional view along the resulting prior art array base palte in A-A direction shown in Figure 1 cross section;
The top plan view of the array base palte that Fig. 3 provides for the utility model embodiment;
Fig. 4 is the cross-sectional view along A-A direction shown in Figure 3 cross section resulting the utility model embodiment array base palte;
The top plan view of the array base palte behind the formation public electrode that Fig. 5 provides for the utility model embodiment;
Formation grid line that Fig. 6 provides for the utility model embodiment and gate electrode and have the dielectric layer of reflection action after the top plan view of array base palte;
Fig. 7 is for the formation grid line that provides along the resulting the utility model embodiment in A-A direction shown in Figure 6 cross section and gate electrode with the cross-sectional view of the array base palte after having the dielectric layer of reflection action;
The formation source-drain electrode that Fig. 8 provides for the utility model embodiment and the top plan view of the array base palte behind the data wire;
The formation source-drain electrode that provides along the resulting the utility model embodiment in A-A direction shown in Figure 8 cross section and the cross-sectional view of the array base palte behind the data wire are provided Fig. 9;
The top plan view of the array base palte behind the formation PVX layer that Figure 10 provides for the utility model embodiment;
The cross-sectional view of the array base palte of Figure 11 after for the formation PVX layer that provides along the resulting the utility model embodiment in A-A direction shown in Figure 10 cross section;
Figure 12 for the utility model embodiment provide when public electrode be positioned at dielectric layer with reflection action above the time, the cross-sectional view of the array base palte behind the resulting formation in the A-A direction shown in Figure 10 cross section PVX layer;
Figure 13 is the cross-sectional view of the array base palte of TN pattern of the prior art.
Embodiment
The utility model embodiment provides a kind of array base palte, in order to realize the array base palte of half-transmission half-reflection type.
The utility model embodiment provides the structure of TFT-LCD substrate, this TFT-LCD substrate comprises grid line and data wire, grid line and data wire define pixel region, and at infall formation thin-film transistor, the drain electrode of the thin-film transistor pixel electrode interior with being formed on pixel region is connected, and public electrode is the bottom transparency electrode.
Provide specifying of each embodiment of the utility model below in conjunction with accompanying drawing.
Embodiment one:
The utility model embodiment is characterised in that: the common electrode layer of the AD-SDS pattern array substrate that present embodiment provides is formed by transparent electrode material, on transparent common electrode, form and the corresponding opaque strip metal bar of strip pixel electrode, this opaque metal bar has reflection action, thereby makes array base palte have the effect of half reflection and half transmission.
Referring to Fig. 3 and Fig. 4, the utility model provides a kind of array base palte of AD-SDS active driving TFT, comprising: public electrode 1, grid line and gate electrode 2, strip opaque metal layer 3, gate insulator 4, active layer 5, n type semiconductor layer 6, source-drain electrode and data line layer 7, passivation layer (being the PVX layer) 8 and pixel electrode 9.Wherein, pixel electrode 9 can be pectination or other shapes.
Wherein, public electrode 1 is a transparent electrode material, forms and strip pixel electrode 9 corresponding strip opaque metal bars on transparent public electrode 1, promptly forms metal level 3, and this metal level 3 has reflection action.
Described grid line and gate electrode 2 are the monofilm that is made of neodymium aluminium (AlNd), aluminium (Al), copper (Cu), molybdenum (Mo), tungsten molybdenum (MoW) or chromium (Cr);
Perhaps, described grid line and gate electrode 2 are the composite membrane that comprises following one or more materials:
AlNd、Al、Cu、Mo、MoW、Cr。
Described metal level 3 is the monofilm that is made of neodymium aluminium (AlNd), aluminium (Al), copper (Cu), molybdenum (Mo), tungsten molybdenum (MoW) or chromium (Cr);
Perhaps, described metal level 3 is the composite membrane that comprises following one or more materials:
AlNd、Al、Cu、Mo、MoW、Cr。
Described gate insulator 4 is the monofilm that is made of silicon nitride (SiNx), silica (SiOx) or silicon oxynitride (SiOxNy);
Perhaps, described gate insulator 4 is the composite membrane that comprises following one or more materials:
SiNx、SiOx、SiOxNy。
Described source-drain electrode 7 is the monofilm by Mo, MoW or Cr;
Perhaps, described source-drain electrode 7 is the composite membrane that comprises following one or more materials:
Mo、MoW、Cr。
Described public electrode 1 is the monofilm that is made of indium zinc oxide (ITO) or indium-zinc oxide (IZO), the perhaps composite membrane for being made of ITO and IZO.
Described pixel electrode 9 is the monofilm that is made of indium zinc oxide (ITO) or indium-zinc oxide (IZO), the perhaps composite membrane for being made of ITO and IZO.
Introduce a kind of manufacturing process that can be used for making described array base palte below, comprising:
Step 1: deposit ito thin film on underlay substrate 0, form public electrode 1 by mask and etching technics, the top plan view that has formed the array base palte after the public electrode 1 as shown in Figure 5; Wherein, underlay substrate can be glass substrate, transparent plastic base or other suitable substrates.
Step 2: as shown in Figure 6 and Figure 7, depositing metal layers on the array base palte of completing steps one, by mask and etching technics, form grid line and gate electrode 2 and strip opaque metal layer 3 simultaneously, wherein strip opaque metal layer 3 cover ITO public electrode 1 above;
Step 3: as Fig. 8 and shown in Figure 9, deposit gate insulator 4, active layer 5, n type semiconductor layer 6 on the array base palte of above-mentioned technology successively and metal level is leaked in the source finishing,, form source-drain electrode and data wire 7 by mask and etching technics;
Step 4: shown in Figure 10 and 11, finish above-mentioned technology after, deposit PVX layer 8 again, in the drain electrode of array base palte, form via hole by mask and etching technics.
Step 5: at last on aforesaid substrate by mask and etching technics, form pixel electrode 9, by via hole drain electrode is linked to each other with pixel electrode 9.
Embodiment two:
Be with the difference of embodiment one: public electrode 1 be positioned at strip opaque metal layer 3 above, the profile of the array base palte of formation is as shown in figure 12.
Half-transmitting and half-reflecting described in each embodiment of the utility model, the light that just is meant the position that does not have lighttight metal level 3 on the array base palte is to be provided by backlight, the light that the position of metal level 3 is arranged is to be provided through metal level 3 reflections by ambient light.And, under the high light environment, use the display unit of this array base palte can close backlight, directly utilize the reverberation of reflecting part to realize showing.
Embodiment three:
Be with the difference of embodiment one: strip opaque metal layer 3 is to leak metal by the source to carry out the independently metal strip structure that forms after the mask etching technology, has reflective effect, that is to say, strip opaque metal layer 3 forms simultaneously with source-drain electrode 7, and strip opaque metal layer 3 is to adopt same material to be made with source-drain electrode 7, and strip opaque metal layer 3 is between PVX layer 8 and gate insulator 4.Be that described dielectric layer is positioned at the same one deck of source leakage metal level, leak metal by the source and be made.
Embodiment four:
Be with embodiment one and two difference: the last or following metal level 3 that do not cover of public electrode 1, but public electrode 1 adopts light tight metal material, by mask etching technology, form slit (Slit) structure of strip, slit transmission by strip backlight is come, and the light in the environment can reflect by the lighttight public electrode 1 in other zones outside the slit.That is, this array base palte comprises the public electrode 1 that is positioned on the underlay substrate 0, and described public electrode 1 is positioned at same one deck with described metal level 3, and is formed by same material, and this material is light tight metal, and described public electrode 1 is for having the public electrode of gap structure.
Embodiment five:
As shown in figure 13, be the profile of the array base palte of prior art TN general mode, the array base palte of TN pattern does not have public electrode, and pixel electrode 9 is not a strip, and pixel electrode 9 forms electric field with public electrode 1 on the color membrane substrates.
The array base palte of TN pattern also can be realized half-transmitting and half-reflecting by opaque strip metal layer is set.Such as, strip opaque metal layer 3 can be between underlay substrate 0 and gate insulator 4, and strip opaque metal layer 3 forms simultaneously with grid line and gate electrode 2.
Perhaps, strip opaque metal layer 3 is positioned between gate insulator 4 and the passivation layer (PVX) 8, forms simultaneously with source-drain electrode and data wire 7.
That is to say, in the array base palte that the utility model embodiment provides, strip opaque metal layer 3 can form simultaneously with grid line and gate electrode 2, also can form simultaneously with source-drain electrode and data wire 7, therefore need not increases masking process at strip opaque metal layer 3 separately, therefore is easier to realize.
The metal level 3 that each embodiment of the utility model mentions can be realized by other materials in fact, is not to be defined in metal, and these materials can unify to be summarised as dielectric layer 3.This shows, the array base palte that the utility model embodiment provides, comprise: underlay substrate, grid line and gate electrode, gate insulator, active layer, n type semiconductor layer, source-drain electrode and data line layer, PVX layer and pixel electrode, wherein, underlay substrate can be glass substrate, transparent plastic base or other suitable substrates.
This array base palte also comprises:
The dielectric layer that on underlay substrate, is provided with reflection action.
Preferably, this array base palte also comprises: be positioned at the public electrode on the underlay substrate; Described dielectric layer is between public electrode and underlay substrate.
Perhaps, this array base palte also comprises: be positioned at the public electrode on the underlay substrate; Described dielectric layer is between public electrode and gate insulator.
Perhaps, described dielectric layer is between PVX layer and gate insulator.
Perhaps, described dielectric layer is between underlay substrate and gate insulator.
Preferably, described dielectric layer is a metal level.
And described metal level can be the strip metal layer.Certainly, also the metal level of other shapes can be, not necessarily the metal level of strip will be.
Described metal level is the monofilm that is made of neodymium aluminium (AlNd), aluminium (Al), copper (Cu), molybdenum (Mo), tungsten molybdenum (MoW) or chromium (Cr);
Perhaps, described metal level is the composite membrane that comprises following one or more materials:
AlNd、Al、Cu、Mo、MoW、Cr。
Described gate insulator is the monofilm that is made of silicon nitride (SiNx), silica (SiOx) or silicon oxynitride (SiOxNy);
Perhaps, described gate insulator is the composite membrane that comprises following one or more materials:
SiNx、SiOx、SiOxNy。
Preferably, described pixel electrode is the monofilm that is made of indium zinc oxide (ITO) or indium-zinc oxide (IZO);
Perhaps, described pixel electrode is the composite membrane that is made of ITO and IZO.
In the utility model the foregoing description, exemplified the array base palte of AD-SDS and TN pattern,, be suitable for the realization half-transmitting and half-reflecting technical scheme that the utility model embodiment provides equally for other pattern array substrates.
Embodiment six:
The utility model embodiment provides a kind of liquid crystal panel, comprise color membrane substrates, array base palte and be filled in color membrane substrates and array base palte between liquid crystal, described array base palte is above-mentioned array base palte.Owing to adopted above-mentioned array base palte, can realize half-transmitting and half-reflecting.
Embodiment seven:
A kind of display device that the utility model embodiment provides comprises above-mentioned liquid crystal panel.Described display device can be LCD TV, monitor, notebook computer, panel computer, PDA, mobile phone, music player etc.Described display device can be realized half-transmitting and half-reflecting owing to adopted above-mentioned liquid crystal panel.
Array base palte, liquid crystal panel and display device that each embodiment of the utility model provides, realized half-transmitting and half-reflecting, utilized the light in the surrounding environment to a certain extent, thereby reduced use backlight, reduce the power consumption of display device, improved the display frame quality simultaneously.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these are revised and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these changes and modification interior.
Claims (12)
1. array base palte, comprising: underlay substrate, grid line and gate electrode, gate insulator, active layer, n type semiconductor layer, source-drain electrode and data line layer, passivation layer and pixel electrode is characterized in that this array base palte also comprises:
Dielectric layer with reflection action.
2. array base palte according to claim 1 is characterized in that described dielectric layer is between passivation layer and gate insulator.
3. array base palte according to claim 1 is characterized in that described dielectric layer is between underlay substrate and gate insulator.
4. array base palte according to claim 1 is characterized in that, this array base palte also comprises: be positioned at the public electrode on the underlay substrate;
Described dielectric layer is between public electrode and underlay substrate.
5. array base palte according to claim 1 is characterized in that, this array base palte also comprises: be positioned at the public electrode on the underlay substrate;
Described dielectric layer is between public electrode and gate insulator.
6. array base palte according to claim 1 is characterized in that, described dielectric layer and the same one deck of described source-drain electrode, and described dielectric layer and described source-drain electrode adopt same material to be made.
7. array base palte according to claim 1, it is characterized in that, this array base palte also comprises the public electrode that is positioned on the underlay substrate, described public electrode and described dielectric layer are positioned at same one deck, and form by same material, this material is light tight metal, and described public electrode is the public electrode with gap structure.
8. according to each described array base palte of claim 1～7, it is characterized in that described dielectric layer is a metal level.
9. array base palte according to claim 8 is characterized in that, described metal level is the strip metal layer.
10. array base palte according to claim 8 is characterized in that, described metal level is by neodymium aluminium, aluminium, copper, molybdenum, tungsten molybdenum or chromium one or more monofilms that constitute or composite membrane wherein.
11. a liquid crystal panel, comprise color membrane substrates, array base palte and be filled in color membrane substrates and array base palte between liquid crystal, it is characterized in that described array base palte is each described array base palte of claim 1～10.
12. a display device is characterized in that, comprises the described liquid crystal panel of claim 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201844786U CN202084547U (en) | 2011-06-02 | 2011-06-02 | Array substrate, liquid crystal plane and display equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201844786U CN202084547U (en) | 2011-06-02 | 2011-06-02 | Array substrate, liquid crystal plane and display equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202084547U true CN202084547U (en) | 2011-12-21 |
Family
ID=45345169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011201844786U Expired - Lifetime CN202084547U (en) | 2011-06-02 | 2011-06-02 | Array substrate, liquid crystal plane and display equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202084547U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013127236A1 (en) * | 2012-02-28 | 2013-09-06 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor and display device |
| CN103760721A (en) * | 2014-01-08 | 2014-04-30 | 北京京东方光电科技有限公司 | Thin film transistor array substrate, preparation method for same and display device of thin film transistor array substrate |
-
2011
- 2011-06-02 CN CN2011201844786U patent/CN202084547U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013127236A1 (en) * | 2012-02-28 | 2013-09-06 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor and display device |
| CN103760721A (en) * | 2014-01-08 | 2014-04-30 | 北京京东方光电科技有限公司 | Thin film transistor array substrate, preparation method for same and display device of thin film transistor array substrate |
| WO2015103826A1 (en) * | 2014-01-08 | 2015-07-16 | 京东方科技集团股份有限公司 | Thin-film transistor array substrate and preparation method therefor, and display device |
| US10128272B2 (en) | 2014-01-08 | 2018-11-13 | Boe Technology Group Co., Ltd. | Thin film transistor array substrate, method for fabricating the same and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102645803B (en) | Pixel unit, array substrate, liquid crystal panel, display device and manufacturing methods thereof | |
| CN102681276B (en) | Array substrate, method for manufacturing same and display device comprising same | |
| US9054195B2 (en) | Array substrate, method for fabricating the same, and display device | |
| CN102629577B (en) | TFT array substrate and manufacturing method thereof and display device | |
| US20180321562A1 (en) | Boa liquid crystal display panel and manufacturing method thereof | |
| CN103268878B (en) | The manufacture method of tft array substrate, tft array substrate and display unit | |
| CN102629606B (en) | Array substrate and preparation method thereof and display device | |
| US10217778B2 (en) | Array substrate and manufacturing method thereof | |
| CN103226272B (en) | Array substrate and preparation method thereof, and display device | |
| CN102709237B (en) | Thin-film transistor array substrate and manufacturing method and electronic devices thereof | |
| CN102654703B (en) | Array substrate and manufacturing method thereof as well as display equipment | |
| CN102881688A (en) | Array substrate, display panel and array substrate manufacturing method | |
| TWI487120B (en) | Thin film transistor substrate and display device comprising the same | |
| CN103439840A (en) | Array substrate, display device and method for manufacturing array substrate | |
| CN102969311B (en) | Array substrate and manufacturing method thereof, and display device | |
| CN104835782A (en) | Array substrate, manufacturing method of array substrate and display device | |
| CN101561594B (en) | Array basal plate of FFS mode display device and production method thereof | |
| CN105448824A (en) | Array substrate and manufacturing method thereof as well as display device | |
| CN103018977A (en) | Array substrate and manufacture method thereof | |
| US10403761B2 (en) | Array substrate and manufacturing method thereof, and display device | |
| CN202421681U (en) | Pixel unit, array substrate, liquid crystal panel and display device | |
| CN104538412A (en) | Array substrate and production method thereof and display device | |
| CN103700663A (en) | Array substrate and manufacturing method thereof, and display device | |
| CN103456747A (en) | Array substrate, manufacturing method of array substrate and display device | |
| CN102854681B (en) | The manufacture method of a kind of array base palte, display device and array base palte |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150707 Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150707 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150707 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE Technology Group Co., Ltd. Patentee after: Beijing BOE Photoelectricity Science & Technology Co., Ltd. Address before: 100176 Beijing city in Western Daxing District economic and Technological Development Zone, Road No. 8 Patentee before: Beijing BOE Photoelectricity Science & Technology Co., Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20111221 |