CN202075971U - DDC interface isolation protection circuit - Google Patents
DDC interface isolation protection circuit Download PDFInfo
- Publication number
- CN202075971U CN202075971U CN2011201137060U CN201120113706U CN202075971U CN 202075971 U CN202075971 U CN 202075971U CN 2011201137060 U CN2011201137060 U CN 2011201137060U CN 201120113706 U CN201120113706 U CN 201120113706U CN 202075971 U CN202075971 U CN 202075971U
- Authority
- CN
- China
- Prior art keywords
- interface
- video signal
- receiving apparatus
- ddc
- signal receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The utility model relates to a video signal interface circuit, and discloses a DDC interface isolation protection circuit. Each signal line between the DDC interface at the video signal interface and the 12C interface of the E-EDID information storage body of video reception equipment is connected with a bidirectional isolator; the bidirectional isolator is connected with a pull-up resistor; the E-EDID information storage body of video reception equipment is connected with a pull-up resistor; each signal line between the 12C interface of the E-EDID information storage body of video reception equipment and the 12C interface of the local control core of video reception equipment is connected with a bidirectional isolator; and the local control core of video reception equipment is connected with a pull-down resistor and a field effect transistor. In the utility model, a protection circuit is added to guarantee that no conflict happens among different circuit portions on electrical characteristics and data read-write operations; data is prevented to be lost; and maintenance is convenient.
Description
Technical field
The utility model relates to a kind of video signal interface circuit, relates in particular to a kind of DDC interface isolation protective circuit.
Background technology
The DDC interface is a main flow video interface now, a sub-interface that must comprise such as interfaces such as DVI, VGA.That is to say that aforementioned video interface except the main channel that comprises a transmission video signal, also needs to comprise a subchannel, is used for transmitting the DDC signal, they are encapsulated in same cable, the same plug.By the DDC interface, signal source is such as video card, can and signal receiver, such as display, do two-way data interaction, by this mutual, signal source can be known the detailed configuration information of receiving equipment, thereby output is fit to the vision signal that receiving equipment shows demand.
For the existing video signal receiving equipment, the general using method of DDC interface is: on the DDC of each input interface interface, connect a non-volatile erasable memory bank of the serial based on 8 I2C buses, such as 24C02.In this memory bank, according to the form of VESA international standard defined, stored the details of receiving equipment, mainly comprise information such as the video signal format that can receive, display model, this formative information is referred to as E-EDID information.
As can be seen, widely used now, DDC based on simple connection realizes, problems are arranged: owing to just simply connected a memory bank on the DDC interface, E-EDID information can only be when video reception apparatus dispatches from the factory, write by external unit, receiving equipment can't oneself upgrade its content, can't upgrade.The non-volatile erasable memory bank of this serial based on the E2 technology of 24C02 is easy to obliterated data under external interference, based on previous reasons, receiving equipment can't recover E-EDID information, in case lose, can only depot repair, maintenance cost is too high.The video interface line is directly connected to memory bank, external interference, and video comes from the signal pressure reduction of video reception apparatus, all might impact to memory bank, causes loss of data.
The utility model content
The purpose of this utility model is to provide a kind of DDC interface isolation protective circuit; thereby on the basis of original function; increase the access function of the local control of video signal receiving apparatus core to the E-EDID storage medium; increased holding circuit simultaneously; guarantee between the each several part circuit, on electrical specification, do not have conflict, also do not have conflict on the data read-write operation; the data that prevent loss are convenient to maintenance.
In order to achieve the above object, the utility model has following technical scheme:
A kind of DDC interface isolation protective circuit of the present utility model, on the every signal line between the I2C interface of DDC interface on the video signal input interface and video signal receiving apparatus E-EDID storage medium, be connected with bidirectional isolator, this bidirectional isolator is connected with pull-up resistor, and described video signal receiving apparatus E-EDID storage medium is connected with pull-up resistor; On the every signal line between the I2C interface of the I2C interface of video signal receiving apparatus E-EDID storage medium and the local control of video signal receiving apparatus core, be connected with bidirectional isolator, the local control of described video signal receiving apparatus core is connected with pull down resistor and field effect transistor; Above-mentioned bidirectional isolator all is subjected to the local control of video signal receiving apparatus control core, wherein, the signal source that video signal input interface connected and this locality of video signal receiving apparatus control core, can both remove the E-EDID storage medium of accessing video signal receiver as active devices.
Wherein, described bidirectional isolator is is oppositely connected and composed by two NMOS field effect transistor; The grid of two NMOS field effect transistor links together.
Wherein, the signal source that described video signal input interface connected, these two active devices of this locality control core with video signal receiving apparatus at one time, can only have one to have access to the E-EDID storage medium; The switching of access right is controlled by this locality control core of video signal receiving apparatus.
Advantage of the present utility model is:
The utility model is on the basis of original function; increase the access function of the local control of video signal receiving apparatus core to the E-EDID storage medium; increased holding circuit simultaneously; guarantee between the each several part circuit; on electrical specification, do not have conflict; also do not have conflict on the data read-write operation, the data that prevent loss are convenient to maintenance.
Description of drawings
Fig. 1 is circuit theory diagrams of the present utility model.
Among the figure: 1.PC machine, 2. video card, 3. video signal cable, 4. display, 5. video input interface, 6. plate carries the control core, the U1.E-EDID storage medium, R1, R2, R3. pull-up resistor, R4. pull down resistor, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9.NMOS field effect transistor.
Embodiment
Following examples are used to illustrate the utility model, but are not used for limiting scope of the present utility model.
Referring to Fig. 1; generally speaking; video transmission all has a video source; a receiver; in a kind of DDC interface isolation protective circuit of the present utility model; as video signal source, display 4 illustrates the function of this buffer circuit and function mode as signal receiver with the video card in the standard PC 12 for we.
DDC interface on the video input interface 5 comprises signal wire DDC_SCL and DDC_SDA, respectively by the I2C interface of a bidirectional isolator and E-EDID storage medium U1, comprises that pin SCL, SDA connect.Isolator between signal wire DDC_SCL and the SCL is is oppositely connected and composed by NMOS field effect transistor Q1, Q2, and the isolator between signal wire DDC_SDA and the SDA is made of NMOS field effect transistor Q5, Q6.The grid of 4 NMOS field effect transistor Q1, Q2, Q5, Q6 links together, draw high+5V by pull-up resistor R3, make these 4 NMOS field effect transistor Q1, Q2, Q5, Q6 be defaulted as unlatching, that is to say, under the normality, signal wire DDC_SCL and SCL, and be communicated with between signal wire DDC_SDA and the SDA.
Pin SCL, the SDA of E-EDID storage medium (U1) are drawn high+5V by pull-up resistor R1, R2, allow the I2C interface signal of E-EDID storage medium U1 keep high level under normal conditions, just idle level.In the open/close of short duration process of isolator, these two pull-up resistors can be guaranteed abnormality can not occur on the E-EDID storage medium U1.
Pin SCL, the SDA of E-EDID storage medium U1 carry the I2C interface of control core 6 (the local control of video signal receiving apparatus core) respectively by a bidirectional isolator and plate, comprise signal wire MCU_SCL and MCU_SDA and link together.Wherein, the isolator between pin SCL and the MCU_SCL is is oppositely connected and composed by NMOS field effect transistor Q3, Q4, and the isolator between pin SDA and the MCU_SDA is made of NMOS field effect transistor Q7, Q8.The grid of 4 NMOS field effect transistor Q3, Q4, Q7, Q8 links together, R4 pulls down to ground level by pull down resistor, make these 4 NMOS field effect transistor Q3, Q4, Q7, Q8 be defaulted as and close, that is to say, under the normality, pin SCL and MCU_SCL, and disconnect between pin SDA and the MCU_SDA.
Plate carries the grid that the signal wire DDC_CTRL that controls core 6 is connected to 4 NMOS field effect transistor Q3, Q4, Q7, Q8.Under the normality, signal wire DDC_CTRL is output voltage not, or output LOW voltage, makes 4 NMOS field effect transistor Q3, Q4, Q7, Q8 keep closing.Signal wire DDC_CTRL connects the grid of NMOS field effect transistor Q9 simultaneously, the source ground of NMOS field effect transistor Q9, and drain electrode connects the grid of 4 NMOS field effect transistor Q1, Q2, Q5, Q6.Under the normality, because signal wire DDC_CTRL output voltage not, or output LOW voltage, NMOS field effect transistor Q9 keeps closed condition, and the grid voltage of 4 NMOS field effect transistor Q1, Q2, Q5, Q6 is not had influence.
When plate carries control core 6 needs visit E-EDID storage medium U1, want earlier signal wire DDC_CTRL to be drawn high, 4 NMOS field effect transistor Q3, Q4, Q7, Q8 are opened, be communicated with pin SCL and MCU_SCL respectively, and SDA and MCU_SDA.Simultaneously, NMOS field effect transistor Q9 conducting is pulled down to ground level with the grid of 4 NMOS field effect transistor Q1, Q2, Q5, Q6, makes these 4 NMOS field effect transistor Q1, Q2, Q5, Q6 close cut-off signal line DDC_SCL and SCL, and DDC_SDA and SDA.After plate carried the visit end of 6 pairs of E-EDID storage mediums of control core U1, plate carries control core 6 wanted degrade signal line DDC_CTRL, and connected state is returned to normal.
As mentioned above, just can realize the utility model comparatively fully.The above only is a comparatively reasonably embodiment of the present utility model; protection domain of the present utility model includes but are not limited to: this, and any the including at the utility model based on unsubstantiality sex change change on the technical solutions of the utility model of those skilled in the art comprises within the scope.
Claims (3)
1. DDC interface isolation protective circuit, it is characterized in that: on the every signal line between the I2C interface of DDC interface on the video signal input interface and video signal receiving apparatus E-EDID storage medium, be connected with bidirectional isolator, this bidirectional isolator is connected with pull-up resistor, and described video signal receiving apparatus E-EDID storage medium is connected with pull-up resistor; On the every signal line between the I2C interface of the I2C interface of video signal receiving apparatus E-EDID storage medium and the local control of video signal receiving apparatus core, be connected with bidirectional isolator, the local control of described video signal receiving apparatus core is connected with pull down resistor and field effect transistor; Above-mentioned bidirectional isolator all is subjected to the local control of video signal receiving apparatus control core, wherein, the signal source that video signal input interface connected and this locality of video signal receiving apparatus control core, can both remove the E-EDID storage medium of accessing video signal receiver as active devices.
2. a kind of DDC interface isolation protective circuit according to claim 1, it is characterized in that: described bidirectional isolator is is oppositely connected and composed by two NMOS field effect transistor; The grid of two NMOS field effect transistor links together.
3. a kind of DDC interface isolation protective circuit according to claim 1, it is characterized in that: the signal source that described video signal input interface connected, these two active devices of this locality control core with video signal receiving apparatus, at one time, can only there be one to have access to the E-EDID storage medium; The switching of access right is controlled by this locality control core of video signal receiving apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201137060U CN202075971U (en) | 2011-04-18 | 2011-04-18 | DDC interface isolation protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201137060U CN202075971U (en) | 2011-04-18 | 2011-04-18 | DDC interface isolation protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202075971U true CN202075971U (en) | 2011-12-14 |
Family
ID=45114064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011201137060U Expired - Lifetime CN202075971U (en) | 2011-04-18 | 2011-04-18 | DDC interface isolation protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202075971U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194436A (en) * | 2011-04-18 | 2011-09-21 | 北京彩讯科技股份有限公司 | Insulation protective circuit for DDC (Direct Digital Control) interface |
-
2011
- 2011-04-18 CN CN2011201137060U patent/CN202075971U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194436A (en) * | 2011-04-18 | 2011-09-21 | 北京彩讯科技股份有限公司 | Insulation protective circuit for DDC (Direct Digital Control) interface |
| CN102194436B (en) * | 2011-04-18 | 2015-09-16 | 北京彩讯科技股份有限公司 | DDC interface isolation protective circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102194436B (en) | DDC interface isolation protective circuit | |
| US20100109795A1 (en) | Transmission of alternative content over standard device connectors | |
| US20110068736A1 (en) | Power charging of mobile devices | |
| CN109683836B (en) | Driving device compatible with hardware interfaces of various display protocols | |
| KR20120099881A (en) | Image processing apparatus and control method thereof | |
| CN103595943A (en) | Video signal transmission equipment, playing system and video signal transmission method | |
| CN107341120B (en) | Multi-input interface compatible device and method for virtual reality equipment | |
| CN104834619B (en) | A kind of I2C bus circuit, implementation method and electronic equipment | |
| US11216213B2 (en) | Transmission apparatus, method of controlling transmission apparatus, and cable | |
| CN104967806B (en) | Switching circuit based on HDMI | |
| CN202026431U (en) | Debugging device and debugging system | |
| CN201655249U (en) | Integrated audio/video controller for LED display | |
| CN205195849U (en) | Signal transmission circuit | |
| CN202075971U (en) | DDC interface isolation protection circuit | |
| CN102880273A (en) | Display equipment and method for supplying power to external equipment | |
| CN103517139B (en) | A kind of TV with hardware configuration upgrade function | |
| US20200280757A1 (en) | Cable, method of controlling cable, connection device, electronic device, and method of controlling electronic device | |
| CN108024129A (en) | Display device and its mainboard | |
| CN205068361U (en) | Computer extender | |
| CN201499263U (en) | Single-fiber single-wavelength 1080P VOOP | |
| CN204705767U (en) | A kind of head mounted display | |
| CN102541783B (en) | Timing simulation system and method | |
| CN204810421U (en) | Switching circuit based on HDMI interface | |
| CN204270282U (en) | A kind of KVM access device with VGA split screen function | |
| CN203522918U (en) | HDMI-to-PCIE acquisition card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 100094, Room 301, building 8, Zhongguancun Software Park, 8 northeast Wang Xi Road, Beijing, Haidian District Patentee after: Beijing Triolion Science & Technology Co., Ltd. Address before: 100085, room 1009, building 10, block C, Jinyu Ka Wah building, No. 9, 3rd Street, Haidian District, Beijing Patentee before: Beijing Triolion Science & Technology Co., Ltd. |
|
| CX01 | Expiry of patent term |
Granted publication date: 20111214 |
|
| CX01 | Expiry of patent term |