CN202059440U - Device for realizing clock format conversion - Google Patents
Device for realizing clock format conversion Download PDFInfo
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- CN202059440U CN202059440U CN 201120184344 CN201120184344U CN202059440U CN 202059440 U CN202059440 U CN 202059440U CN 201120184344 CN201120184344 CN 201120184344 CN 201120184344 U CN201120184344 U CN 201120184344U CN 202059440 U CN202059440 U CN 202059440U
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Abstract
The utility model relates to a device for realizing clock format conversion. The device comprises a network interface module, a protocol processing module, a clock conversion module and a driving circuit, wherein a data packet containing clock information is received from Ethernet by the network interface module; the data packet containing clock information from Ethernet is input to the protocol processing module and then analyzed and processed by the protocol processing module according to the IEEE1588 protocol to obtain the clock information, and the clock information is provided to the clock conversion module; the clock information is converted into a synchronous clock in an IRIG-B format or pulse output format by a clock generation module in the clock conversion module, and the synchronous clock is converted to a physical signal for transmission by the driving circuit in the clock conversion module; as the device is compatible to the terminal equipment in the primal system, the investment on the primary network is protected; as a large amount of synchronous clock interfaces can be provided, the demand of a large amount of terminal equipment for synchronous clocks in the industrial site is met.
Description
Technical field
The utility model relates to a kind of device of realizing the clock format conversion, particularly relates to the device that realization is converted to the temporal information of I EEE1588 form multiple clock information form.
Background technology
Raising along with industrial circle system information level, transfer of data, operation control need at a high speed, the network environment of high bandwidth, and original low speed data transmission system, can not satisfy the requirement of information system as data transmission system to data transmission bauds, bandwidth and fail safe based on CAN bus, universal serial bus etc., therefore, ethernet technology as a kind of maturation, at a high speed, lower-cost network technology becomes the selection of industry naturally.
The terminal of industrial information network has automation equipment, protective device, supervisory control system and the control device of a lot of different manufacturers, and various devices all have the interface of receive clock synchronizing signal, mainly contain pulse synchronous signal; Serial port to the time mode; The IRIG-B mode.Their collection site data send control centre to, and accept the control command that mission control center issues.When carrying out these operations, generally require free record, especially circuit switches, machine operation control waits operation, more strict time order and function order, therefore, equipment requirements in the whole industry spot system has a synchronized clock system, so that unified time to be provided.Original industry spot synchronized clock system typically uses a gps clock and accepts module and obtain gps clock, and then be converted to the clock form that field apparatus can receive, as IRIG-B sign indicating number, pulse per second (PPS) etc., distribute downwards by the separate lines of separating with data transmission link.
Along with the application of ethernet technology in the industry spot network, a kind of new clock synchronization mode begins to use, it is the IEEE1588 agreement, its full name is " the precision interval clock synchronous protocol standard of network measure and control system ", basic design is by hardware and software the internal clock of the network equipment (client computer) and the master clock of main control computer to be realized can realizing precision lock in time less than 1us synchronously.Because IEEE1588 agreement main reference Ethernet is worked out, its data packet format is consistent with Ethernet, and therefore the IEEE1588 protocol massages can transmit by data transmission link in Ethernet, and does not need extra cable.When the industry spot network begins to upgrade to Ethernet, such problem can appear in the construction of synchronized clock system: because the on-site terminal number of devices is very big, and Ethernet switch often can not maybe can only provide the non-IEEE1588 clock interface of minute quantity, therefore, when network upgrade, on-site terminal equipment need be replaced by the novel equipment with IEEE1588 clock interface, hardware cost is higher and cause the waste of original investment, perhaps keep original clock system, but the inconsistent problem of new and old clock system may appear, and the field wiring complexity, the cable cost is very high.
The utility model content
In order to solve the problems of the technologies described above, to provide a kind of now and realize that the temporal information with I EEE1588 form is converted to the device of multiple clock information form.
A kind of device of realizing the clock format conversion,
Described device comprises Network Interface Module, protocol process module, clock modular converter and drive circuit;
Network Interface Module receives the packet that includes clock information in the Ethernet;
Protocol process module receives in the described Ethernet that described Network Interface Module handles and includes the clock information packet, handles obtaining clock information according to the IEEE1588 protocal analysis, and calculates the local clock deviation, to keep and the upper level clock synchronization;
The clock modular converter receives described clock information from described protocol process module, and described clock information is converted to the synchronised clock of IRIG-B form or pulse output format;
Drive circuit receives described synchronised clock from described clock modular converter, and described synchronised clock conversion physical signalling is sent.
Described Network Interface Module comprises Ethernet interface chip DP83640 and local clock, and adopts the data-interface of RJ45,1X9 optical module or SFP; Described DP83640 is by the IEEE1588 protocol massages of data-interface reception and transmission Ethernet data bag, and the concrete time of recorder and transmission message; Described Network Interface Module passes through MII interface and the mutual message of protocol process module, and the concrete time of packet sending and receiving is provided by serial line interface; Local clock is by the clock interface input of DP83640, as the record benchmark of concrete time of transmitting-receiving.
The cpu system that described protocol process module employing cpu chip AT9200 is a core is realized, be used for clock jitter according to IEEE1588 protocol massages and local zone time calculating this locality and upper level, and adjustment local zone time, keep and the upper level clock synchronization, will offer described clock generating module the time simultaneously.
Described clock generating module adopts CPLD chip EPM1270 to realize, and use 8 asynchronous buss to connect between the described protocol process module, be used to receive the clock information that described protocol process module provides, carry out format conversion according to setting, the form of supporting comprises IRIG-B mode and programming lock-out pulse, and exports to described drive circuit.
Described drive circuit is finished chnnel coding by the protocol conversion chip, perhaps converts clock signal to coincidence circuit by level transferring chip and transmits the signal that requires, and sends then.
By clock converter provided by the invention, can insert in the high-speed industrial field network of new ethernet technology for the basis; Can obtain clock information and keep synchronous by resolving the IEEE1588 protocol massages; Can provide the synchronised clock of the IRIG-B mode and the lock-out pulse mode of multiple interfaces form, the terminal equipment in the compatible original system, the investment of protection legacy network; A large amount of synchronised clock interfaces can be provided, satisfy the demand of industry spot great amount of terminals equipment needs synchronised clock.
Description of drawings
Fig. 1 is converted to the flow chart of clock form for a long time for realizing the Ethernet data bag
Fig. 2 is converted to the schematic diagram of clock form for a long time for realizing the Ethernet data bag
Embodiment
Below in conjunction with accompanying drawing the present invention is done detailed description further.
A kind of device of realizing the clock format conversion comprises the steps:
(a), utilize Network Interface Module to receive the packet that includes clock information in the Ethernet;
(b), will include in the described Ethernet clock information packet input protocol process module, handle to obtain clock information through described protocol process module according to the IEEE1588 protocal analysis, and described clock information offered the clock modular converter;
(c), the clock generating module in the described clock modular converter converts described clock information the synchronised clock of IRIG-B form or pulse output format to, the drive circuit in the described clock modular converter converts described synchronised clock to physical signalling and sends.As shown in Figure 1.
Described Network Interface Module adopts the networking interface of RJ45,1X9 optical module or SFP.
Described step (b) comprises that also described clock information and the upper level clock of handling acquisition according to the IEEE1588 protocal analysis through described protocol process module compares, and it is synchronous to guarantee both.
Described drive circuit mode output signal comprises:
Pulse synchronous signal, comprising PSS, PPM and PPH;
Serial port to the time mode, comprising RS232 and RS422;
Or adopt the IRIG mode to the time, comprise direct current, interchange, RS422 and RS232.
Described clock modular converter comprises clock generating module and drive circuit.
Realize that the Ethernet data bag is converted to the device of clock form for a long time, is characterized in that:
Described device comprises:
Network Interface Module is used for receiving the packet that Ethernet includes clock information;
Protocol process module, be used for receiving the described Ethernet that described Network Interface Module handles and include the clock information packet, handle obtaining clock information according to the IEEE1588 protocal analysis, and calculate the local clock deviation, to keep and the upper level clock synchronization;
The clock modular converter is used for receiving described clock information from described protocol process module, and described clock information is converted to the synchronised clock of IRIG-B form or pulse output format;
Drive circuit is used for receiving described synchronised clock from described clock modular converter, and described synchronised clock conversion physical signalling is sent.
Described Network Interface Module adopts the networking interface of RJ45,1X9 optical module or SFP.
Described drive circuit mode output signal comprises:
Pulse synchronous signal, comprising PSS, PPM and PPH;
Serial port to the time mode, comprising RS232 and RS422;
Or adopt the IRIG mode to the time, comprise direct current, interchange, RS422 and RS232.
Described clock modular converter comprises clock generating module and drive circuit.
Generally speaking; system principle of the present invention is to utilize special chip to obtain the IEEE1588 protocol massages of Ethernet data packet format; extract clock information and keep synchronous by protocol processes; synchronised clock according to IRIG-B mode and lock-out pulse mode requires to convert to corresponding form then; form the multi-form physical signalling of multichannel by drive circuit again and export to terminal equipment; thereby kept the clock form with the original system compatibility, so that the transformation of original system and protection original investment.
With reference to the accompanying drawings 2, Ethernet implementation is according to an embodiment of the invention described.
As shown in Figure 2, this scheme comprises: as the Network Interface Module of data packet transceive, extract and keep synchronous protocol process module as clock information, the clock generating module that generates as the synchronised clock of IRIG-B mode and lock-out pulse mode is as the drive circuit of clock output.
Network Interface Module comprises Ethernet interface chip DP83640 and local clock.DP83640 receives and sends form by data-interface is the IEEE1588 protocol massages of Ethernet data bag, and the concrete time of recorder and transmission message.Network Interface Module passes through MII interface and the mutual message of protocol process module, and the concrete time of packet sending and receiving is provided by serial line interface.Local clock is by the clock interface input of DP83640, as the record benchmark of concrete time of transmitting-receiving.
Protocol process module employing cpu chip AT9200 is that the cpu system of core is realized, be used for clock jitter according to IEEE1588 protocol massages and local zone time calculating this locality and upper level, and adjustment local zone time, keep and the upper level clock synchronization, to the time offer clock generating module simultaneously, support IEEE1588 version V1, V2.Its principle be by with the message interaction of upper level clock, obtain that the transmitting-receiving message is accurate to be sent and time of reception, calculate deviation and line delay according to these times then.Detailed process is: protocol process module can get access to the transmitting time t1 of message from the protocol massages that receives by the MII interface, again the time of reception t2 by serial line interface reading and saving from Network Interface Module; Then, send protocol massages and obtain its transmitting time t3 (by the local network interface module) and time of reception t4 (passing through protocol massages) to the upper level clock again, just can calculate time deviation and line delay according to these several times.After the time deviation of acquisition and upper level clock, protocol process module just can keep synchronously by adjusting local zone time, and the temporal information synchronously is written in the clock generating module by 8 asynchronous buss.
Clock generating module adopts CPLD chip EPM1270 to realize, and use 8 asynchronous buss to connect between the protocol process module, be used to receive the clock information that protocol process module provides, carry out format conversion according to setting, the form of supporting comprises the IRIG-B mode, programmable sync pulse (comprising PPS, PPM, PPH and 10MHz clock), and export to drive circuit.Protocol process module provides absolute zebra time, and clock generating module converts thereof into the form output of IRIG-B, simultaneously, according to the moment of IRIG-B output carry out to the time, to produce lock-out pulse accurately.All signals output to driver module with the form of Transistor-Transistor Logic level, output to device external after the processing of overdrive circuit.
Drive circuit is used to export the form that meets terminal requirements and the synchronised clock of level standard.Drive circuit is finished chnnel coding by the protocol conversion chip, perhaps converts clock signal to coincidence circuit by level transferring chip and transmits the signal that requires, and sends then.In the present embodiment, drive circuit can provide the IRIG-B mode synchronised clock of 8 road DC forms, the programmable sync pulse of 8 road Transistor-Transistor Logic levels (comprising PPS, PPM, PPH and 10MHz clock) by level transferring chip.In addition, wherein the signal of two-way IRIG-B is converted to the light signal transmission by electrooptical device.
In the present embodiment, all modules all are arranged on the same veneer.
By scheme described above; the synchronised clock that the present invention will adopt the IEEE1588 agreement to transmit is converted to the synchronised clock of IRIG-B mode and lock-out pulse mode; the clock interface of the terminal equipment in the compatible original system has reduced the hardware cost of upgrade of network, has protected the investment of legacy network.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (5)
1. device of realizing the clock format conversion is characterized in that:
Described device comprises Network Interface Module, protocol process module, clock modular converter and drive circuit;
Network Interface Module receives the packet that includes clock information in the Ethernet;
Protocol process module receives in the described Ethernet that described Network Interface Module handles and includes the clock information packet, handles obtaining clock information according to the IEEE1588 protocal analysis, and calculates the local clock deviation, to keep and the upper level clock synchronization;
The clock modular converter receives described clock information from described protocol process module, and described clock information is converted to the synchronised clock of IRIG-B form or pulse output format;
Drive circuit receives described synchronised clock from described clock modular converter, and described synchronised clock conversion physical signalling is sent.
2. device according to claim 1 is characterized in that: described Network Interface Module comprises Ethernet interface chip DP83640 and local clock, and adopts the data-interface of RJ45,1X9 optical module or SFP; Described DP83640 is by the IEEE1588 protocol massages of data-interface reception and transmission Ethernet data bag, and the concrete time of recorder and transmission message; Described Network Interface Module passes through MII interface and the mutual message of protocol process module, and the concrete time of packet sending and receiving is provided by serial line interface; Local clock is by the clock interface input of DP83640, as the record benchmark of concrete time of transmitting-receiving.
3. device according to claim 1, it is characterized in that: the cpu system that described protocol process module employing cpu chip AT9200 is a core is realized, be used for clock jitter according to IEEE1588 protocol massages and local zone time calculating this locality and upper level, and adjustment local zone time, keep and the upper level clock synchronization, will offer described clock generating module the time simultaneously.
4. device according to claim 1, it is characterized in that: described clock generating module adopts CPLD chip EPM1270 to realize, and use 8 asynchronous buss to connect between the described protocol process module, be used to receive the clock information that described protocol process module provides, carry out format conversion according to setting, the form of supporting comprises IRIG-B mode and programming lock-out pulse, and exports to described drive circuit.
5. device according to claim 1 is characterized in that: described drive circuit is finished chnnel coding by the protocol conversion chip, perhaps converts clock signal to coincidence circuit by level transferring chip and transmits the signal that requires, and sends then.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120184344 CN202059440U (en) | 2011-06-02 | 2011-06-02 | Device for realizing clock format conversion |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120184344 CN202059440U (en) | 2011-06-02 | 2011-06-02 | Device for realizing clock format conversion |
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| CN202059440U true CN202059440U (en) | 2011-11-30 |
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| CN 201120184344 Expired - Lifetime CN202059440U (en) | 2011-06-02 | 2011-06-02 | Device for realizing clock format conversion |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102901944A (en) * | 2012-09-27 | 2013-01-30 | 中国电力科学研究院 | B code clock synchronization device for field calibration of electronic mutual inductors |
| CN103532953A (en) * | 2013-10-16 | 2014-01-22 | 中国南方电网有限责任公司 | IEEE (Institute of Electrical and Electronics Engineers) 1588 master station based on Ucos-II operating system and Lwip (Lightweight Internet Protocol) stack and method for processing message based on master station |
| CN105406920A (en) * | 2015-10-30 | 2016-03-16 | 武汉光迅科技股份有限公司 | Optical module supporting gigabit Ethernet protocol processing |
| TWI669014B (en) * | 2017-12-26 | 2019-08-11 | 中華電信股份有限公司 | System and method for end-to-end ptp profiles integration |
-
2011
- 2011-06-02 CN CN 201120184344 patent/CN202059440U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102901944A (en) * | 2012-09-27 | 2013-01-30 | 中国电力科学研究院 | B code clock synchronization device for field calibration of electronic mutual inductors |
| CN103532953A (en) * | 2013-10-16 | 2014-01-22 | 中国南方电网有限责任公司 | IEEE (Institute of Electrical and Electronics Engineers) 1588 master station based on Ucos-II operating system and Lwip (Lightweight Internet Protocol) stack and method for processing message based on master station |
| CN105406920A (en) * | 2015-10-30 | 2016-03-16 | 武汉光迅科技股份有限公司 | Optical module supporting gigabit Ethernet protocol processing |
| CN105406920B (en) * | 2015-10-30 | 2018-06-26 | 武汉光迅科技股份有限公司 | A kind of optical module for supporting gigabit Ethernet protocol processes |
| TWI669014B (en) * | 2017-12-26 | 2019-08-11 | 中華電信股份有限公司 | System and method for end-to-end ptp profiles integration |
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Granted publication date: 20111130 |