CN202042156U - GIP (general information portal) panel testing structure - Google Patents
GIP (general information portal) panel testing structure Download PDFInfo
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- CN202042156U CN202042156U CN2010206034723U CN201020603472U CN202042156U CN 202042156 U CN202042156 U CN 202042156U CN 2010206034723 U CN2010206034723 U CN 2010206034723U CN 201020603472 U CN201020603472 U CN 201020603472U CN 202042156 U CN202042156 U CN 202042156U
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Abstract
The utility model discloses a GIP (general information portal) panel testing structure. The testing structure comprises a display panel and a plurality of serial gaskets which is manufactured on a first substrate, wherein a first grid driving circuit, a second grid driving circuit, a plurality of grid lines, and a plurality of source lines are arranged on the first substrate of the display panel, and the plurality of serial gaskets are electrically connected to the first grid driving circuit; when the display panel is tested, the serial gaskets are electrically connected to the second grid driving circuit by a testing system, and a testing signal is sent to the second grid driving circuit by passing the serial gaskets and the testing system from the first grid driving circuit in sequence. The GIP panel testing structure can reduce the testing devices required during testing the panel and further lower the testing cost by designing the serial gaskets on the panel and a control line on a probe jig.
Description
Technical field
The utility model is the framework about a kind of test panel, particularly at the test structure of the GIP panel with bilateral gate driving, can reduce the testing cost of panel.
Background technology
In order to reduce the cost of display pannel, panel manufacturers is directly made the gate driver circuit on the panel on panel gradually, does not therefore need additionally to buy gate driving IC when the assembling panel again.This kind do not need the panel of gate driving IC to be referred to as GIP (gate in panel) panel, or is called non-grid (gateless) panel.General large-size or the higher GIP panel of degree of separating, gate driver circuit on its panel can be done the left and right sides at display panel substrate, can drive odd gates line and even number gate line on the panel respectively, perhaps, each half of gate line about the driving circuit of this left and right sides respectively drives on the panel.
Traditionally, when this kind of test GIP panel 100, its testing process as shown in Figure 1, drive the odd gates line in left side earlier, with half pixel 101 in the test panel, and then drive the even number gate line on right side, with second half pixel 102 in the test panel, the pixel data of integrating these two halves at last again lacks distribution 103 to obtain complete panel point.
The mode that this kind is traditional then needs the test signal generator in two testing apparatus, the especially testing apparatuss of overlapping if will drive the gate driver circuit of the left and right sides simultaneously.Under mass-produced situation, testing each panel needs two test signal generators, makes that test is very uneconomical.If only use a test signal generator, then must be after having surveyed the panel pixel of half, dismounting testing apparatus, and then the pixel of testing second half; Way so, with making the time of carrying out test elongated, so, all can't effectively reduce testing cost no matter in which kind of above-mentioned mode.
Therefore the utility model discloses a kind of new test structure and method, at the GIP panel with bilateral gate driving, reduces the demand of testing apparatus, and then reduces testing cost.
The utility model content
The utility model is framework and the method that proposes a kind of GIP of test panel, in classic method, uses the utility model and can save testing apparatus required when carrying out test.The test structure of GIP panel of the present utility model includes: a display pannel, on first plate base of this display pannel, have a first grid driving circuit, a second grid driving circuit, a plurality of gate lines, with a plurality of source electrode lines; One a plurality of serial connection liners are made on this first plate base, and these a plurality of serial connection liners all are electrically connected to this first grid driving circuit.This first plate base can be substrate or infrabasal plate on the display pannel, and the gate driver circuit on this substrate can be set to have the offset buffer function, and is able to those gate lines on timesharing startup (activate) substrate.
When this display pannel of test, these a plurality of serial connection liners can be electrically connected to this second grid driving circuit via a test macro, make a test signal through this a plurality of serial connection liners and this test macro, and be sent to the second grid driving circuit in regular turn by the first grid driving circuit.On the contrary, these a plurality of serial connection liners also can be designed to electrically connect with the second grid driving circuit, when the test display pannel, are electrically connected to the first grid driving circuit by this test macro more then.
This test macro includes: a probe tool, on this probe tool an operation circuit and plurality of probes are arranged, and when carrying out test, this operation circuit can be electrically connected to the second grid driving circuit with these a plurality of serial connection liners on the substrate; Plurality of probes on this test macro can electrically connect with these a plurality of liners that are connected in series with first grid driving circuit, second grid driving circuit respectively; One pin is surveyed board, and this pin is surveyed board and loaded this probe tool, and controls this probe tool and first grid driving circuit, second grid driving circuit and this a plurality of electric connections that are connected in series liner; One signal generator includes the test signals such as inversion signal, an enabling signal, a reference voltage signal and a plurality of voltage pulse signals of a frequency signal, a frequency in order to generation.
Carry out GIP panel test method of the present utility model, include: use this first plate base of above-mentioned display pannel, and use this above-mentioned test macro; When test action, this pin is surveyed board and is controlled the probe tool that it installs, and the plurality of probes on this probe tool is electrically connected with first grid driving circuit, second grid driving circuit, these a plurality of liners that are connected in series respectively; Wherein these a plurality of serial connection liners can be electrically connected to the second grid driving circuit via the operation circuit on this probe tool; So when the signal generator in the test macro send a test signal behind the first grid driving circuit, this circuit can timesharing start gate line in regular turn one by one, when the last item gate line that this circuit is controlled, this test signal can be sent to a plurality of serial connection liners on first plate base, be sent to the second grid driving circuit by plurality of probes on the probe tool and operation circuit then, this driving circuit timesharing too starts the gate line that it is controlled in regular turn one by one, finishes up to test.
When carrying out the test display pannel, first grid driving circuit on its first plate base and second grid driving circuit can be set to have the offset buffer function earlier; For avoiding fuzzy focus of the present utility model, not in this superfluous principle and detailed functions of chatting offset buffer; Consequently this test signal can be via a plurality of gate lines on first grid driving circuit and the second grid driving circuit timesharing sequential start display pannel.So-called timesharing sequential start is meant that gate driver circuit can start a certain gate line with a frequency (clock) as the function of offset buffer, starts, one by one up to inswept all gate lines.
A certain gate line on proper this first substrate be activated during in, signal generator can be sent voltage pulse signal (pulse) to a plurality of source electrode lines on this substrate, so that each pixel on this gate line is imported a voltage; Because the gate driver circuit timesharing starts those gate lines in regular turn one by one up to inswept all gate lines, so each pixel on the panel all can be transfused to voltage via those source electrode lines.In finishing to after each pixel input voltage, as above-mentioned mode again by a plurality of gate lines on this substrate of gate driver circuit timesharing sequential start, when a certain gate line be activated during in, can read the voltage of these a plurality of source electrode lines; Read the magnitude of voltage of all pixels in this way, and must be in order to analyze the defect distribution of this display pannel.
Description of drawings
Fig. 1 is the traditional test mode of explanation one GIP display pannel.
Fig. 2 is gate driver circuit, a plurality of gate lines and a plurality of source electrode line that explanation one substrate has the left and right sides.
Fig. 3 is the circuit framework and the function of explanation offset buffer.
Fig. 4 is an explanation test structure of the present utility model.
Embodiment
The utility model will be described in detail with preferred embodiment and viewpoint, and this type of narration is to explain structure of the present utility model, only in order to explanation but not in order to limit claim of the present utility model.Therefore, the preferred embodiment in instructions, the utility model also can extensively be rendered in other embodiment.
The utility model is test structure and the method that discloses a kind of GIP panel, especially is applied in a kind of GIP panel with both sides gate driving, uses test structure of the present utility model and method and can save testing apparatus.
Prepare a display pannel, general panel includes two plate bases up and down, and the material of substrate is a transparent material, as glass.As shown in Figure 2, have gate driver circuit, below the gate driver circuit of the left and right sides is called first grid driving circuit 201 and second grid driving circuit 203 in the wherein both sides of a plate base 200 of this panel.In addition, on substrate 200, also have several horizontal conductive drive wires, be called gate line 210, and have several vertical conductive drive wires, be called source electrode line 220 at this at this.Is a pixel of display pannel at gate line 210 with the place that source electrode line 220 intersects, and is this pixel of may command via the voltage of control gate line and source electrode line.First grid driving circuit 201 and second grid driving circuit 203 can start the gate line 210 on (activate) substrate 200, when a certain gate line 210 be activated during, if with vertical source electrode line 220 input voltage signals that this gate line intersects, then can control the magnitude of voltage of this pixel; With above-mentioned gate line control mode, also can read the magnitude of voltage of this pixel by source electrode line.
In the present embodiment, first grid driving circuit 201 can start the gate line of odd number, second grid driving circuit 203 then can start the gate line of even number, thus the summation of first grid driving circuit 201 and second grid driving circuit 203 can driving substrate on total gate line 210.
In another example also can be by the gate line of first grid driving circuit 201 control even numbers, by the gate line of second grid driving circuit 203 control odd numbers.
In another embodiment, gate line in the substrate 200 is divided into left and right sides two halves at the center line position of this substrate, control the wherein gate line (being exemplified as the left side) of half with first grid driving circuit 201, control second half gate line (being exemplified as right-hand part) by second grid driving circuit 203.
When the test display pannel, first grid driving circuit 201 and second grid driving circuit 203 can be configured to offset buffer 300, as shown in Figure 3.For avoiding fuzzy focus of the present utility model, at this not superfluous operating principle of chatting offset buffer.When first grid driving circuit 201 and second grid driving circuit 203 are configured to offset buffer 300, as long as to this first grid driving circuit 201 and second grid driving circuit 203 input one frequency signal CK 311 and enabling signal Vst 312, then but 203 timesharing of first grid driving circuit 201 and second grid driving circuit produce as shown in Figure 3 OUT1 313, OUT2 314 and OUT3 315 isopulse signals in regular turn, in order to timesharing sequential start gate line 210.Right in first grid driving circuit 201 and second grid driving circuit 203 do not electrically connect, so during this substrate 200 of test, must import enabling signal Vst 312 respectively and give first grid driving circuit 201 and second grid driving circuit 203, can start gate line total on the substrate 200 210.
In one embodiment, as shown in Figure 4, prepare an above-mentioned substrate 200, make a plurality of serial connection liners 250 on this substrate, those serial connection liners 250 electrically connect with first grid driving circuit 201, in order to prepare to transmit the signal of being come by this driving circuit 201.Prepare a test macro, this system includes a signal generator 40, one pins and surveys board (Probe Station) (not being illustrated among the figure), a probe tool 50.
Signal generator 40 can produce and include frequency signal (CK), the inversion signal of frequency (/CK), enabling signal (Vst), reference voltage signal (Vg), and a plurality of voltage pulse signals (Pulse) (not being illustrated among the figure).This pin is surveyed the action of board may command probe tool, and plurality of probes is arranged on the probe tool 50, in order to first grid driving circuit 201, second grid driving circuit 203, serial connection liner 250, reaches the necessary contact point of execution test and electrically connects.One operation circuit is arranged on the probe tool in addition, can when carry out test, will be connected in series liner 250 and be electrically connected to second grid driving circuit 203 (be connected in series liner 250 originally and be off state) with second grid driving circuit 203.
When carrying out the display pannel test, first grid driving circuit 201 on the substrate 200 and second grid driving circuit 203 have been set to have the offset buffer function.Signal generator 40 sees through pin survey board, the probe tool is sent to first grid driving circuit 201 with test signal, and this driving circuit 201 will start the gate line of an odd number in regular turn with a frequency (clock).When first grid driving circuit 201 starts the gate line of the last item odd number on the substrate, this test signal can be sent to serial connection liner 250, and be sent to second grid driving circuit 203 via the operation circuit on the probe tool, the gate line of beginning sequential start even number is till the gate line that starts the last item even number.
Test display pannel in the above described manner,, only need to use a cover signal generator 40, just can finish the test of test display pannel for the substrate that left and right sides gate driver circuit is arranged.
The more detailed test detail of present embodiment below remarks additionally: in during above-mentioned first grid driving circuit 201 and a certain gate line 210 of second grid driving circuit 203 startups, can import a voltage pulse signal (pulse) respectively to each bar source electrode line 220 by signal generator 40 or other testing apparatus, so that each pixel on this gate line is imported a voltage; Because gate line 210 is started in regular turn one by one by timesharing, so each pixel on the display pannel all can be transfused to a voltage.The mode that so-called timesharing starts in regular turn one by one is the method for operating as offset buffer shown in Figure 3 300, just with a frequency, imports a voltage pulse signal to a certain gate line, up to having swept all gate lines.After test execution finished, timesharing sequential start gate line 210 in the same manner described above again read the magnitude of voltage of each bar source electrode line 220 then in regular turn, knows that promptly the picture element flaw on the full wafer display board distributes.
Above-mentionedly be stated as preferred embodiment of the present utility model.The skill person in this field is deserved to be in order to explanation the utility model but not in order to limit the patent right scope that the utility model is advocated to understand it.Its scope of patent protection when on aforesaid claim and etc. same domain decide.All skill persons who is familiar with this field, in not breaking away from this patent spirit or scope, change of being done or retouching all belong to the utility model and disclose equivalence change or the design that spirit is finished down, and should be included in the above-mentioned claim.
Claims (7)
1. the test structure of a GIP panel is characterized in that, includes:
One display pannel, on first plate base of this display pannel, have a first grid driving circuit, a second grid driving circuit, a plurality of gate lines, with a plurality of source electrode lines;
One a plurality of serial connection liners are made on this first plate base, and these a plurality of serial connection liners all are electrically connected to this first grid driving circuit;
When this display pannel of test, those serial connection liners can be electrically connected to this second grid driving circuit via a test macro, make a test signal through those serial connection liner and this test macro, and be sent to this second grid driving circuit in regular turn by this first grid driving circuit.
2. the test structure of GIP panel as claimed in claim 1 is characterized in that, this display pannel includes a upper substrate and an infrabasal plate, and this first plate base can be this upper substrate or is this infrabasal plate.
3. the test structure of GIP panel as claimed in claim 1, it is characterized in that, those serial connection liners can be designed to electrically connect with this second grid driving circuit, when this display pannel of test, are electrically connected to this first grid driving circuit by this test macro more then.
4. the test structure of GIP panel as claimed in claim 1 is characterized in that, this test macro includes:
One probe tool has an operation circuit and plurality of probes on this probe tool, and when carrying out test, and those probes can each be connected in series the liner electric connection with this first grid driving circuit, this second grid driving circuit with those;
One pin is surveyed board, and this pin is surveyed board and loaded this probe tool, and control this probe tool with this first grid driving circuit, this second grid driving circuit, reach those and be connected in series the electric connection of liner;
One signal generator is in order to produce this test signal.
5. the test structure of GIP panel as claimed in claim 4 is characterized in that, this operation circuit can be connected in series those liner and be electrically connected to this second grid driving circuit.
6. the test structure of GIP panel as claimed in claim 4 is characterized in that, this signal generator can produce and include: a frequency signal; The inversion signal of one frequency; One enabling signal; One reference voltage signal; A plurality of voltage pulse signals.
7. the test structure of GIP panel as claimed in claim 4 is characterized in that, those serial connection liners can be electrically connected to this second grid driving circuit via this operation circuit on this probe tool;
Make this signal generator can send a test signal to this first grid driving circuit; This test signal can be sent to this second grid driving circuit via those serial connection liners, those probes and this operation circuit again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206034723U CN202042156U (en) | 2010-11-09 | 2010-11-09 | GIP (general information portal) panel testing structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206034723U CN202042156U (en) | 2010-11-09 | 2010-11-09 | GIP (general information portal) panel testing structure |
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| Publication Number | Publication Date |
|---|---|
| CN202042156U true CN202042156U (en) | 2011-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206034723U Expired - Fee Related CN202042156U (en) | 2010-11-09 | 2010-11-09 | GIP (general information portal) panel testing structure |
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| Country | Link |
|---|---|
| CN (1) | CN202042156U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390079A (en) * | 2015-12-28 | 2016-03-09 | 昆山工研院新型平板显示技术中心有限公司 | GIP detection circuit and flat display device |
| WO2018152882A1 (en) * | 2017-02-23 | 2018-08-30 | 武汉华星光电技术有限公司 | Gate drive circuit detection apparatus and detection method |
-
2010
- 2010-11-09 CN CN2010206034723U patent/CN202042156U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390079A (en) * | 2015-12-28 | 2016-03-09 | 昆山工研院新型平板显示技术中心有限公司 | GIP detection circuit and flat display device |
| CN105390079B (en) * | 2015-12-28 | 2018-03-30 | 昆山工研院新型平板显示技术中心有限公司 | GIP detects circuit and panel display apparatus |
| WO2018152882A1 (en) * | 2017-02-23 | 2018-08-30 | 武汉华星光电技术有限公司 | Gate drive circuit detection apparatus and detection method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111116 Termination date: 20161109 |