CN202041826U - Integrated antenna digital control device based on NIOS II microprocessor - Google Patents

Integrated antenna digital control device based on NIOS II microprocessor Download PDF

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Publication number
CN202041826U
CN202041826U CN2010206979060U CN201020697906U CN202041826U CN 202041826 U CN202041826 U CN 202041826U CN 2010206979060 U CN2010206979060 U CN 2010206979060U CN 201020697906 U CN201020697906 U CN 201020697906U CN 202041826 U CN202041826 U CN 202041826U
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chip
antenna
nios
microprocessor
fpga
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李铁
贾军
赵书阳
陈大平
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Beijing Institute of Telemetry Technology
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Beijing Institute of Telemetry Technology
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Abstract

An integrated antenna digital control device based on an NIOS II microprocessor is a control device capable of realizing high-precision control of an antenna servo system, and mainly comprises an interface circuit, an A/D (Analog/Digital) conversion chip and an FPGA (Field Programmable Gate Array) module, wherein the A/D conversion chip is used for acquiring receiver signals and push rod signal data and sending the acquired signals and data to the FPGA module; and the NIOS II microprocessor is embedded into the FPGA module and used for simultaneously acquiring the receiver signals, push rod signals, time-code signals and differential serial signals, selecting the antenna control modes according to the signals, generating control quality according to a certain control algorithm and sending the control quality to an antenna driving unit, so as to control the antenna servo system. The integrated antenna digital control device provided by the utility model has very strong data processing capability, achieves highly-integrated design of an antenna servo controller, and enables the integration level of the antenna servo controller to be greatly upgraded.

Description

A kind of integrated antenna digital control device based on NIOS II microprocessor
Technical field
The utility model relates to a kind of integrated antenna digital control device based on NIOS II microprocessor, belong to the antenna servo system technical field, be used for High Accuracy Control, be equally applicable to the control of high-performance, high integration antenna servo system antenna servo system.
Background technology
Antenna servo system is an ingredient important in the telemetry system, it mainly acts on is in target enters visual line of sight the time, make receiving antenna search for and catch target automatically, with certain tracking accuracy Continuous Tracking target, target is near the center line of main beam all the time, thereby receives telesignalisation reliably continuously with maximum receiving gain.Particularly ought break down, when target departs from predetermined flight track, antenna servo system can be in the scope of big spatial domain the line trace of going forward side by side of code acquisition target, obtain important telemetry with failure judgement.In Tracking Through Telemetry equipment, the superiority of digital servosystem is obvious day by day.
Existing antenna controller is divided into analog controller and digitial controller two big classes.Because analog controller is difficult to realize the control algolithm of more complicated, be difficult to satisfy the needs of antenna servo system High Accuracy Control, so digitial controller is an inevitable choice.The advantage of digitial controller shows: parameter modification is convenient, can realize complicated controller algorithm, can satisfy the requirement of High Accuracy Control.Digitial controller is fit to integratedly in addition, and modular design is dwindled greatly with respect to its volume of analog controller, and power consumption obviously reduces, and this haves a great attraction for AEROSPACE APPLICATION.The update of system is more easy owing to only relate to software in addition.
Present C2000 series DSP with Ti company serves as that the antenna controller of control core is commonplace, though this class scheme can realize the control of antenna servo system, also have following shortcoming: (1) data-handling capacity is not enough.C2000 series is fixed point type DSP, and floating data processing power deficiency can not satisfy the real-time requirement of the complicated control algolithm of operation.(2) Peripheral Interface deficiency.The Peripheral Interface of the DSP C2000 series that TI company is common is rich and varied, but serial ports (UART) has only two, if select for use this a, need extend out serial port from parallel data.In case project demands changes, required hardware adaptor also needs redesign.If select the C6000 series DSP chip of Ti company for use, though arithmetic capability is enough, Peripheral Interface still is short of, and can not satisfy the demand of antenna servo system equally.
The utility model content
Technology of the present utility model is dealt with problems and is: overcome the deficiencies in the prior art, a kind of integrated antenna digital control device based on the NIOSII microprocessor is provided.
Technical solution of the present utility model is: a kind of integrated antenna digital control device based on NIOS II microprocessor, comprise the FPGA module, interface module and A/D modular converter, the FPGA module comprises configuring chip, fpga chip, extend out SDRAM and extend out Flash, fpga chip respectively with configuring chip, extend out SDRAM and extend out Flash and be connected, the embedded NIOS II of fpga chip microprocessor, the A/D modular converter comprises multichannel selection chip and A/D conversion chip, interface module is made up of the PCI bridging chip, the PCI bridging chip connects fpga chip and host computer, multichannel is selected chip will receive analog signals to send into the A/D conversion chip and carry out analog to digital conversion, and the digital signal after the conversion is sent to fpga chip.
Described fpga chip adopts the StratixEP1S25 chip.
Described A/D conversion chip adopts the AD1674 chip, and multichannel selects chip to select the DG406 of MAXIM company for use, and A/D conversion chip and multichannel are selected to connect by the OP37 chip between the chip.
The utility model design concept:
The embedded NIOS II of fpga chip microprocessor comprises abundant peripheral hardware resource.Wherein the two-way serial ports is gathered antenna position information and duplexer amount signal, gather with programmed control receiver signal and push rod signals sampling and by PIO, push button signalling, time code signal collect in the NIOS II microprocessor by PIO equally, the control information of host computer and the monitor message of antenna controller are all transmitted by cpci bus, and antenna controller has been reserved, and the two-way serial interface can receive the digital received machine information and three road serial interfaces can receive three tunnel inertial navigation information.Contain timer in the NIOS II microprocessor, every 10ms produces a look-at-me.After regularly interrupting generation, antenna controller is gathered antenna position information, receiver signal, push rod signal, push button signalling, time code signal, and the steering order that issues according to host computer, select corresponding work mode, thereby select corresponding control algolithm to generate controlled quentity controlled variable, pass to the antenna driver element by serial ports, thereby realize High Accuracy Control antenna servo system.
The utility model compared with prior art beneficial effect is:
(1) the utility model utilizes the EP1S25F780 chip of the Stratix series of altera corp to be the execution core, and realization is to the High Accuracy Control of antenna servo system;
(2) the utlity model has the advantage of digitial controller: debugging flexibly, convenient, volume is little, in light weight, be convenient to realize complicated control algolithm, more existing fixed DSP is the digitial controller of core, data-handling capacity of the present utility model significantly improves, and can satisfy the real-time requirement of complicated control algolithm;
(3) the utility model adopts NIOS II microprocessor can realize the software restructural, NIOS II microprocessor is a kind of soft nucleus CPU, specially at the design philosophy of programmable system on the programmable logic device (PLD) of Altera and the sheet, done corresponding optimization, as a kind of configurable general risc processor, it can combine with the User Defined logic and constitute the SOC system, and download in the programming device of Altera and go, 32 soft nuclears of NIOS, in conjunction with external flash and mass storage, can constitute 32 powerful embedded processor systems;
(4) the utility model adopts NIOS II microprocessor technology not only to satisfy a large amount of operand demands, make the various states of antenna can real-time report give host computer and be presented in the monitoring interface, and realized the customizable of peripheral hardware, satisfy system for the numerous demand of Peripheral Interface, made the integrated level of system further improve;
(5) the utility model has been realized digitizing, the modularization, integrated of system, and realized the peripheral hardware restructural, can realize High Accuracy Control by generating the demand that different NIOS II microprocessors satisfies system's different peripheral on the basis that does not change circuit design to antenna servo system.
Description of drawings
Fig. 1 is a structure composition frame chart of the present utility model;
Fig. 2 is a control principle block diagram of the present utility model;
Fig. 3 is the embedded NIOS II microprocessor of FPGA of the present utility model;
Fig. 4 is an A/D modular converter circuit diagram of the present utility model;
Fig. 5 is the Flash memory circuitry figure that extends out of the present utility model;
Fig. 6 is the SDRAM circuit diagram that extends out of the present utility model;
Fig. 7 is a PCI bridging chip circuit diagram of the present utility model;
Fig. 8 is the control flow chart of FPGA module of the present utility model.
Embodiment
As shown in Figure 1, hardware module of the present utility model mainly is made up of interface module 6, A/D modular converter 10, FPGA module 4, wherein interface module 6 comprises PCI bridging chip 5, A/D modular converter 10 comprises multichannel selection chip 9 and A/D conversion chip 8, and FPGA module 4 comprises fpga chip 3, configuring chip 2, extends out Flash storer 11 and extends out SDRAM 12.PCI bridging chip 9054 joins with host computer 7 and FPGA module 4, be used for giving host computer 7 with the various condition monitoring signal reportings that FPGA module 4 generates, and the various control signals that host computer 7 is sent is handed down to FPGA module 4.Interface module 6 is handed down to fpga chip 3 with the control command that host computer 7 issues by PCI bridging chip 5, and the various pilot signals that fpga chip 3 collects also report host computer 7 by PCI bridging chip 5, and are presented on the monitoring interface of host computer 7.Multichannel is selected chip 9 selective receivers 1 wherein a tunnel sending in the A/D conversion chip 8 in the azimuth information of AGC signal, azimuth error signal, pitch error signal and the push rod of receiver 4, the pitching information, control the initial of A/D conversion by fpga chip 3,12 bit digital information behind the EOC are sent in the fpga chip 3.Embedded NIOSII microprocessor in the fpga chip 3 cooperates the Flash storer 11 and the SDRAM12 that extend out, has constituted a powerful embedded processor system.NIOS II microprocessor is gathered receiver signal, push rod signal, push button signalling, time code signal, and receive the steering order and the information of antenna driver element 1 that host computer 7 issues by PCI bridging chip 5 by defeated antenna pedestal angle information, switching value information and power amplifier self of difference string oral instructions, by the High Accuracy Control of certain control rate realization to antenna pedestal.
As shown in Figure 2, provided control principle of the present utility model, the detection of FPGA module 4 control time-code information, receiver information, push rod information and key information, and the control signal that issues according to host computer 7 generates certain controlled quentity controlled variable, be transferred to antenna driver element 1 by the RS422 serial ports, antenna driver element 1 generates certain Control current drive motor rotation according to the controlled quentity controlled variable of FPGA module 4 outputs, thereby realizes the High Accuracy Control of antenna servo system.
FPGA module 4 receiver control signals and push rod signals sampling; Embedded NIOS II microprocessor, gather antenna position information, receiver signal, push rod signal, push button signalling, time code signal, and the various steering orders that issue according to host computer 7, select corresponding work mode, thereby select corresponding control algolithm to generate controlled quentity controlled variable, pass to antenna driver element 1 by the RS422 serial ports, thereby realize High Accuracy Control antenna servo system.
As shown in Figure 3, FPGA module 4 is embedded NIOS II microprocessor.NIOS II microprocessor is a kind of risc processor that adopts pipelining, single instruction stream, and its most of instruction can be finished in a clock period.NIOS II microprocessor is again a kind of soft nucleus CPU, specially at the design philosophy of programmable system on the programmable logic device (PLD) of Altera and the sheet, has done corresponding optimization.As a kind of configurable general risc processor, it can combine with the User Defined logic and constitute the SOC system, and downloads in the programming device of Altera and go.32 soft nuclears of NIOS in conjunction with external flash and mass storage, can constitute 32 powerful embedded processor systems.NIOS II microprocessor is gathered receiver signal, push rod signal, push button signalling, time code signal, and receive the steering order and the information of antenna driver element 1 that host computer 7 issues by PCI bridging chip 5 by defeated antenna pedestal angle information, switching value information and power amplifier self of difference string oral instructions, by the High Accuracy Control of certain control rate realization to antenna pedestal.
As shown in Figure 4, be A/D modular converter 10 circuit diagrams of the present utility model.A/D modular converter 10 comprises multichannel selection chip 9 and A/D conversion chip 8.Multichannel selects chip 9 to link to each other with receiver signal, push rod signal, is used to select one road analog signals to send into A/D conversion chip 8 and carries out analog to digital conversion.A/D conversion chip 8 links to each other with FPGA module 4, is used for analog signals is sampled, and obtains digitized receiver signal and push rod signal.That modulus conversion chip of the present utility model adopts is the AD1674 of AD company, and this chip has the sampling rate of 12 precision, 10us, can support ± 5V, ± input voltage range of 10V, 0~10V, 0~20V.Multichannel selects chip 9 to select the DG406 of MAXIM company for use, and this chip support is selected 1 operation to 16 of input signal.Connect by chip OP37 between the two, satisfied the demand of system acquisition receiver signal and push rod signal fully.The beginning of the selection of signal and A/D conversion is controlled by the NIOS II microprocessor in the FPGA module 4, and reads 12 bit digital information of AD1674 output by it behind the A/D EOC.
Shown in Fig. 5,6, for the Flash of extending out storer 11 of the present utility model and extend out SDRAM12.Embedded NIOS II microprocessor in the fpga chip 3, the program initial storage is in Flash storer 11, and after waiting to power on, program changes among the SDRAM12 from Flash storer 11 and moves.
As shown in Figure 7, PCI bridging chip 5 of the present utility model has been selected PCI9054 for use.PCI9054 is the pci bus interface chip that U.S. PLX company produces, and it satisfies PCI V2.2 agreement, supports 32 33MHz clock pci buss, is specially adapted to the exploitation of pci bus peripheral product.PCI9054 adopts leading data pipeline framework (the Data Pipe Architecture) technology of PLX, is equipped with DMA engine, direct master control able to programme and immediate subordinate data transmission and PCI information transfer capability.PCI9054 has three equipment local bus options: M pattern, C pattern and J pattern.The utility model has adopted PCI9054 local bus J pattern.
The control flow of FPGA is as shown in Figure 8: system's back load logic information from configuring chip that powers on, success loads back program in the loading NIOS II microprocessor from Flash, initialization enters normal mode of operation after finishing, NIOS II microprocessor is carried out blank operation when not interrupting, and has when interruption to enter main the interruption.The control information of in main the interruption, at first reading host computer, carry out the selection of mode of operation then by the control information of host computer, and calculate the controlled quentity controlled variable of antenna driver element in the PID control program, send to the antenna driver element by the serial ports router by the RS422 serial ports at last.After the serial ports router finishes, enter and interrupt in the determining program.
The utility model conduct is based on the platform of the integrated antenna digital control device of NIOS II microprocessor, enough hardware resources are provided, with advanced person's control algolithm, application person can realize its function by revising NIOS II microprocessor flexibly and easily according to its special application.
The unspecified part of the utility model belongs to general knowledge as well known to those skilled in the art.

Claims (3)

1. integrated antenna digital control device based on NIOS II microprocessor, it is characterized in that: comprise FPGA module (4), interface module (6) and A/D modular converter (10), FPGA module (4) comprises configuring chip (2), fpga chip (3), extend out SDRAM (12) and extend out Flash (11), fpga chip (3) respectively with configuring chip (2), extend out SDRAM (12) and extend out Flash (11) and be connected, the embedded NIOS II of fpga chip (3) microprocessor, A/D modular converter (10) comprises multichannel selection chip (9) and A/D conversion chip (8), interface module (6) is made up of PCI bridging chip (5), PCI bridging chip (5) connects fpga chip (3) and host computer (7), multichannel is selected chip (9) will receive analog signals to send into A/D conversion chip (8) and carry out analog to digital conversion, and the digital signal after the conversion is sent to fpga chip (3).
2. a kind of integrated antenna digital control device based on NIOS II microprocessor according to claim 1 is characterized in that: described fpga chip (3) adopts the StratixEP1S25 chip.
3. a kind of integrated antenna digital control device according to claim 1 based on NIOS II microprocessor, it is characterized in that: described A/D conversion chip (8) adopts the AD1674 chip, multichannel selects chip (9) to select the DG406 of MAXIM company for use, and A/D conversion chip (8) and multichannel are selected to connect by the OP37 chip between the chip (9).
CN2010206979060U 2010-12-27 2010-12-27 Integrated antenna digital control device based on NIOS II microprocessor Expired - Lifetime CN202041826U (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104393408A (en) * 2014-12-11 2015-03-04 中国电子科技集团公司第五十四研究所 Flat azimuth driving combined device
CN104393412A (en) * 2014-12-05 2015-03-04 成都国卫通信技术有限公司 Antenna control device and method
CN104950770A (en) * 2015-06-24 2015-09-30 中国船舶重工集团公司第七二六研究所 Controllable high-speed multi-channel signal acquisition control circuit system and control method thereof
CN105653384A (en) * 2015-12-30 2016-06-08 惠州市伟乐科技股份有限公司 Soft-core CPU resetting method and master-slave type system
CN108167030A (en) * 2018-01-25 2018-06-15 榆林学院 A kind of blast furnace TRT servo-control systems based on FPGA

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104393412A (en) * 2014-12-05 2015-03-04 成都国卫通信技术有限公司 Antenna control device and method
CN104393408A (en) * 2014-12-11 2015-03-04 中国电子科技集团公司第五十四研究所 Flat azimuth driving combined device
CN104950770A (en) * 2015-06-24 2015-09-30 中国船舶重工集团公司第七二六研究所 Controllable high-speed multi-channel signal acquisition control circuit system and control method thereof
CN104950770B (en) * 2015-06-24 2018-07-06 中国船舶重工集团公司第七二六研究所 Controllable high speed multichannel signal acquisition control circuit system and its control method
CN105653384A (en) * 2015-12-30 2016-06-08 惠州市伟乐科技股份有限公司 Soft-core CPU resetting method and master-slave type system
CN108167030A (en) * 2018-01-25 2018-06-15 榆林学院 A kind of blast furnace TRT servo-control systems based on FPGA

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Granted publication date: 20111116