CN202041644U - Configurable segment correlator - Google Patents

Configurable segment correlator Download PDF

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Publication number
CN202041644U
CN202041644U CN2011200978779U CN201120097877U CN202041644U CN 202041644 U CN202041644 U CN 202041644U CN 2011200978779 U CN2011200978779 U CN 2011200978779U CN 201120097877 U CN201120097877 U CN 201120097877U CN 202041644 U CN202041644 U CN 202041644U
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China
Prior art keywords
circuit
correlator
correlation
register
configurable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2011200978779U
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Chinese (zh)
Inventor
李柬
褚孝鹏
张鹏泉
袁琳
范玉进
曹晓东
赵维兵
张波
王文亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin Cambridge Energy Saving Technology Co., Ltd.
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Tianjin Optical Electrical Communication Technology Co Ltd
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Priority to CN2011200978779U priority Critical patent/CN202041644U/en
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Publication of CN202041644U publication Critical patent/CN202041644U/en
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Abstract

The utility model relates to a configurable segment correlator for segmenting and correlating quickly captured satellite signals in multiple channels and in parallel. The configurable segment correlator comprises an FPGA (Field Programmable Gate Array) circuit. In the internal circuit structure of the FPGA circuit, a dual-port RAM (random-access memory) is respectively connected with a correlation operation circuit and a counter, and an address decoder is respectively connected with the dual-port RAM, the correlation operation circuit and the counter. In the connection relation of the correlation operation circuit, a buffer I is connected with a symbol conversion circuit through a signal register, a buffer II is connected with the symbol conversion circuit through a pseudo code register, the symbol conversion circuit is connected with an accumulator, and a timer is respectively connected with the signal register, the pseudo code register and the accumulator. The configurable segment correlator is characterized in that: the circuit is simple; the configurable segment correlator is flexible to use, and the correlation length, the number of correlation channels and the correlation interval can be optionally configured; and the scalability is high.

Description

Configurable segmentation correlator
Technical field
The utility model relates to a kind of pseudo-code stripping off device in the satellite navigation communications field, the relevant configurable segmentation correlator of catching satellite-signal fast of particularly a kind of multidiameter delay segmentation.Because its configuration is persistence length and relevant way, can improve control efficiency.
Background technology
In the satellite navigation communications field, when capture time is had requirement, need carry out multidiameter delay and handle.The mode that adopts multichannel to add up can increase system cost, reduces operation efficiency, and inconvenient compatible multi-mode satellite system.
Summary of the invention
Deficiency in view of the prior art existence, the utility model provides a kind of configurable segmentation correlator at the application of special occasions, local pseudo-code and satellite-signal are carried out the time sharing segment processing, catch for follow-up signal and to provide support, improve operation efficiency, and can carry out flexible configuration different satellite systems.
The utility model for achieving the above object, the technical scheme of being taked is: a kind of configurable segmentation correlator, it is characterized in that: comprise the FPGA circuit, the internal circuit configuration of described FPGA circuit is: dual port RAM is connected with related operation circuit, counter respectively, and address decoder is connected with dual port RAM, related operation circuit, counter respectively.
Characteristics of the present utility model are: 1, circuit is simple.2, use flexibly, can arbitrarily dispose persistence length, relevant way and related interval.3, extensibility is strong.
Description of drawings
Fig. 1 connects block diagram for the utility model circuit.
Fig. 2 is the utility model port output synoptic diagram.
Fig. 3 is that the utility model related operation circuit connects block diagram.
Embodiment
As shown in Figure 1, configurable segmentation correlator, comprise that the FPGA(scene can compile gate array) circuit, the internal circuit configuration of FPGA circuit is: dual port RAM is connected with related operation circuit, counter closed loop respectively, and address decoder is connected with dual port RAM, related operation circuit, counter respectively.This segmentation correlator can be set persistence length, relevant way and relevant spacing according to configuration information, on demand pseudo-code and signal is carried out the related operation processing, and operation result deposits in waits in the dual port RAM that the external world reads.Its persistence length, relevant way and related interval are controlled.
The external RAM that this segmentation correlator can be used as controller (as MCU) uses, and adopts non-multiplex mode to connect.Controller can be operated quick operation FPGA internal register as the operation external RAM like this.Configuration and that speed is set is fast.
As shown in Figure 2, input satellite navigation baseband digital signal, output segmentation correlation.Form the correspondence with foreign country port by address, data and read-write.Among the figure: the input of BB_IN baseband signal, the input of PN_IN pseudo-code signal, the relevant read-write of Cor_OUT output, A0~7 address signals, D0~7 data-signals, WR write signal, RD read signal.
As shown in Figure 3, the annexation of related operation circuit is: the buffer I is connected with code converter by sign register, the buffer II is connected with code converter by the pseudo-code register, code converter is connected with totalizer, and timer is connected with sign register, pseudo-code register, totalizer respectively.The pseudo-code and the signal of input at first deposit buffer in, pseudo-code and sign register are read pseudo-code and signal according to the control timing segmentation, sign changer carries out conversion according to the positive and negative symbol to signal of pseudo-code, totalizer will carry out additive operation and obtain correlation through the signal of sign reversing, according to the outwards output of timer time point, the related operation circuit with counter and drive clock as time reference.

Claims (2)

1. configurable segmentation correlator, it is characterized in that: comprise the FPGA circuit, the internal circuit configuration of described FPGA circuit is: dual port RAM is connected with related operation circuit, counter respectively, and address decoder is connected with dual port RAM, related operation circuit, counter respectively.
2. configurable segmentation correlator according to claim 1, it is characterized in that: the annexation of described related operation circuit is: the buffer I is connected with code converter by sign register, the buffer II is connected with code converter by the pseudo-code register, code converter is connected with totalizer, and timer is connected with sign register, pseudo-code register, totalizer respectively.
CN2011200978779U 2011-04-06 2011-04-06 Configurable segment correlator Expired - Fee Related CN202041644U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011200978779U CN202041644U (en) 2011-04-06 2011-04-06 Configurable segment correlator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011200978779U CN202041644U (en) 2011-04-06 2011-04-06 Configurable segment correlator

Publications (1)

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CN202041644U true CN202041644U (en) 2011-11-16

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CN2011200978779U Expired - Fee Related CN202041644U (en) 2011-04-06 2011-04-06 Configurable segment correlator

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CN (1) CN202041644U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104062646A (en) * 2014-07-03 2014-09-24 四川九洲电器集团有限责任公司 Segmented relevant unit, pseudo code range unit, and method thereof
CN111398996A (en) * 2020-03-17 2020-07-10 广州南方卫星导航仪器有限公司 Surveying and mapping satellite navigation receiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104062646A (en) * 2014-07-03 2014-09-24 四川九洲电器集团有限责任公司 Segmented relevant unit, pseudo code range unit, and method thereof
CN111398996A (en) * 2020-03-17 2020-07-10 广州南方卫星导航仪器有限公司 Surveying and mapping satellite navigation receiver

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: TIANJIN KANGQIAO ENERGY-SAVING TECHNOLOGY CO., LTD

Free format text: FORMER OWNER: TIANJIN PHOTOELECTRIC TELECOM TECHNOLOGY CO., LTD.

Effective date: 20120718

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 300211 HEXI, TIANJIN TO: 300384 NANKAI, TIANJIN

TR01 Transfer of patent right

Effective date of registration: 20120718

Address after: 300384 Tianjin City Guangdong Huayuan Industrial Zone Road No. 6, room 502-3

Patentee after: Tianjin Cambridge Energy Saving Technology Co., Ltd.

Address before: 300211 No. six, Taishan Road, Tianjin, Hexi District

Patentee before: Tianjin Photoelectric Telecom Technology Co., Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20111116

Termination date: 20150406

EXPY Termination of patent right or utility model