CN202025068U - Circuit signal detecting device - Google Patents
Circuit signal detecting device Download PDFInfo
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- CN202025068U CN202025068U CN2010205980696U CN201020598069U CN202025068U CN 202025068 U CN202025068 U CN 202025068U CN 2010205980696 U CN2010205980696 U CN 2010205980696U CN 201020598069 U CN201020598069 U CN 201020598069U CN 202025068 U CN202025068 U CN 202025068U
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Abstract
The utility model relates to a circuit signal detecting device used for detecting electrical signals. The device comprises a time sequence generating circuit, an advanced-signal output detecting circuit, a peak pulse detecting circuit, a logical error detecting circuit and a data processing circuit. A scaling circuit and a circuit-under-test are simultaneously exerted with the same test conditions and work concurrently, output time sequences of the scaling circuit and the circuit-under-test are adjusted, and accordingly output signals of the scaling circuit and the circuit-under-test are conducted with comparison tests and comparison test control. By means of the advanced-signal output detecting circuit, the peak pulse detecting circuit, the logical error detecting circuit, a low level parameter drift detecting circuit and the data processing circuit which are arranged on the device, the circuit-under-test is detected in terms of whether advanced signal output, peak pulse output, logical error output, low level parameter drift and zero level output exist or not, and accordingly correctness of output signals can be detected.
Description
Technical field
The utility model relates to a kind of circuit signal pick-up unit of electrical signal detection.
Background technology
The circuit signal test has several different methods, what have is loaded down with trivial details, and the equipment that the needs that have are powerful is very high to the correctness requirement of circuit in some occasions, and many tests are the tests at the specific output under the specific initial conditions, do not have the correctness of test signal all sidedly.
The utility model content
The utility model provides a kind of easy signal correctness pick-up unit at signal output in advance, spike, logic error, the parameter drift problem of circuit.
The technical solution of the utility model is: the circuit signal pick-up unit is by timing sequence generating circuit, shift to an earlier date the signal output detection circuit, the spike testing circuit, the logic error testing circuit, data processing circuit is formed, to design jointly with circuit-under-test, the preferred circuit input end that structure is identical and the input end of circuit-under-test are connected, preferred circuit, the output of circuit-under-test is connected with timing sequence generating circuit, the output of timing sequence generating circuit and signal output detection circuit in advance, the spike testing circuit, the logic error testing circuit, data processing circuit connects respectively, in advance the signal output detection circuit, the spike testing circuit, the output of logic error testing circuit links to each other with data processing circuit.
The signal output detection circuit is made of first sampling hold circuit, first comparer, first trigger in advance, the output of first sampling hold circuit connects the in-phase input end of first comparer, the inverting input of first comparer connects reference voltage: high level allows minimum voltage, the output terminal of first comparer is connected with the input end of first trigger, and the output of first trigger connects data processing circuit.
The spike testing circuit is made up of second sampling hold circuit, the 3rd comparer, the 3rd trigger, the output of second sampling hold circuit connects the in-phase input end of the 3rd comparer, the inverting input of the 3rd comparer connects reference voltage: high level allows maximum voltage, the output terminal of the 3rd comparer is connected with the input end of the 3rd trigger, and the output of the 3rd trigger connects data processing circuit.
The logic error testing circuit is made of the 5th, the 6th comparer, the 3rd, the 4th sampling hold circuit, the 5th, the 6th trigger, five, the output of the 6th comparer connects the input end of the 3rd, the 4th sampling hold circuit respectively, three, the output of the 4th sampling hold circuit is connected with the input end of the 5th, the 6th trigger respectively, and the output of the 5th, the 6th trigger connects data processing circuit.
For the integrality of input with make full use of components and parts, also be provided with low level parameter drift testing circuit, zero level testing circuit on the pick-up unit.The input end of low level parameter drift testing circuit, zero level testing circuit links to each other with timing sequence generating circuit with control end, and output terminal is connected with data processing circuit.
Low level parameter drift testing circuit is made up of first sampling hold circuit, second comparer, second trigger, the output of first sampling hold circuit connects the in-phase input end of second comparer, the inverting input of second comparer connects reference voltage: low level allows maximal value, the output terminal of second comparer is connected with the input end of second trigger, and the output of second trigger connects data processing circuit.
Described zero level testing circuit is made up of second sampling hold circuit, the 4th comparer, the 4th trigger, the output of second sampling hold circuit connects the in-phase input end of the 4th comparer, the inverting input of the 4th comparer connects reference voltage: low level allows maximal value, the output terminal of the 4th comparer is connected with the input end of the 4th trigger, and the output of the 4th trigger connects data processing circuit.
Circuit signal pick-up unit principle of work provided by the utility model is as described below:
By preferred circuit is applied identical test condition and concurrent working simultaneously with circuit-under-test, timing sequence generating circuit is carried out the sequential adjustment or is produced new clock signal according to the output signal of preferred circuit, circuit-under-test the output signal of preferred circuit, circuit-under-test, carry out the test of circuit-under-test output signal and the contrast of standard signal, and the clock signal that utilizes preferred circuit the to produce control that compares, test; By installing timing sequence generating circuit, signal output detection circuit, spike testing circuit, logic error testing circuit, low level parameter drift testing circuit and zero level testing circuit, data processing circuit detection circuit-under-test shift to an earlier date signal output, spike output, logic error output, low level parameter drift and zero level output in advance, thereby check out the correctness of output signal.
1, by output delay of output signal to circuit-under-test and preferred circuit, obtain the output signal of two signals and the circuit-under-test of preferred circuit output signal, these three signals are satisfied with the output signal that two signals that under normal circumstances produced by preferred circuit lag behind circuit-under-test respectively slightly in advance and slightly; These two signals that utilization is produced by preferred circuit output and by the control signal of its generation are undertaken with the comparison of circuit-under-test output signal, measure and compare and measure control, the timely processing needs of satisfy contrast, measuring and bear results.
2, utilize comparator circuit to produce by preferred circuit slightly in advance and the clock signal that lags behind circuit-under-test compare with the output signal of circuit-under-test respectively, utilize sampling hold circuit that result is relatively kept, utilize flip-flop circuit that the result that sampling keeps is kept in good time, utilize data processing circuit in time to handle comparative result, the sequential of judging circuit-under-test whether between two sequential of preferred circuit, thereby judge the correctness of output signal logic.
3, utilize sampling hold circuit to the signal of circuit-under-test output signal before preferred circuit output high level signal arrives with the sampling hold circuit maintenance of sampling, the result that sampling keeps voltage comparator and reference voltage: the minimum that high level allows, and and reference voltage: the mxm. that low level allows compares, judge whether to exist signal output in advance, low level whether to have parameter drift, greater than setting, thereby judge whether to exist the output of pulse in advance, whether low level exists parameter drift; By to the circuit-under-test output signal before preferred circuit output high level signal finishes with the sampling hold circuit maintenance of sampling, result and reference voltage that sampling keeps: maximal value and reference voltage that high level allows: the maximal value that low level allows is compared, whether the high level signal that can judge circuit-under-test output exists spike, whether there is zero level output, the correctness that the judged result of zero level output can the auxiliary judgment circuit logic.The utility model has the advantages that:
1. this device can be attached to test macro, the application system of circuit, can be in real time, parallel, synchronously, the correctness to output signal detects simply, this device circuit simplicity of design.
2. the stationary problem when helping solving circuit-under-test and preferred circuit output signal and comparing.
3. help guaranteeing the security of qualified circuit signal, find the circuit safety failure mode, the design of circuit and production technology are improved important meaning.
Description of drawings
Fig. 1 is an embodiment of the present utility model---a circuit signal pick-up unit theory diagram;
Fig. 2 is the circuit signal pick-up unit principle assumption diagram of Fig. 1;
Fig. 3 is the circuit signal pick-up unit circuit diagram of Fig. 1;
Fig. 4 is the signal timing diagram of the circuit signal pick-up unit of Fig. 3;
Fig. 5 is the circuit diagram of sampling hold circuit among the embodiment of the present utility model;
Fig. 6 is the circuit diagram of another embodiment of circuit signal pick-up unit of Fig. 1.
Among Fig. 2,3,6: E1: preferred circuit, E2: circuit-under-test: its input end is that in1, output terminal are out1; U1, U2, U3, U4 are respectively first, second, third, fourth sampling hold circuit, and its input end is that in2, output terminal are that out2, control end are ctl1; O1, O2, O3, O4, O5, O6: first to the 6th comparer adopts MAX903CAP type voltage comparator, O7: first voltage follower (adopts OPA642 type operational amplifier, inverting input and output are joined), the in-phase input end of O1, O2, O3, O4, O5, O6, O7 is in+, inverting input is in-, and output terminal is out3; D1, D2, D3, D4, D5, D6: first to the 6th trigger adopts DM74174 type d type flip flop, and input end is D, and in-phase output end is Q, and clock end is CP; CL: data processing circuit, L1, L2, Δ 1, Δ 2: signal delay line; B1: not gate, R1: resistance, B2:7432 type OR circuit, B3:89C51 single-chip microcomputer, B4:74LS86 type NOR gate circuit, N2:LED light emitting diode.G1, G2, G3, G4 reference voltage, G1 represent that high level allows minimum value, G2: the expression low level allows maximal value, and G3 represents: high level allows maximal value, and G4 represents: low level allows maximal value.
A1 among Fig. 4, A2, A3, A4, A5, A6, A7 is a clock signal, signal A1: the clock signal of directly exporting for preferred circuit E1, signal A2 is the clock signal of signal A1 after through the first voltage follower O7, signal A3 exports through the clock signal behind the signal delay line L1 for circuit-under-test E2, signal A4 for signal A2 through the clock signal behind the signal delay line L2, signal A5 is signal A2, clock signal behind signal A4 process or the door B2, signal A6 for signal A5 through the clock signal behind the not gate B1, signal A7 be among Fig. 6 signal A4 through the signal of 74LS123 type monostalbe trigger generation.
Among Fig. 5: R3, R4 resistance, O8: operational amplifier, O9: second voltage follower, O8, O9 adopt OPA642 operational amplifier, C1, C2: electric capacity, N1:NPN type triode, B5:3D03C type N-channel MOS enhancing property field effect transistor, in2: the in-phase input end of operational amplifier O8, out2: the output terminal of the second voltage follower O9, the grid of ctl1:B5.
B6:74LS123 type monostalbe trigger among Fig. 6, R5: resistance, C3: electric capacity.
Embodiment
Below in conjunction with accompanying drawing embodiment of the present utility model and principle of work are described further:
Fig. 1 is the theory diagram of circuit signal pick-up unit.The circuit signal pick-up unit is by timing sequence generating circuit, in advance signal output detection circuit, spike testing circuit, logic error testing circuit, data processing circuit are formed as shown in Figure 1, and this device is gone up low level parameter drift testing circuit, zero level testing circuit in addition.
Preferred circuit and tested circuit input end are joined, and apply identical input signal simultaneously, the output and the timing sequence generating circuit of preferred circuit and circuit-under-test are joined, the output of timing sequence generating circuit is joined with in advance signal deteching circuit, low level parameter drift testing circuit, zero level testing circuit, spike testing circuit, logic error testing circuit, data processing circuit respectively, and test and control signal are provided.And shift to an earlier date signal output detection circuit, low level parameter drift testing circuit, spike testing circuit, zero level testing circuit, and the output and the data processing circuit of logic error testing circuit join, and data processing circuit is handled input signal.
Fig. 2 is the principle assumption diagram of an embodiment of the utility model.
Referring to Fig. 2: first sampling hold circuit, first comparer, first trigger are formed signal output detection circuit in advance, first sampling hold circuit, second comparer, second trigger are formed low level parameter drift testing circuit, second sampling hold circuit, the 3rd comparer, the 3rd trigger are formed the spike testing circuit, and second sampling hold circuit, the 4th comparer, the 4th trigger are formed the zero level testing circuit.First voltage follower, signal delay line L1, signal delay line L2, signal delay line Δ 1, signal delay line Δ 2, OR circuit B2, not circuit B1 forms timing sequence generating circuit, produce test signal and control signal: A2, A3, A4, A5, A6, signal A2 wherein, signal A3, signal A4 is as test signal, send into first sampling hold circuit respectively, second sampling hold circuit, the 5th comparer, the input end of the 6th comparer, signal A2, signal A4, signal A5, signal A6, as control signal, signal A5 controls first sampling hold circuit behind signal delay line Δ 1, signal A6 controls second sampling hold circuit behind signal delay line Δ 2, signal A5 controls first trigger, second trigger, signal A6 controls the 3rd trigger, the 4th trigger, the 3rd sampling hold circuit, the 4th sampling hold circuit, signal A4 controls the 5th trigger, the 6th trigger and data processing circuit CL.
Fig. 3 is embodiment circuit diagram of signal supervisory instrument, and Fig. 4 is the sequential chart of pick-up unit shown in Figure 3, and preferred circuit and the circuit that circuit-under-test is common design, structure is identical, preferred circuit are to be proved the qualified circuit that satisfies request for utilization.Link to each other referring to the input end in1 of Fig. 3: preferred circuit E1 and the input end in1 of circuit-under-test E2, give E1 and the identical signal of E2 input, and start working simultaneously.
In conjunction with Fig. 3 and Fig. 4, timing sequence generating circuit is by signal delay line L1, L2, Δ 1, Δ 2, the first voltage follower O7, or door B2, and not gate B1 forms.The output out1 of timing sequence generating circuit and preferred circuit E1, circuit-under-test E2 joins, and the clock signal that produces Fig. 4 is signal A1, signal A2, signal A3, signal A4, signal A5, signal A6.Wherein signal A2, signal A3, signal A4 are used to measure or input signal relatively, and signal A2, signal A4, signal A5, signal A6 are control signal.
The output signal of preferred circuit E1 output terminal out1 is signal A1, the output terminal out1 of preferred circuit E1 connects the in-phase input end of the first voltage follower O7 in the timing sequence generating circuit, and the output terminal output signal A2 of the first voltage follower O7 sends into or the end of homophase input in+, the signal delay line L2 of an input end, the 5th comparer O5 of door B2.The output signal of circuit-under-test E2 behind signal delay line L1 is A3.
The end signal of signal delay line L2 is A2, other end output signal is A4, another input end of the signal A4 termination of signal delay line L2 or door B2, the input end of XOR gate B4, the inverting input in-of the 6th comparer O6, the clock end CP of the 5th trigger D5, the 6th trigger D6, the P0.6 end of single-chip microcomputer;
Or the door B2 output signal be A5, connect the input end of not gate B1, an end of signal delay line Δ 1, the clock end CP of the first trigger D1, the second trigger D2, the reset terminal ctl1 of another termination first sampling hold circuit U1 of signal delay line Δ 1.
The first sampling hold circuit U1 does not reset as long as guarantee that the first trigger D1, the second trigger D2 finish that signal to the D end remains to the Q end in signal delay line Δ 1 output.
The output signal of not gate B1 is A6, output termination the 3rd sampling hold circuit U3 of not gate B1, the reset terminal ctl1 of the 4th sampling hold circuit U4, the clock end CP of the 3rd trigger D3, the 4th trigger D4, an end of signal delay line Δ 2.The reset terminal ctl1 of another termination second sampling hold circuit U2 of signal delay line Δ 2.
The second sampling hold circuit U2 does not reset as long as guarantee that the 3rd trigger D3, the 4th trigger D4 finish that signal to the D end remains to the Q end in signal delay line Δ 2 output.
The first sampling hold circuit U1, the first comparer O1, the first trigger D1 forms signal output detection circuit in advance, the input end in2 end of the first sampling hold circuit U1 is sent in the output of circuit-under-test E2 behind delay line L1, the output terminal out2 of the first sampling hold circuit U1 connects the in+ end of the first comparer O1, the in-termination reference voltage G1 of the first comparer O1: high level allows minimum value, detect circuit-under-test E2 circuit before the control end ctl1 of the first sampling hold circuit U1 resets, existence shifts to an earlier date the output (the out2 output of the first sampling hold circuit U1 is whether greater than reference voltage G1: high level allows minimum value) of pulse, when existing, then the first comparer O1 is output as high level, the output out3 of the first comparer O1 connects the D end of the first trigger D1, the output terminal of the CP termination of the first trigger D1 or door B2, or the output signal of door B2 is A5, or the output of door B2 meets the reset terminal ctl 1 of the first sampling hold circuit U1 behind delay line Δ 1, as shown in Figure 4, when signal A5 rising edge arrives, make the input end signal of the first trigger D1 remain on the Q end, after postponing through signal delay line Δ 1, signal A5 send the ctl1 reset terminal of the first sampling hold circuit U1, controlling the first sampling hold circuit U1 resets, adjust signal delay line Δ 1 length, guarantee to finish and allow the first sampling hold circuit U1 reset again after signal to the D end keeps at the signal A5 rising edge first trigger D1 that arrives.The output Q end of the first trigger D1 links to each other with the P0.0 mouth of single-chip microcomputer B3 in the data processing circuit.
The first sampling hold circuit U1, the second voltage comparator O2 and the second trigger D2 form low level parameter drift testing circuit, the output out2 of the first sampling hold circuit U1 meets the in-phase input end in+ of the second comparer O2, the inverting input in-of the second comparer O2 meets reference voltage G2: low level allows maximal value, detect circuit-under-test E2 before the control end ctl1 of the first sampling hold circuit U1 resets, the maximal value that whether exists output level to allow greater than low level, as in greater than, output level is again that low level then exists the low level parameter drift, as the in+ of the second comparer O2 during greater than in-, the output out3 of the second comparer O2 is a high level, the output of the second comparer O2 connects the input end D end of the second trigger D2, the output terminal of the CP termination of the second trigger D2 or door B2, signal is A5, when signal A5 high level arrives, the input signal of the second trigger D2 remains on the output Q, and the P0.1 mouth of single-chip microcomputer B3 joins in the Q end of the second trigger D2 and the data processing circuit.
The second sampling hold circuit U2, tertiary voltage comparer O3 and the 3rd trigger D3 form the spike testing circuit, the output out1 of circuit-under-test E2 joins with the input end in2 of the second sampling hold circuit U2 after signal delay line L1 signal delay, the in+ end of the output out2 of the second sampling hold circuit U2 and the 3rd comparer O3 joins, the in-termination reference voltage G3 of the 3rd comparer O3: high level allows maximal value, detection is before circuit-under-test E2 circuit high level finishes, the maximal value whether level allows greater than high level, if greater than, then there is spike in explanation, then the homophase of the 3rd comparer O3 input in+ is greater than anti-phase input in-, the output ou3 of the 3rd comparer O3 presents high level, the D end of the output out3 of the 3rd comparer O3 and the 3rd trigger D3 joins, the clock end CP of the 3rd trigger D3 connects the output of B1, the output signal of not gate B1 is A6, when signal A6 high level rising edge arrives, the 3rd comparer O3 result relatively, remain in the Q end of the 3rd trigger D3, the P0.2 mouth of single-chip microcomputer joins in the Q end of the 3rd trigger D3 and the data processing circuit.When the 3rd trigger D3 has finished the signal maintenance, then the second sampling hold circuit U2 just can reset, signal A6 control second sampling hold circuit U2 after 2 time-delays of signal delay line Δ finishes and resets, and adjusts the length of Δ 2, guarantees that the 3rd trigger D3 finishes signal and keeps allowing U2 reset again.
The second sampling hold circuit U2, the 4th voltage comparator O4 and the 4th trigger D4 form the zero level testing circuit, the output out2 of the second sampling hold circuit U2 connects the in+ end of the 4th comparer O4, the in-termination reference voltage G4 of the 4th comparer O4: low level allows maximal value, detection is before circuit-under-test E2 circuit high level finishes, if output is low level, then detect the maximal value whether low level allows greater than low level, if less than, illustrate that circuit-under-test E2 is output as zero level, then the in-of the 4th comparer O4 is greater than in+, the 4th comparer O4 output out3 is a low level, the 4th trigger D4 input end D is a low level, the clock end CP of the 4th trigger D4 connects the output of not gate B1, and output signal is A6, when signal A6 signal rising edge arrives, the value of the D end of the 4th trigger D4 is stored in the Q end, the result of the comparison of the 4th comparer O4 just remains in the Q end of the 4th trigger D4, and the Q end of the 4th trigger D4 links to each other with the P0.3 mouth of single-chip microcomputer B3 in the data processing circuit.
The 5th comparer O5, the 6th comparer O6, the 3rd sampling hold circuit U3, the 4th sampling hold circuit U4, the 5th trigger D5, the 6th trigger D6 form the logic error testing circuit, the in-phase input end in+ of the inverting input in-of the 5th comparer O5, the 6th comparer O6 and the end of signal delay line L1 join, the output out1 of another termination circuit-under-test E2 of signal delay line L1; The output of the in-phase input end in+ of the 5th comparer O5 and the end of signal delay line L2, the first voltage follower O7, the input end of OR circuit B2 join; The inverting input in-of the 6th comparer O6 and the other end of signal delay line L2, the CP end of trigger D5, trigger D6, or another input end of door B2, the input end of XOR gate B4, the P0.6 mouth of single-chip microcomputer B3 joins; The output terminal out3 of the 5th comparer O5 meets the input end in2 of the 3rd sampling hold circuit U3, the 6th comparer O6 output terminal out3 meets the input end in2 of the 4th sampling hold circuit U4, the output out2 of the 3rd sampling hold circuit U3, the 4th sampling hold circuit U4, connect the input end D end of the 5th trigger D5, the 6th trigger D6 respectively, the output terminal Q end of the 5th trigger D5, the 6th trigger D6 connects P0.4, the P0.5 mouth of single-chip microcomputer in the data processing circuit respectively.
The output of the first voltage follower O7 and the inverting input of self join, output signal is A2, the end of the output of the first voltage follower O7 and signal delay line L2 joins, the other end output signal of signal delay line L2 is A4, the output signal A4 of signal delay line L2 sends into the CP end of the 5th trigger D5, the 6th trigger D6, when signal A4 rising edge arrived, the output out2 of the 3rd sampling hold circuit U3 remained in the Q end of the 5th trigger D5; The output ou2 of the 4th sampling hold circuit U4 remains to the Q end of the 6th trigger D6; The output of not gate B1 meets the reset terminal ctl1 of the 3rd sampling hold circuit U3, the 4th sampling hold circuit U4, the output signal of not gate B1 is A6, when A6 is high level, the 3rd sampling hold circuit U3, the 4th sampling hold circuit U4 reset and are output as 0, when signal A6 was low level, circuit carried out signal sampling and keeps maximum level at output terminal.Circuit-under-test E2 output termination signal delay line L1, the other end output signal of signal delay line L1 is A3, adjust signal delay line L1, signal delay line L2, make that under normal circumstances signal A3 is at signal A2, between the sequential of signal A4, the 3rd sampling hold circuit U3 then, the 4th sampling hold circuit U4 output is 1, when signal A3 not at signal A2, between the signal A4, the 3rd sampling hold circuit U3 then, it is not 1 that the 4th sampling hold circuit U4 exports rare one to, in conjunction with shifting to an earlier date the signal output detection circuit, whether the testing result of zero level testing circuit is can the decision circuitry sequential correct.
Single-chip microcomputer B3, XOR gate B4, resistance R 1, LED light emitting diode N2 form data processing circuit, single-chip microcomputer B3 is a 89C51 type single-chip microcomputer, power end high level end links to each other with resistance R 1, the input end of another termination LED light emitting diode N2 of resistance R 1, the output terminal of LED light emitting diode N2 connects the P1.0 mouth of single-chip microcomputer, the signal A4 output terminal of the input termination signal delay line L2 of XOR gate B4, the other end connects the P1.1 mouth of single-chip microcomputer B3, the middle fracture of the output order sheet of XOR gate B4
When the P1.1 of single-chip microcomputer B3 mouth is a low level, when signal A4 is low level, the singlechip interruption mouth
Output low level, the single-chip microcomputer response is interrupted, and P0 mouth data are read in single-chip microcomputer, and judge that data are wrong if single-chip microcomputer is found the P0 mouth, then the P1.0 of single-chip microcomputer B3 output 0 (the P1.0 reset signal is 1), light LED light emitting diode N2, report to the police, single-chip microcomputer has responded interruption, and P1.1 is put 1, signal A4 is that 0 XOR gate B4 is output as 1, when the high level of signal A4 arrived, XOR gate B4 was output as 0, the middle fracture of single-chip microcomputer
Be output as 0, because as long as the negative edge of signal A4 is worked, the signal A4 output terminal of signal delay line L2 connects the P0.6 mouth of single-chip microcomputer, single-chip microcomputer judges whether to handle P0 mouth data according to the value of P0.6, when being 1, need not handle P0.6 P0 mouth data, and the P1.1 mouth is changed to 0, and then XOR gate B4 is output as 1, and shielding is interrupted.The input of signal A4, P1.1 and middle fracture
The output mutual relationship sees the following form, and can realize having only when signal A4 is negative edge by the setting of P1.1 among the single-chip microcomputer B3 and the value of P0.6, and single-chip microcomputer is handled the purpose of P0 mouth data.
Fig. 5 is an embodiment of sampling hold circuit: sampling hold circuit is by resistance R 3, resistance R 4, amplifier O8, NPN type triode N1, capacitor C 1, capacitor C 2, N channel enhancement field effect transistor B5, the second voltage follower O9 constitutes, the normal phase input end of amplifier O8 and inverting input respectively with resistance R 4, resistance R 3 is joined, resistance R 4, the other end ground connection of resistance R 3, the normal phase input end of amplifier O8 is in2, the inverting input of amplifier O8 and capacitor C 1 are joined, one end of the other end of capacitor C 1 and capacitor C 2 and the emitter of triode N1, the in-phase input end of the second voltage follower O9, the drain electrode of field effect transistor B5 links to each other, the output of amplifier O8 connects base stage and the collector of triode N1, the other end of C2 and the source electrode of B5, ground joins, the voltage follower of the second voltage follower O9 for being linked to be by amplifier, inverting input links to each other with output, output terminal is out2, pulse signal is through the input end in2 of amplifier O8 input, make amplifier O8 export high level, high level makes triode N1 conducting, voltage is delivered to capacitor C 2, if field effect transistor B5 ends, capacitor C 2 voltages are held, and the voltage of maintenance is sent by the out2 end by the second voltage follower O9, field effect transistor B5 is a N channel enhancement field effect transistor, when grid when being high, the source leakage conductance is logical, and the in-phase input end of the second voltage follower O9 is 0, be output as 0, capacitor C 2 discharges simultaneously, sampling hold circuit resets, otherwise, when the B5 grid is low level, the source is leaked and is ended, capacitor C 2 chargings, and the input signal high level is held on the output terminal out2.First to fourth sampling hold circuit all can adopt this circuit in the circuit signal pick-up unit circuit diagram shown in Figure 3.
Fig. 6 is another embodiment of the present utility model, on the basis of Fig. 3, increase monostalbe trigger B6, capacitor C 3 and resistance R 5, the line that removes XOR gate B4 and be attached thereto, the signal A4 output terminal of signal delay line L2 links to each other 4 pin of monostalbe trigger B6 with the 1 pin A of monostalbe trigger B6 end
Connect the middle fracture of single-chip microcomputer B3
Monostalbe trigger B6's
The end output signal is an A7 signal among Fig. 4, when the A4 negative edge arrives, and monostalbe trigger output low level pulse signal, pulse signal send
Mouthful, the single-chip microcomputer response is interrupted, and read in P0 mouth data, and whether judged result is correct as a result according to reading in, and whether control N2 lights (the P1.0 mouth is put 1 or 0).Adjust resistance R 5 and capacitor C 3 and can regulate the output pulse width of monostalbe trigger B6.
Claims (7)
1. circuit signal pick-up unit, it is characterized in that by timing sequence generating circuit, shift to an earlier date the signal output detection circuit, the spike testing circuit, the logic error testing circuit, data processing circuit is formed, to design jointly with circuit-under-test, the preferred circuit input end that structure is identical is connected with tested circuit input end, preferred circuit, the output of circuit-under-test is connected with timing sequence generating circuit, the output of timing sequence generating circuit and signal output detection circuit in advance, the spike testing circuit, the logic error testing circuit, data processing circuit connects respectively, in advance the signal output detection circuit, the spike testing circuit, the output of logic error testing circuit links to each other with data processing circuit.
2. according to the described a kind of circuit signal pick-up unit of claim 1, it is characterized in that the signal output detection circuit is made of the first sampling maintenance, first comparer, first trigger in advance, the output of first sampling hold circuit connects the in-phase input end of first comparer, the inverting input of first comparer connects reference voltage: high level allows minimum voltage, the output terminal of first comparer is connected with the input end of first trigger, and the output of first trigger connects data processing circuit.
3. according to the described a kind of circuit signal pick-up unit of claim 1, it is characterized in that the spike testing circuit is made up of second sampling hold circuit, the 3rd comparer, the 3rd trigger, the output of second sampling hold circuit connects the in-phase input end of the 3rd comparer, the inverting input of the 3rd comparer connects reference voltage: high level allows maximum voltage, the output terminal of the 3rd comparer is connected with the input end of the 3rd trigger, and the output of the 3rd trigger connects data processing circuit.
4. according to the described a kind of circuit signal pick-up unit of claim 1, it is characterized in that the logic error testing circuit is by the 5th, the 6th comparer, three, the 4th sampling hold circuit, five, the 6th trigger constitutes, five, the output of the 6th comparer connects the input end of the 3rd, the 4th sampling hold circuit respectively, three, the output of the 4th sampling hold circuit is connected with the input end of the 5th, the 6th trigger respectively, and the output of the 5th, the 6th trigger connects data processing circuit.
5. according to the described a kind of circuit signal pick-up unit of claim 1, it is characterized in that pick-up unit also has low level parameter drift testing circuit, zero level testing circuit; The input end of low level parameter drift testing circuit, zero level testing circuit links to each other with timing sequence generating circuit with control end, and output terminal is connected with data processing circuit.
6. according to claim 1 or 5 described a kind of circuit signal pick-up units, it is characterized in that described low level parameter drift testing circuit is made up of first sampling hold circuit, second comparer, second trigger, the output of first sampling hold circuit connects the in-phase input end of second comparer, the inverting input of second comparer connects reference voltage: low level allows maximal value, the output terminal of second comparer is connected with the second trigger input end, and the output of second trigger connects data processing circuit.
7. according to claim 1 or 5 described a kind of circuit signal pick-up units, it is characterized in that described zero level testing circuit is made up of second sampling hold circuit, the 4th comparer, the 4th trigger, the output of second sampling hold circuit connects the in-phase input end of the 4th comparer, the inverting input of the 4th comparer connects reference voltage: low level allows maximal value, the 4th comparator output terminal is connected with the 4th trigger input end, and the output of the 4th trigger connects data processing circuit.
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| CN2010205980696U CN202025068U (en) | 2010-11-06 | 2010-11-06 | Circuit signal detecting device |
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| CN2010205980696U CN202025068U (en) | 2010-11-06 | 2010-11-06 | Circuit signal detecting device |
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| CN202025068U true CN202025068U (en) | 2011-11-02 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102087335A (en) * | 2010-11-06 | 2011-06-08 | 洪明 | Circuit signal detection device |
| CN102545040A (en) * | 2011-11-29 | 2012-07-04 | 厦门优迅高速芯片有限公司 | Burst mode optical power holding and monitoring circuit |
| CN103840642A (en) * | 2012-11-27 | 2014-06-04 | 美的集团股份有限公司 | Electromagnetic heating device and drive circuit thereof |
| CN107621214A (en) * | 2017-09-11 | 2018-01-23 | 芜湖市宝艺游乐科技设备有限公司 | It is a kind of to facilitate detection cold-heading ball swage measurement apparatus |
| CN107797789A (en) * | 2017-11-11 | 2018-03-13 | 北京中电华大电子设计有限责任公司 | A kind of true random number generator circuit to compare thermal noises of equal resistors that can eliminate imbalance |
| CN113970375A (en) * | 2021-09-10 | 2022-01-25 | 北方广微科技有限公司 | Time sequence protection circuit applied to uncooled infrared focal plane reading circuit |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102087335A (en) * | 2010-11-06 | 2011-06-08 | 洪明 | Circuit signal detection device |
| CN102087335B (en) * | 2010-11-06 | 2013-06-12 | 洪明 | Circuit signal detection device |
| CN102545040A (en) * | 2011-11-29 | 2012-07-04 | 厦门优迅高速芯片有限公司 | Burst mode optical power holding and monitoring circuit |
| CN103840642A (en) * | 2012-11-27 | 2014-06-04 | 美的集团股份有限公司 | Electromagnetic heating device and drive circuit thereof |
| CN107621214A (en) * | 2017-09-11 | 2018-01-23 | 芜湖市宝艺游乐科技设备有限公司 | It is a kind of to facilitate detection cold-heading ball swage measurement apparatus |
| CN107797789A (en) * | 2017-11-11 | 2018-03-13 | 北京中电华大电子设计有限责任公司 | A kind of true random number generator circuit to compare thermal noises of equal resistors that can eliminate imbalance |
| CN113970375A (en) * | 2021-09-10 | 2022-01-25 | 北方广微科技有限公司 | Time sequence protection circuit applied to uncooled infrared focal plane reading circuit |
| CN113970375B (en) * | 2021-09-10 | 2023-12-19 | 北方广微科技有限公司 | Timing sequence protection circuit applied to uncooled infrared focal plane readout circuit |
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