CN201716499U - Display device - Google Patents
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- CN201716499U CN201716499U CN2010201976704U CN201020197670U CN201716499U CN 201716499 U CN201716499 U CN 201716499U CN 2010201976704 U CN2010201976704 U CN 2010201976704U CN 201020197670 U CN201020197670 U CN 201020197670U CN 201716499 U CN201716499 U CN 201716499U
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Abstract
The utility model relates to a display device, comprising a control circuit, a first gate driver, a second gate driver and a plurality of pixel unit groups. Each pixel unit group comprises first, second, third and fourth pixel units. The control circuit respectively provides a first start signal and a second start signal to the first gate driver and the second gate driver. In the first menu period, the first start signal is quicker than the second start signal by one period therefore driving the first, second, third and fourth pixel units in turn. In the second menu period, the second start signal is quicker than the first start signal by one period, thereby driving the second, first, fourth and third pixel units in turn. The display device improves the situation that light, dark line occurs on the pixel.
Description
Technical field
The utility model relates to a kind of display, and particularly improves the display that bright dark line situation takes place picture relevant for a kind of.
Background technology
In recent years, along with semiconductor science and technology is flourish, portable electronic product and flat-panel screens product also rise thereupon.And in the middle of the type of numerous flat-panel screens, (liquidcrystal display LCD) based on advantage such as its low voltage operating, radiationless line scattering, in light weight and volume be little, has become the main flow of display product to LCD immediately.
Fig. 1 is the synoptic diagram of the Z type dot structure of existing a kind of double-gate utmost point.Fig. 2 is a kind of source electrode driver drive waveforms of Fig. 1 and the synoptic diagram of actual waveform.Please refer to Fig. 1 and Fig. 2.Among Fig. 1, the driving of arrow represent pixel order (claiming Z type mode to drive).The polarity mode of collocation source electrode driver (not illustrating) charging is an example with the type of drive of 2 lines (2line), and the polarity on the pixel can present the arrangement mode as Fig. 1.
Because being the mode that adopts pixel transistor to share source electrode line, realizes the double-gate electrode structure.Under double-gate electrode structure and Z type mode drove, the duration of charging of each pixel was shorter.When source electrode driver output transition, corresponding pixel may have the situation of undercharge, and as shown in Figure 2, last whole picture result displayed has the dark situation of bright delegation of delegation, the situation of vertical bright dark line occurs.
The reason of vertical bright dark line be liquid crystal just/counter-rotating of negative polarity.Just changeing under the negative or negative situation of becoming a full member, the source electrode driver drive waveforms is sent on the pixel, and the reaction velocity of its voltage is fast inadequately, as the source electrode driver drive waveforms of Fig. 2.Therefore, under the situation of general 2line, the pixel voltage of second same polarity just can be near target voltage.
Fig. 3 is a kind of synoptic diagram that opens beginning signal and frequency signal of Fig. 1.Fig. 4 is a kind of synoptic diagram that opens beginning signal and sweep signal of Fig. 1.Among Fig. 3, STVP1 is for opening the beginning signal, and CKV1, CKVB1 are the frequency signal of offset buffer (shift register) CH1～CHN.Offset buffer CH1～CHN can produce sweep signal to sweep trace G1～GN, as shown in Figure 4 in regular turn according to opening beginning signal STVP1.Be noted that in Fig. 1, the order that sweep trace G1～GN receives sweep signal is changeless.Promptly order is sweep trace G1 → G2 → G3 → G4....This kind type of drive can make picture bright dark line phenomenon occur.
The utility model content
The purpose of this utility model is to provide a kind of display, is intended to solve the type of drive that exists in the prior art and can makes picture the problem of bright dark line phenomenon occur.
The utility model is achieved in that a kind of display, and described display comprises:
Open the control circuit that beginning signal and second opens the beginning signal in order to produce first;
Couple many odd-numbered scan lines and described control circuit, and open the beginning signal according to first and provide sweep signal in regular turn to first gate pole driver of described odd-numbered scan lines;
Couple many even-line interlace lines and described control circuit, and open the beginning signal according to second and provide sweep signal in regular turn to second gate pole driver of described even-line interlace line;
Couple the source electrode driver of many data lines; And
A plurality of pixel cell groups, arbitrary pixel cell group comprises:
Couple first pixel cell of one of described odd-numbered scan lines;
Couple second pixel cell of one of described even-line interlace line;
Couple the 3rd pixel cell of one of described odd-numbered scan lines; And
Couple the 4th pixel cell of one of described even-line interlace line.
Described first pixel cell in each described pixel cell group, described second pixel cell, described the 3rd pixel cell and described the 4th pixel cell all are coupled to same data line.
Described first gate pole driver comprises a plurality of offset buffers, and described offset buffer couples described odd-numbered scan lines respectively, and opening the beginning signal according to described first provides sweep signal to described odd-numbered scan lines in regular turn.
Described first gate pole driver also comprises a plurality of plan offset buffers, and described plan offset buffer is respectively coupled between each described offset buffer, in order to postpone described first transmission of opening the beginning signal.
Described second gate pole driver comprises a plurality of offset buffers, and described offset buffer couples described even-line interlace line respectively, and opening the beginning signal according to described second provides sweep signal to described even-line interlace line in regular turn.
Described second gate pole driver also comprises a plurality of plan offset buffers, and described plan offset buffer is respectively coupled between each described offset buffer, in order to postpone described second transmission of opening the beginning signal.
Based on above-mentioned, the utility model has disposed many groups gate pole driver in display, thus change each gate pole driver open the beginning signal, can change the driving order of each pixel cell.Can improve the situation that bright dark line appears in pixel thus.
Description of drawings
Fig. 1 is the synoptic diagram of the Z type dot structure of existing a kind of double-gate utmost point.
Fig. 2 is a kind of source electrode driver drive waveforms of Fig. 1 and the synoptic diagram of actual waveform.
Fig. 3 is a kind of synoptic diagram that opens beginning signal and frequency signal of Fig. 1.
Fig. 4 is a kind of synoptic diagram that opens beginning signal and sweep signal of Fig. 1.
Fig. 5 is the synoptic diagram of a kind of double-gate utmost point+Z/-Z type dot structure of providing of the utility model first embodiment.
Fig. 6 is the synoptic diagram of a kind of offset buffer of providing of the utility model first embodiment.
Fig. 7 is a kind of synoptic diagram that opens beginning signal and sweep signal that the utility model first embodiment provides.
Fig. 8 is a kind of synoptic diagram that opens beginning signal and frequency signal that the utility model first embodiment provides.
Fig. 9 be a kind of+Z type of providing of the utility model first embodiment/-synoptic diagram of Z type type of drive.
Figure 10 is the synoptic diagram of a kind of double-gate utmost point+Z/-Z type dot structure of providing of the utility model second embodiment.
Figure 11 is a kind of synoptic diagram that opens beginning signal and frequency signal that the utility model second embodiment provides.
Embodiment
In order to make the purpose of this utility model, technical scheme and beneficial effect clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
The existing double-gate utmost point adopts Z type mode to drive, and can make picture produce bright dark line.In view of this, embodiment of the present utility model has disposed two groups of gate pole drivers in display, thereby changes the order that opens the beginning signal of above-mentioned two groups of gate pole drivers, can realize+the Z type/-the driven mode of Z type.Can effectively improve the situation of bright dark line thus.Elaborate embodiment of the present utility model below with reference to the accompanying drawings, accompanying drawing is for example understood example embodiment of the present utility model, wherein same the or similar element of same numeral indication.
Fig. 5 is the synoptic diagram of a kind of double-gate utmost point+Z/-Z type dot structure of providing of the utility model first embodiment.Please refer to Fig. 5, display 10 is that example describes with the LCD.Display 10 comprises source electrode driver 20, first gate pole driver 31, second gate pole driver 32, control circuit 40 and a plurality of pixel cell group (is that example describes with pixel cell group PA).Pixel cell group PA comprises a plurality of pixel cells (is that example describes with pixel cell P1～P8).First gate pole driver 31 comprises a plurality of offset buffers (is that example describes with offset buffer CH1, CH1 ', CH3, CH3 ', CH5, CH5 ', CH7, CH7 ').Second gate pole driver 32 comprises a plurality of offset buffers (is that example describes with CH2, CH2 ', CH4, CH4 ', CH6, CH6 ', CH8, CH8 ').Above-mentioned offset buffer CH1 '～CH8 ' also can be described as plan (dummy) offset buffer.
First gate pole driver 31 couples control circuit 40 and many odd-numbered scan lines (is that example describes with odd-numbered scan lines G1, G3, G5, G7).First gate pole driver 31 can receive and open beginning signal STVP1, and provides sweep signal to odd-numbered scan lines G1, G3, G5, G7 in regular turn by offset buffer CH1, CH1 ', CH3, CH3 ', CH5, CH5 ', CH7, CH7 '.Note that in the present embodiment offset buffer CH1, CH3, CH5, CH7 can be respectively in order to provide sweep signal to odd-numbered scan lines G1, G3, G5, G7, offset buffer CH1 ', CH3 ', CH5 ', CH7 ' can be used to the transmission of delaying sweep signal.
In like manner, second gate pole driver 32 couples control circuit 40 and many even-line interlace lines (is that example describes with even-line interlace line G2, G4, G6, G8).Second gate pole driver 32 can receive and open beginning signal STVP2, and provides sweep signal to even-line interlace line G2, G4, G6, G8 in regular turn by offset buffer CH2, CH2 ', CH4, CH4 ', CH6, CH6 ', CH8, CH8 '.Note that in the present embodiment offset buffer CH2, CH4, CH6, CH8 can be respectively in order to provide sweep signal to even-line interlace line G2, G4, G6, G8, offset buffer CH2 ', CH4 ', CH6 ', CH8 ' can be used to the transmission of delaying sweep signal.Below provide a kind of embodiment of offset buffer to consider and examine for haveing the knack of art technology person.
Fig. 6 is the synoptic diagram of a kind of offset buffer of providing of the utility model first embodiment.The offset buffer of Fig. 6 is that example describes with CH1.Offset buffer CH1 comprises transistor M1_1～M1_14 and capacitor C 1_1.Transistor M1_1～M1_14 for example is the N channel transistor.The offset buffer that note that Fig. 6 only is a kind of selection embodiment, and art technology person also can use alternate manner instead according to its demand and implement offset buffer.In like manner can analogize the embodiment of each offset buffer, not repeat them here.
Need one carry be, the offset buffer CHN of afterbody, its Gout end is not connected to gate line, purpose is the reset signal as upper level.The Cout of offset buffer CHN end then is input to Fv end at different levels, and purpose mainly is to allow at different levelsly in vertical closing time (vertical blanking time), guarantees that its voltage that outputs to gate line is all VGL.
Fig. 7 is a kind of synoptic diagram that opens beginning signal and sweep signal that the utility model first embodiment provides.Fig. 8 is a kind of synoptic diagram that opens beginning signal and frequency signal that the utility model first embodiment provides.Fig. 9 be a kind of+Z type of providing of the utility model first embodiment/-synoptic diagram of Z type type of drive.Please in the lump with reference to Fig. 5, Fig. 7～Fig. 9.
Signal instruction:
VGL: export each sweep trace to, be used for closing the voltage of the pixel transistor of each pixel cell.
STVP1: the enabling signal of each offset buffer in first gate pole driver 31.
CKV1: in first gate pole driver 31, one of them of two class frequency signals, CKVB1 is anti-phase with frequency signal.
CKVB1: in first gate pole driver 31, one of them of two class frequency signals, CKV1 is anti-phase with frequency signal.
STVP2: the enabling signal of each offset buffer in second gate pole driver 32.
CKV2: in second gate pole driver 32, one of them of two class frequency signals, CKVB2 is anti-phase with frequency signal.
CKVB2: in second gate pole driver 32, one of them of two class frequency signals, CKV2 is anti-phase with frequency signal.
In the present embodiment, suppose first picture during, during second picture, during the three-picture, during the 4th picture ... during being continuous pictures in regular turn.
During first picture, control circuit 40 can provide enabling signal STVP1 to first gate pole driver 31 earlier, after during one, provides enabling signal STVP2 to second gate pole driver 32 again.Note that sweep trace G1, G2, G3, G4, G5, G6, G7, G8... can receive sweep signal in regular turn.When sweep trace G1 received sweep signal, pixel cell P1, P5... can be driven.When sweep trace G2 received sweep signal, pixel cell P2, P6... can be driven.When sweep trace G3 received sweep signal, pixel cell P3, P7... can be driven.When sweep trace G4 received sweep signal, pixel cell P4, P8... can be driven.In other words, during first picture, each pixel cell of pixel cell group PA can drive in proper order with the driving of+Z type, shown in the arrow of Fig. 9.
During second picture, control circuit 40 can provide enabling signal STVP2 to second gate pole driver 32 earlier, after during one, provides enabling signal STVP1 to first gate pole driver 31 again.Note that sweep trace G2, G1, G4, G3, G6, G5, G8, G7... can receive sweep signal in regular turn.When sweep trace G2 received sweep signal, pixel cell P2, P6... can be driven.When sweep trace G1 received sweep signal, pixel cell P1, P5... can be driven.When sweep trace G4 received sweep signal, pixel cell P4, P8... can be driven.When sweep trace G3 received sweep signal, pixel cell P3, P7... can be driven.In other words, during second picture, each pixel cell of pixel cell group PA can drive in proper order with the driving of-Z type, shown in the arrow of Fig. 9.
By that analogy, during three-picture, its type of drive is identical during can first picture.During the 4th picture, its type of drive is identical during can second picture, does not repeat them here.
Comprehensively above-mentioned, present embodiment by changing enabling signal STVP 1, STVP2, can be realized+the driven mode of Z type and-Z type during continuous pictures.Therefore can make picture better evenly, can effectively improve the situation that bright dark line appears in picture.
What deserves to be mentioned is, though display has been depicted a possible kenel in the foregoing description, but it is all different for the design of display that the technical staff in the technical field should be known in each manufacturer, and therefore application of the present utility model is when being not restricted to the possible kenel of this kind.In other words, so long as during different pictures, what alternately change many group gate pole drivers opens the beginning signal, thereby realizes that different type of drive has been to have met spiritual place of the present utility model just.Below again for another embodiment so that those skilled in the art can further understand spirit of the present utility model, and implement the utility model.
In first embodiment, open among first gate pole driver 31 of Fig. 5, the embodiment of second gate pole driver 32 and Fig. 8 between beginning signal STVP1, the STVP2 every during length, only be a kind of selection embodiment, the utility model is not as limit.Have the knack of the embodiment that art technology person can change the foregoing description according to its demand.For instance, Figure 10 is the synoptic diagram of a kind of double-gate utmost point+Z/-Z type dot structure of providing of the utility model second embodiment.Figure 11 is a kind of synoptic diagram that opens beginning signal and frequency signal that the utility model second embodiment provides.Please in the lump with reference to Figure 10 and Figure 11, the display 11 of Figure 10 is similar with the display 10 of Fig. 5.Difference is, first gate pole driver 33 of the display 11 among Figure 10, second gate pole driver 34.
In the present embodiment, the quantity of first gate pole driver 33, second gate pole driver, 34 employed offset buffers is half of first embodiment, therefore can reduce hardware quantity, complexity and cost.In addition, owing to first gate pole driver 33, second gate pole driver 34 are respectively absolute construction.Present embodiment shortened open be separated by between beginning signal STVP1, the STVP2 during, every sweep trace opens Shi Jiehui and the last time of opening overlaps, and so can increase the duration of charging of pixel cell.Utilize with last one open the overlapping time and carry out preliminary filling, can be applicable on the panel of large-size.In addition, also can reach similar effect with first embodiment.
In sum, the utility model has disposed many groups gate pole driver in display, during different pictures, alternately changes the sequencing that opens the beginning signal of each gate pole driver, can change the driving order of each pixel cell.Can improve the situation that bright dark line appears in pixel thus.In addition, in embodiment of the present utility model, also can reduce the quantity of the offset buffer of gate pole driver, and shorten respectively open between the beginning signal during.So can reduce hardware quantity, complexity and cost, also can increase the duration of charging of pixel cell, make it can be applicable to large size panel.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.
Claims (6)
1. a display is characterized in that, described display comprises:
Open the control circuit that beginning signal and second opens the beginning signal in order to produce first;
Couple many odd-numbered scan lines and described control circuit, and open the beginning signal according to first and provide sweep signal in regular turn to first gate pole driver of described odd-numbered scan lines;
Couple many even-line interlace lines and described control circuit, and open the beginning signal according to second and provide sweep signal in regular turn to second gate pole driver of described even-line interlace line;
Couple the source electrode driver of many data lines; And
A plurality of pixel cell groups, arbitrary pixel cell group comprises:
Couple first pixel cell of one of described odd-numbered scan lines;
Couple second pixel cell of one of described even-line interlace line;
Couple the 3rd pixel cell of one of described odd-numbered scan lines; And
Couple the 4th pixel cell of one of described even-line interlace line.
2. display as claimed in claim 1 is characterized in that, described first pixel cell in each described pixel cell group, described second pixel cell, described the 3rd pixel cell and described the 4th pixel cell all are coupled to same data line.
3. display as claimed in claim 1, it is characterized in that, described first gate pole driver comprises a plurality of offset buffers, and described offset buffer couples described odd-numbered scan lines respectively, and opening the beginning signal according to described first provides sweep signal to described odd-numbered scan lines in regular turn.
4. display as claimed in claim 3 is characterized in that, described first gate pole driver also comprises a plurality of plan offset buffers, and described plan offset buffer is respectively coupled between each described offset buffer, in order to postpone described first transmission of opening the beginning signal.
5. display as claimed in claim 1, it is characterized in that, described second gate pole driver comprises a plurality of offset buffers, and described offset buffer couples described even-line interlace line respectively, and opening the beginning signal according to described second provides sweep signal to described even-line interlace line in regular turn.
6. display as claimed in claim 5 is characterized in that, described second gate pole driver also comprises a plurality of plan offset buffers, and described plan offset buffer is respectively coupled between each described offset buffer, in order to postpone described second transmission of opening the beginning signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201976704U CN201716499U (en) | 2010-05-19 | 2010-05-19 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201976704U CN201716499U (en) | 2010-05-19 | 2010-05-19 | Display device |
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| CN201716499U true CN201716499U (en) | 2011-01-19 |
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| CN2010201976704U Expired - Fee Related CN201716499U (en) | 2010-05-19 | 2010-05-19 | Display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943075A (en) * | 2013-01-23 | 2014-07-23 | 联咏科技股份有限公司 | Gate driving circuit and gate line driving method for display panel |
| CN108445687A (en) * | 2015-06-30 | 2018-08-24 | 上海天马微电子有限公司 | A kind of array substrate, display panel and liquid crystal display device |
| WO2020093604A1 (en) * | 2018-11-09 | 2020-05-14 | 惠科股份有限公司 | Display panel and driving method therefor |
-
2010
- 2010-05-19 CN CN2010201976704U patent/CN201716499U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103943075A (en) * | 2013-01-23 | 2014-07-23 | 联咏科技股份有限公司 | Gate driving circuit and gate line driving method for display panel |
| CN108445687A (en) * | 2015-06-30 | 2018-08-24 | 上海天马微电子有限公司 | A kind of array substrate, display panel and liquid crystal display device |
| WO2020093604A1 (en) * | 2018-11-09 | 2020-05-14 | 惠科股份有限公司 | Display panel and driving method therefor |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: CPT TECHNOLOGY (GROUP) CO., LTD. Free format text: FORMER OWNER: CPT DISPLAY TECHNOLOGY SHENZHEN LTD. Effective date: 20130704 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 518000 SHENZHEN, GUANGDONG PROVINCE TO: 350000 FUZHOU, FUJIAN PROVINCE |
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| TR01 | Transfer of patent right |
Effective date of registration: 20130704 Address after: 350000, No. 6 West Road, Mawei District, Fujian, Fuzhou Patentee after: CPT DISPLAY TECHNOLOGY (SHENZHEN)CO., LTD. Patentee after: Chunghwa Picture Tubes Ltd. Address before: 518000, Guangming hi tech Industrial Park, Shenzhen, Guangdong, No. 9, Ming Tong Road, Baoan District Patentee before: CPT Display Technology Shenzhen Ltd. Patentee before: Chunghwa Picture Tubes Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110119 Termination date: 20180519 |