CN201673908U - Embedded passive device wafer-level chip size packaging structure - Google Patents
Embedded passive device wafer-level chip size packaging structure Download PDFInfo
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- CN201673908U CN201673908U CN2010202255981U CN201020225598U CN201673908U CN 201673908 U CN201673908 U CN 201673908U CN 2010202255981 U CN2010202255981 U CN 2010202255981U CN 201020225598 U CN201020225598 U CN 201020225598U CN 201673908 U CN201673908 U CN 201673908U
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Abstract
The utility model relates to an embedded passive device wafer-level chip size packaging structure and belongs to the field of semiconductor packaging. The packaging structure comprises a chip (101). The surface of the chip (101) is coated with a re-passivation layer (106). The re-passivation layer (106) is provided with one or more metal wiring layers on which passive devices are formed. The surface of the uppermost metal wiring layer is covered with a metal wire surface protection layer (107). The embedded passive device wafer-level chip size packaging structure of the utility model has the advantages of small occupied packaging space and high precision of the passive devices.
Description
(1) technical field
The utility model relates to a kind of wafer-level package structure, belongs to the semiconductor packages field.
(2) background technology
In electronic circuit, need active device and passive device collaborative work to realize certain electric function usually.In traditional encapsulation, these passive devices all are to mount in the circuit board as discrete device usually.This assembling mode not only takies encapsulated space, and its assembly cost is also than higher.
Along with development of semiconductor, working frequency of chip is more and more higher, and (as radio-frequency devices) also constantly appears in new high-frequency element, and be corresponding, also needs more high-precision passive device and cooperate high-frequency element to realize its function.Such as, for radio frequency (RF) device, need add an accurate inductance of inductance value, and realize the input and output coupling, thereby make radio-frequency devices have higher performance by loop resonance generation build-out resistor.The packaged type of main flow is that the shortcoming of this packaged type is with high-frequency element and passive device discrete package at present:
1) encapsulated space that takies is big, can't satisfy the requirement of portable product small size encapsulation.
2) the passive device precision is not enough, and influenced greatly by encapsulating structure, needs loaded down with trivial details adjustment process.
3) discrete package, the assembly cost height.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, passive device is embedded into the functional chip surface by the wafer level packaging mode, the low-cost embedded passive device disc grade chip size encapsulating structure that a kind of encapsulated space that takies is little, the passive device precision is high is provided.
The purpose of this utility model is achieved in that a kind of embedded passive device disc grade chip size encapsulating structure, comprise chip, be coated with one deck passivation layer again at chip surface, passivation layer is provided with one deck or forms the metal wiring layer of passive device more than one deck again, be provided with dielectric layer between the different metal wiring layers, be electrically connected by the through hole on the dielectric layer between between the different metal wiring layers; In the superiors' metal wiring layer surface coverage layer of metal line sealer is arranged.Above-mentioned each layer all is the processing mode preparation by wafer level.
The beneficial effects of the utility model are:
1), can reduce final encapsulation volume after passive device being integrated into chip surface.
2), owing to adopted photoetching process, can obtain the passive device of high accurancy and precision, can realize other electric capacity precision of other inductance of nanohenry level and pico farad level.
3), adopt wafer level integrated, and compatible mutually with present projection technology, cost is low.
4) signal transmission distance is short, can satisfy the high frequency demand.
(4) description of drawings
Fig. 1 is the structural representation of the utility model embodiment 1.
Fig. 2 is the A-A cut-away view of Fig. 1.
Fig. 3 is the structural representation of the utility model embodiment 2.
Fig. 4 is the B-B cut-away view of Fig. 3.
(5) embodiment
Embodiment 1:
Referring to Fig. 1 and Fig. 2, Fig. 1 is the structural representation of the utility model embodiment 1.Fig. 2 is the A-A cut-away view of Fig. 1.By Fig. 1 and Fig. 2 as can be seen, the utility model embedded passive device disc grade chip size encapsulating structure, comprise chip 101, in chip 101 surface coated one deck passivation layer 106 is again arranged, passivation layer 106 is provided with one deck or (is one deck among the figure) more than one deck metal wiring layer---the wire coil 104 that forms passive device again, wire coil 104 is between each chip terminal 102 of chip 101, and the lead terminal 105 of wire coil 104 is connected on the chip terminal 102 of described chip by wiring metal line 103 again.
Embodiment 2:
Referring to Fig. 3 and Fig. 4, Fig. 3 is the structural representation of the utility model embodiment 2.Fig. 4 is the B-B cut-away view of Fig. 3.By Fig. 3 and Fig. 4 as can be seen, embodiment 2 is with the difference of embodiment 1: the metal wiring layer that forms passive device is a metal wire 108, links to each other with outside line at the lead terminal 105 place's growing metal projections or the metal salient point of this metal wire 108.
Have more than one deck as metal wiring layer, be provided with dielectric layer between the then different metal wiring layers, be electrically connected by the through hole on the dielectric layer between the different metal wiring layers; In the superiors' metal wiring layer surface coverage layer of metal line sealer 107 is arranged.
Described passivation layer again 106, dielectric layer and metal wire sealer 107 can be polyimides (Polyimide) or benzocyclobutane resin (BCB).Every layer of metal wiring layer can (but being not limited to) be the stacked of titanium, copper, gold, nickel or iron-nickel alloy or above two or more metals.Form different passive devices by preparing different metal wiring layers.Passivation layer 106, metal wiring layer and metal wire sealer 107 all are to adopt the wafer level packaging mode to form again.
Described chip terminal 102 is soldered ball or metal salient point structure.
Its implementation procedure is:
Step 1, at the crystal column surface coating one deck that comprises functional chip 101 passivation layer 106 again, and chip terminal 102 openings that will need to connect outside line by photolithographicallpatterned make its exposure.
Step 2, deposit plating seed layer by modes such as sputter or physics vapor phase depositions at whole crystal column surface on 106 surfaces of passivation layer again.
Step 3, make photo etched mask by modes such as photoetching, form target passive device figure at the plating seed laminar surface.
Step 4, the wafer that will have a photo etched mask are electroplated, and electroplate the back and remove photo etched mask and also erode inactive area Seed Layer metal, the final passive device that will obtain that forms.
Step 5, on the metallic circuit figure armor coated 107 (or dielectric layers), and will need the metal gasket place opening that goes between by photolithographicallpatterned.
Step 6, with thinning back side of silicon wafer, and cut into the single chip size packages body that contains the embedded passive device.
If preparation bilayer or multilayer integrated passive devices repeat above step 2 to step 5.
Claims (5)
1. embedded passive device disc grade chip size encapsulating structure; comprise chip (101); it is characterized in that: one deck passivation layer (106) is again arranged in described chip (101) surface coated; passivation layer (106) is provided with one deck or the above metal wiring layer that forms passive device of one deck again; in the superiors' metal wiring layer surface coverage layer of metal line sealer (107) is arranged, above-mentioned each layer is to form by the wafer level packaging mode at the crystal column surface that includes chip.
2. a kind of embedded passive device disc grade chip size encapsulating structure according to claim 1, it is characterized in that described metal wiring layer has more than one deck, be provided with dielectric layer between the different metal wiring layers, be electrically connected by the through hole on the dielectric layer between the different metal wiring layers.
3. a kind of embedded passive device disc grade chip size encapsulating structure according to claim 1 and 2, the lead terminal (105) that it is characterized in that described passive device is connected on the chip terminal (102) of described chip by wiring metal line (103) again.
4. a kind of embedded passive device disc grade chip size encapsulating structure according to claim 3 is characterized in that described chip terminal (102) is soldered ball or metal salient point structure.
5. a kind of embedded passive device disc grade chip size encapsulating structure according to claim 1 and 2 is characterized in that the lead terminal (105) of described passive device links to each other with outside line by metal coupling or metal salient point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202255981U CN201673908U (en) | 2010-06-10 | 2010-06-10 | Embedded passive device wafer-level chip size packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202255981U CN201673908U (en) | 2010-06-10 | 2010-06-10 | Embedded passive device wafer-level chip size packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201673908U true CN201673908U (en) | 2010-12-15 |
Family
ID=43331316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010202255981U Expired - Lifetime CN201673908U (en) | 2010-06-10 | 2010-06-10 | Embedded passive device wafer-level chip size packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201673908U (en) |
-
2010
- 2010-06-10 CN CN2010202255981U patent/CN201673908U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101215 |