CN201657223U - VLSI (Very Large Scale Integrated) system structure of JPEG (Joint Photographic Experts Group) image decoder - Google Patents
VLSI (Very Large Scale Integrated) system structure of JPEG (Joint Photographic Experts Group) image decoder Download PDFInfo
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Abstract
The utility model discloses a VLSI (Very Large Scale Integrated) system structure of a JPEG (Joint Photographic Experts Group) image decoder, which mainly comprises an input FIFO (First Input First Output) module, a header code stream analysis module, an entropy decoding module, a dequaztization module, a reverse zigzag conversion module, an inverse discrete cosine transform module, a desampling module, a color gamut conversion module and a display module. In the utility model, the assembly line design is used on the whole design to simultaneously process a plurality of images; a mode of multibyte buffer and long feedback of decoding words is used for the huffman decoding in the entropy decoding module to improve the running efficiency of an huffman decoding module; the non-zero coefficient data input is realized by adding a coefficient to be decoded into the inverse discrete cosine transform module for counting display and combining a module data ending mark method, so that the period of data input of a single decoding module is greatly shortened, the decoding speed of decoding is effectively improved and the whole decoding speed is well improved. By simulation verification, the utility model can achieve the decoding effect of 60fps/s under the resolution of 800*600 at the clock frequency of 100MHz.
Description
Technical field
The utility model belongs to digital image processing field, relates to VLSI system configuration and its implementation of a kind of jpeg image decoder.Relating in particular to the hardware that adopts Verilog HDL language to realize jpeg decoder realizes.
Background technology
JPEG full name is Joint Photographic Experts Group (JPEG (joint photographic experts group)), and it is one and is engaged in the committee that the still image compression is formulated under ISO (ISO).It has made the first cover GB still image compression standard ISO 10918-1, is called for short JPEG.
Joint Photographic Experts Group comprises multiple different compress mode, and wherein the base pressure compression process has obtained using the most widely.Most of present video compression technologies (as MJPEG, MPEG-1/2) have all adopted the base pressure compression process of JPEG.Jpeg image has a wide range of applications in current multimedia technology.Utilize it, can when significantly improving compression efficiency (25: 1), obtain the better image effect, thereby can significantly reduce in storage and required memory space and the bandwidth of transmit image data.
Along with the development of technology in recent years, portable type electronic product more and more comes into one's own, and this just objectively has higher requirement to the decode rate and the effect of jpeg image file.The JPEG decoding process mainly contains three kinds, and the one, traditional pure software decoding, the 2nd, DSP realizes by MCU control, the 3rd, realize by special-purpose decoding chip.Because the third mode has very big price advantage with respect to other two kinds, makes that in portable type electronic product now, special-purpose decoding chip is becoming main flow.On the existing market special-purpose decoding chip great majority all by foreign vendor design and make, its optimized Algorithm of the homemade chip of minority and design also all are covert.The bottleneck of restriction jpeg image decode rate mainly concentrates on huffman decoding and these two parts of IDCT (inverse discrete cosine transformation) in the standard.Wherein huffman is decoded as elongated runs decoding, and IDCT then once needs 64 coefficients just can finish once calculating.In order to solve an above-mentioned difficult problem, scheme generally adopts the mode of parallel module to handle now, but has caused the expansion of chip area so inevitably, thereby makes the cost of chip increase greatly.
The utility model content
The purpose of this utility model is to solve the weak point on the existing decoding chip design, a kind of clear in structure is provided, speed of service piece, can be at a high speed, effectively jpeg image file is compressed VLSI system configuration and its implementation that to save the jpeg image decoder of chip area simultaneously.
For achieving the above object, the utility model adopts following technical scheme:
A kind of VLSI system configuration of jpeg image decoder, this implementation method may further comprise the steps:
Step1: from the bit data flow of outside input, at first enter into input FIFO, a code stream analyzing module is resolved according to the JFIF file format the dateout of input buffer then;
Step2: after a code stream analyzing is intact, enter into the entropy decoder module;
Step3: after finishing the entropy decoding, the nonzero coefficient that obtains is carried out the de-quantization operation;
Step4: after finishing de-quantization, enter into anti-zigzag converter unit;
Step5: after finishing anti-zigzag conversion, the nonzero coefficient that obtains and the position (coeff_cnt) of current coefficient 64 parameters in module are input to IDCT inverse discrete cosine transformation module together, carry out inverse discrete cosine transformation;
Step6:, obtained the image information that original process reduces the YCbCr colour gamut of resolution through behind the idct transform;
Step7:, obtained the Y of each pixel, Cb, Cr component through separating sampling; At the Y that has obtained each pixel, Cb, behind the Cr component, with the Y of each pixel, Cb, the value of Cr component is converted to R, G, the value of B component.
In described step1, a code stream analyzing module has adopted dual memory, is used for storing the various information that comprise in the code stream; And adopt a code stream flag bit 0 or 1 code stream of following in the processing, by judging the flag bit of current processing code stream, with deciding the wherein one group of data that adopt in the dual memory to decode.
Dual memory application is in huffman desorption coefficient memory and quantization parameter memory; In resolving a code stream process, adopt the 0-1 conversion of highest address bit to realize separating two groups of storages from the huffman desorption coefficient of two width of cloth images with from the quantization parameter of two width of cloth images, and in the decoding use, adopt the mode of code stream flag bit, realize reading of correct coefficient.
In described step1,96bits buffering shift register is adopted in the decoding for huffman in the entropy decoding, and according to decoded data length respectively with the rd_word of code word size 16bits, the rd_byte of code word size 8bits, code word size is put high level less than the rd_bits of 8bits, feed back to 96bits buffering shift register, make it read in new isometric valid data.
In described Step5, at the input of IDCT inverse discrete cosine transformation module, follow non-zero output 8bit counter to be decoded, be used for representing the position of current nonzero coefficient in whole module 64 input coefficients to be decoded.
In described step7, conversion formula is:
R＝Y+1.402·(Cr-128)
G＝Y-0.34414·(Cb-128)-0.71414·(Cr-128)
B=Y+1.772 (Cb-128) is R wherein, and G, B have represented the redness of pixel respectively, green and blue component; Y, Cb, Cr have represented light tone component and two chromatic components of pixel respectively; For the data that RGB is obtained are positive number, the chromatic component on equation the right has all deducted 128.
A kind of VLSI system configuration of jpeg image decoder has adopted the design of streamline, comprises a code stream analyzing module, the de-quantization module, entropy decoder module, anti-zigzag conversion module, IDCT inverse discrete cosine transformation module is separated sampling module, the color gamut conversion module.From the bit data flow of outside input, at first via entering a code stream analyzing module after the input FIFO buffering; After a code stream analyzing was finished, the output stream of importing FIFO subsequently entered entropy decoder module (having called the HT coefficient that a code stream analyzing module produces in this module implementation); The decoded data of entropy enter into de-quantization module (having called the QT coefficient that a code stream analyzing module produces in this module implementation); Data flow behind the de-quantization enters anti-zigzag conversion module, carries out anti-zigzag conversion; After finishing anti-zigzag conversion, enter IDCT inverse discrete cosine transformation module; Behind the IDCT inverse discrete cosine transformation, obtain the image information of YCbCr colour gamut; Image information is separated sampling (having called the sample mode that a code stream analyzing module produces in this module implementation) after entering and separating sampling module; The information of separating after the sampling enters the color gamut conversion module, carries out after colour gamut changes; Enter display module (in this module implementation, having called the width and the elevation information of the image of a code stream analyzing module generation).
Introducing front end data effective marker and rear module idle marker between two continuous modules arbitrarily, under synchronised clock control, when to have only the both be effective, just understanding and carry out transfer of data at two intermodules.
The beneficial effects of the utility model are: no matter in design, adopt The pipeline design, cooperate the dual reservoir designs of a code stream, be the data of sub-picture the inside, and still the data of two width of cloth images can be similar to the processing that realizes that data are not stagnated.In addition, because in the input system of IDCT module, considerable a part of coefficient is zero, therefore after removing unnecessary zero coefficient, has accelerated processing speed of data greatly.By top design, when not passing through to increase parallel module, do not promoting decode rate, approximate being equal to of its effect adopted when walking abreast module, thereby reduced chip area, greatly reduce chip cost.
Description of drawings
Fig. 1 is overall system design figure;
Fig. 2 is a code stream analyzing location mode transition diagram;
Fig. 3 is various sections a identifier in the JFIF form;
Fig. 4 is anti-zigzag conversion ordering chart;
Fig. 5 is anti-zigzag conversion coefficient sequential counting conversion figure;
Fig. 6 is two-dimentional IDCT modular system structure chart;
Fig. 7 is the multiply-add operation structural circuit figure in the one dimension IDCT module;
Fig. 8 is a JPEG sample mode schematic diagram;
Wherein, among Fig. 1,1 input fifo module, 2 code stream analyzing modules, 3 entropy decoder modules, 4 de-quantization modules, 5 anti-zigzag conversion modules, 6IDCT inverse discrete cosine transformation module, 7 separate sampling module, 8 color gamut conversion modules, 9 display modules.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is described further.
At first the overall process of present embodiment is simply described in conjunction with Fig. 1.Among Fig. 1, HT has represented the huffman table, and QT has represented quantization table.What begin most to import from the outside is the data flow of 8 bits, at first enters into input fifo module 1, and the dateouts of 2 pairs of inputs of code stream analyzing module fifo module 1 are resolved according to the JFIF file format then.In this process, the state machine transition diagram of employing as shown in Figure 2.A code stream that adopts the jpeg file of JFIF form is (but be not the section of being) all that is divided into that one by one section stores, and the beginning of each section has the identifier of two byte longs.First byte of each identifier all is hexadecimal 0xFF.Second byte be according to the difference of data in the present segment, corresponding separately value separately.At first, state machine is in initial state, and whether the byte that detects input is 0xFF.If not, keep initial state to wait for the arrival of next byte, if 0xFF, state transitions is to a back byte that reads identifier.According to the difference of this byte value, jump to different states.And each section read finish after, get back to initial state, wait for the arrival of next section.When reading the SOS section, parse the code stream that just really enters into data representing image after the information of SOS section this moment always.And state machine placed idle condition.After eob signal (sub-picture decoding end mark position) is put height, get back to initial state, wait for the arrival of the image that next width of cloth is new.Fig. 3 has provided the implication of the different sections of different identification sign indicating number representative.
In addition in order to realize that the information that a code stream analyzing goes out has all adopted dual memory to store to handling different images the time before and after two width of cloth.Promptly add 1 bit again in the highest order of storage address.Utilize this 1 bit to be changed to 0 or 1 and store the different image information that goes out from two width of cloth image analysis respectively.In the process of code stream decoding, thereupon in streamline together the motion the picture flag bit that also comprises a bit.Utilize this flag bit, can in decode procedure, correctly select to use quantization table (QT) or Huffman table (HT) to wait other information from two width of cloth different images.
The jpeg image data are input to entropy decoder module 3 after cushioning via input fifo module 1.The entropy decoding has comprised huffman decoding and runs decoding and variable length decoding in the Joint Photographic Experts Group.At first,, construct the minimum code stream of 1-16 length, several characteristics that its aufbauprinciple is mainly encoded according to normal form huffman according to a number of the code word of the 1-16 length that code stream analyzing DHT section obtains:
(1) length is that first code word f (N) of N can be last code word of N-1 from length, that is: f (N)=2 (f (N-1)+1), and wherein, f (N-1) is last code word of N-1 length.
(2) code word of equal length must be the binary system description of continuous integral number.If that is: f (N) is first code word of N for length, then other length are that the code word of N then is f (N)+1, f (N)+2, f (N)+3 or the like.
(3) first coding of code word size minimum is started from scratch.
According to three characteristics recited above, be encoded to zero (suppose that this moment, length was i) with first of code word size minimum, then,, set 16 bit counter cnt1 according to (2) bar characteristic, on zero basis, add 1 successively.After treating that length is whole generation of coding of i, counter is added 1, and move to left one, promptly obtained the minimum code stream of (i+1) length.And the like, thereby set up the code stream of all lengths and code word huffman codeword table one to one.After the buffering shift register internal data of wait 96bits is effective, compare with minimum code stream successively according to code word size order from small to large by comparator according to the order from the high byte to the low byte, when the code stream of M bit long minimum code stream greater than the M bit long, but the code stream of M+1 bit long determines that current code stream length is M (this moment, the XOR result by comparator realized) during less than the minimum code stream of M+1 length.According to the size of M, control rd_word, rd_byte, the value of rd_bits, and feed back to the control section of the long buffering shift register of 96bits, make it read in new M length Bit data.After definite current code stream length is M, the current code stream of M bit and the minimum code word of M bit to be subtracted each other, the data that obtain are address offset amount addr_over.After address offset amount addr_over being added the address of the minimum code stream addr_M of M bit, obtain new address.Read the memory cell (SRAM) of storing the huffman codeword table according to new address, will obtain decoded 8bit code word.According to the code word that obtains, high 4 bits can be determined the number of current coefficient front end zero, and low 4 bits represent that the rear end represents the code stream length of current coefficient.To obtain high 4 Bit datas+1, and by the stack of counter coeff_cnt2 accumulative total, like this, the size of this counter values (0-63) has been represented the position of coefficient in current 8*8 decoder module that obtains after the decoding.With the numerical value of counter follow export together by the parameter that obtains after the low 4 bits decoding after, the nonzero coefficient in 64 coefficients of a module can be removed.Because the coefficient of this moment is a frequency coefficient, wherein includes a large amount of zero coefficients, by this measure, has reduced the transfer of data of quite a few, thereby has improved decode rate greatly.
After finishing the entropy decoding, the nonzero coefficient that obtains enters de-quantization module 4 and carries out the de-quantization operation, and at this moment, each nonzero coefficient all is accompanied by the numerical value coeff_cnt2 of its order in module of expression.Therefore with the address signal of coeff_cnt2, just can will read out with nonzero coefficient corresponding quantitative coefficient easily as the memory of storage quantization table.Output to the output of multiplier, quantization parameter and frequency domain parameter are multiplied each other, thereby finish the operation of de-quantization.
After finishing de-quantization, enter into anti-zigzag conversion module 5.By this conversion, 64 frequency coefficients will arranging by serial order are combined into the module of a 8*8 according to the mode shown in arrow among Fig. 4.Owing in the design, do not export 64 frequency coefficients in order successively, but adopt the adjoint representation frequency coefficient in 64 modes in the positional information of module, therefore the data that obtain behind de-quantization have only non-zero, so, herein, only need according to the corresponded manner among Fig. 5, the value of the coeff_cnt2 that each nonzero coefficient is followed is transformed into coeff_cnt according to corresponding relation and gets final product.Corresponding relation as shown in Figure 5, wherein the periphery is the value of coeff_cnt, inner 8*8 module boldface letter is the value of coeff_cnt2.
After finishing anti-zigzag conversion, nonzero coefficient and the coeff_cnt that obtains is input in the IDCT inverse discrete cosine transformation module 6, carry out inverse discrete cosine transformation.Its modular system framework as shown in Figure 6.In system architecture, two-dimentional idct transform is finished by carrying out twice one dimension idct transform.When design one dimension idct transform, adopted Fully-pipelined mode to design simultaneously.In the 1D-IDCT module, if the frequency coefficient of a decoder module of each clock cycle input, these coefficients are fed to one 8 bit width, the shift register of the 8 byte degree of depth, 8 all after dates of every like this mistake, shift register all will be exported the data line in the frequency coefficient matrix.Be the Z among Fig. 7
InWith the data line of displacement output, i.e. (Z
0K～Z
7K) be input to multiply-add operation element circuit data shown in Figure 7.Each all after date Z like this
OutAll will export the data after the computing, these data are the data behind the 1D-IDCT.Among Fig. 71,2,3,4,5,6,7,8 have represented through 8 cosine coefficient sequences after quantizing.Its data are as follows,
Among Fig. 71 represented first row, and 2 have represented the 2nd row, and the like, 8 have represented eighth row.
The storage of 1D-IDCT is cushioned transpose memory to coefficient.In this memory,, realize the transposition when data are read successively by reading the multiple saltus step of address.The dateout that coefficient is cushioned transpose memory, is input to shown in Figure 7 taking advantage of and adds in the circuit equally through one 8 bit width according to primary mode behind the shift register of the 8 byte degree of depth, carry out one dimension idct transform, the Z that obtains once more once more
OutBe the dateout of finishing behind the 2D-IDCT, but in the 2nd 1D-IDCT process among Fig. 71,2,3,4,5,6,7,8 these 8 cosine coefficient sequences had.As follows
Through behind the idct transform, obtained the image information that original process reduces the YCbCr colour gamut of resolution.In Joint Photographic Experts Group, sample mode commonly used has three kinds, and as shown in Figure 8, wherein * number represented the sampled point at the Y component, and zero represented the sampled point of Cb and Cr." 4:2:0 " mode wherein is to get the sampled point of the mean value of the Cb of four pixels in the block of pixels of a 2*2 as 1 Cb in sampling process, gets the sampled point of the mean value of the Cr of four pixels in the block of pixels of a 2*2 as 1 Cr; " 4:2:2 " mode is to get the sampled point of the mean value of the Cb of two pixels in the block of pixels of a 2*1 as 1 Cb in sampling process, and the mean value of getting the Cr of two pixels in the block of pixels of a 2*1 is as 1 Cr; " 4:4:4 " mode then is to get the Cb of each pixel and Cr Cb and the Cr as current pixel point.The process of separating sampling for " 4:2:0 " mode be exactly the mean value of the Cr of four pixels the block of pixels of the 2*2 that will obtain from the IDCT module and Cb as the Cb of 4 pixels in this block of pixels itself and the value of Cr, make each pixel that its complete YCbCr component all be arranged; The mean value that for " 4:2:2 " mode is exactly the Cb of two pixels the block of pixels of the 2*1 that will obtain from the IDCT module and Cr is as the Cb of 2 pixels in the block of pixels itself and the value of Cr, makes each pixel that its complete YCbCr component all be arranged; Then need not to separate sampling for " 4:4:4 " mode.Through after separating sampling module 7, just obtained the Y of each pixel, Cb, Cr component.
At the Y that has obtained each pixel, Cb, behind the Cr component, the image information of YCbCr colour gamut enters color gamut conversion module 8, transformational relation according to the following equation just can be with the Y of each pixel, Cb, and the value of Cr component is converted to R, G, the value of B component, and then enter display module 9 and show.So far, a kind of function of VLSI system of jpeg image decoder is all finished.
R＝Y+1.402·(Cr-128)
G＝Y-0.34414·(Cb-128)-0.71414·(Cr-128)
B＝Y+1.772·(Cb-128)
R wherein, G, B have represented the redness of pixel respectively, green and blue component.Y, Cb, Cr have represented light tone component and two chromatic components (for the data that RGB is obtained are positive number, the chromatic component on equation the right has all deducted 128) of pixel respectively.
Claims (1)
1. the VLSI system configuration of a jpeg image decoder comprises the input fifo module, entropy decoder module, de-quantization module, anti-zigzag conversion module, the IDCT inverse discrete cosine transformation module that connect successively, separates sampling module, color gamut conversion module, display module; The input fifo module, the entropy decoder module, the de-quantization module is separated sampling module and display module and also is connected respectively to a code stream analyzing module.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101790094A (en) * | 2010-03-19 | 2010-07-28 | 山东大学 | VLSI system structure of JPEG image decoder and realization method thereof |
| CN107924554A (en) * | 2015-08-26 | 2018-04-17 | 苹果公司 | To the multi-speed processing of view data in image processing pipeline |
| CN109274973A (en) * | 2018-09-26 | 2019-01-25 | 江苏航天大为科技股份有限公司 | Fast video coding/decoding method on embedded-type ARM platform |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101790094A (en) * | 2010-03-19 | 2010-07-28 | 山东大学 | VLSI system structure of JPEG image decoder and realization method thereof |
| CN101790094B (en) * | 2010-03-19 | 2013-01-30 | 山东大学 | VLSI system structure of JPEG image decoder and realization method thereof |
| CN107924554A (en) * | 2015-08-26 | 2018-04-17 | 苹果公司 | To the multi-speed processing of view data in image processing pipeline |
| CN107924554B (en) * | 2015-08-26 | 2021-09-10 | 苹果公司 | Multi-rate processing of image data in an image processing pipeline |
| CN109274973A (en) * | 2018-09-26 | 2019-01-25 | 江苏航天大为科技股份有限公司 | Fast video coding/decoding method on embedded-type ARM platform |
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