CN201562271U - Computer system - Google Patents
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- CN201562271U CN201562271U CN2009202681971U CN200920268197U CN201562271U CN 201562271 U CN201562271 U CN 201562271U CN 2009202681971 U CN2009202681971 U CN 2009202681971U CN 200920268197 U CN200920268197 U CN 200920268197U CN 201562271 U CN201562271 U CN 201562271U
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- computer system
- output
- control module
- south bridge
- bridge chip
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Abstract
A computer system comprises a basic input and output system, a south bridge chip, a control unit and a system state indicator lamp; matching operation of the basic input and output system, the south bridge chip and the control unit drives the system state indicator lamp to display the electrifying state of each voltage of the system; and the system state indicator lamp could indicate the error state in the power-on self test process after the electrifying process of each voltage is finished. Thereby, it is unnecessary for additionally installing devices on the computer system mainboard to display whether the electrifying state of each voltage achieves the preset requirement; the hardware resource of the conventional system mainboard is fully used so as to save the design cost and not influence the integral layout of the mainboard.
Description
Technical field
The utility model relates to a kind of computer system, relates in particular to a kind of computer system of utilizing existing system state indicator the power-up state of each road voltage of system to be carried out abnormal show before and after start.
Background technology
Design in computer system at present; usually can be provided with a plurality of system state indicators (that is; the port80 pilot lamp that practise to claim) carries out whether display system has abnormality in the process of startup self-detection (POST) after finishing to power at each road voltage of system; yet system state indicator is not done other purposes before startup self-detection, and the waste that causes hardware resource to use.
In addition, before system carries out startup self-detection, computer system need power on according to certain time sequence usually, in power up, the multichannel fundamental voltage is finished conversion successively in this computer system, used to offer the follow-up running of computer system, thereby need whether to reach preset requirement and detect for each the road voltage after the conversion, whether finish to determine powering on of computer system, yet the power-up state at computer system does not provide display mechanism on existing computer system, therefore take place to learn when unusual to be that the conversion of which voltage does not reach preset requirement powering on of system, this makes troubles for the debug (debug) of system, that is, when the generation that powers on of system is unusual, and can't know which voltage generation problem and got rid of, to this, settling mode effectively, for provide one to detect display mechanism by power-up state to system, use the power-up state of the system of detecting, and when unusual, shown, but this mode really can significantly increase the cost of system design, and also can be subjected to the restriction of the spare part of the detection display mechanism that increased at the circuit layout of inside computer system.
Therefore, how to propose a kind of computer system, come the power-up state of each road voltage of indication mechanism, use the disadvantages that overcomes prior art, become the problem that present industry is demanded urgently overcoming in fact with the hardware resource that utilizes the existing systems motherboard.
The utility model content
Shortcoming in view of above-mentioned prior art, a purpose of the present utility model is to provide a kind of computer system, it must utilize the hardware resource of existing systems motherboard to come the power-up state of each road voltage of indication mechanism, to save the system design cost and not influence the layout of existing system motherboard.
For reaching above-mentioned and other purpose, the utility model provides a kind of computer system, power on according to certain time sequence, in power up, the multichannel fundamental voltage is finished conversion successively to reach preset requirement in this computer system, comprising: Basic Input or Output System (BIOS), and finish in this system and to carry out startup self-detection after powering on, when it carries out startup self-detection, produce a self check progress information; South Bridge chip, it connects this Basic Input or Output System (BIOS); Control module, it has a plurality of input ends and output terminal, one of described these input ends are connected with this South Bridge chip, to receive this self check progress information, the part of described these input ends also receives the information that converts from the multichannel fundamental voltage of system respectively, and, export a plurality of control signals by described these output terminals according to information that converts that is received and self check progress information; And a plurality of system state indicators, it connects the output terminal of this control module respectively, to receive described these control signals.
In an embodiment of the present utility model, (Low Pin Count, LPC) bus is connected to this South Bridge chip to this Basic Input or Output System (BIOS) by short tube pin counting.This control module is complex logic assembly (CPLD).The output terminal of this control module is the GPIO interface.
Than prior art, the system indicator that the utility model system will have the abnormality that is used to show the startup self-detection process now is used for the unusual indication of the power-up state of each road voltage of system, that is, the power-up state that system state indicator can be used for each road voltage of system with power on finish after the indication of abnormality of startup self-detection, thereby can effectively save the system design cost and be unlikely to influence the layout of system host slab integral.
Description of drawings
Fig. 1 is the basic framework block schematic diagram of an embodiment of computer system of the present utility model.
[simple declaration of assembly label]
10 Basic Input or Output System (BIOS)s, 11 South Bridge chips
12 control modules, 13 system state indicators
Embodiment
Below by specific instantiation embodiment of the present utility model is described, those skilled in the art can understand other advantage of the present utility model and effect easily by the content that this instructions disclosed.The utility model also can be implemented or be used by other different instantiation, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present utility model not deviating from.
As shown in Figure 1, be the basic framework synoptic diagram of an embodiment of computer system of the present utility model.Computer system of the present utility model powers on according to certain time sequence, and in power up, the multichannel fundamental voltage is finished conversion successively to reach preset requirement in this computer system.As shown in Figure 1, computer system of the present utility model comprises: Basic Input or Output System (BIOS) (BIOS) 10, South Bridge chip 11, control module 12, a plurality of system state indicator (port80 pilot lamp) 13.This computer system shows the power-up state of each road voltage of system in system's power up to drive this system state indicator 13 by the cooperation between this Basic Input or Output System (BIOS) 10, South Bridge chip 11, the control module 12 running, and also can carry out the demonstration of abnormality by this system state indicator 13 in each road voltage powers on the process of carrying out startup self-detection after finishing.Below promptly the utility model is carried out following detailed description.
This Basic Input or Output System (BIOS) 10 has the relation of electric connection with this South Bridge chip 11, that is, this South Bridge chip 11 is connected with an input end (interface 9) of this control module 12, and finish in system in this Basic Input or Output System (BIOS) 10 and to carry out startup self-detection after powering on, when it carries out startup self-detection, produce a self check progress information.This Basic Input or Output System (BIOS) 10 is connected to this South Bridge chip 11 by lpc bus.
This control module 12 has a plurality of input ends (interface 1-9) and one of them (interface 9) is connected with this South Bridge chip 11, to receive this self check progress information, the part of a plurality of input ends of this control module 12 (interface 1-8) also receives the information that converts from the multichannel fundamental voltage of system respectively, this control module 12 is according to information that converts that is received and self check progress information, and (interface G1-G8) exports a plurality of control signals by described these output terminals.
Described these system state indicators 13 connect the output terminal (interface G1-G8) of a plurality of general I/O (GPIO) interface of this control module 12 respectively, but not as limit, and the interface that still can select other form for use as an alternative.
In an embodiment of the present utility model, this control module 12 is a complex logic assembly (CPLD), but not as limit, still can select other logic module with equal effect for use as an alternative.
Therefore, the power-up state of each road voltage showed when the cooperation running by 12 of this Basic Input or Output System (BIOS)s 10, South Bridge chip 11, control module powered on to drive 13 pairs of systems of this system state indicator, and also can in powering on the process of carrying out startup self-detection after finishing, each road voltage carry out the demonstration of abnormality by this system state indicator 13, that is this system state indicator 13 can be used for the indication of the abnormality of the power-up state of each road voltage of system and startup self-detection.In addition, these control module 12 receptions are from the information that converts (S1 for example shown in Figure 1, the S2 of the multichannel fundamental voltage of system ... S8), then drive with the corresponding system state indicator 13 of this information and light if receive the information of converting.Otherwise 13 corresponding voltage transitions are not finished if system state indicator 13 does not light then expression and this pilot lamp, so this system state indicator 13 can be kept the state that does not work.
After this, after each power supply electrifying of system is finished, system can carry out startup self-detection (POST) process, can be by showing unusually of being found in Basic Input or Output System (BIOS) 10 of the present utility model, South Bridge chip 11, control module 12,13 pairs of system boot self checks of the system state indicator process in this process.Promptly, system boot enters in the process of startup self-detection after finishing when powering on, when noting abnormalities, this Basic Input or Output System (BIOS) 10 promptly can be transferred to South Bridge chip 11 by lpc bus with the self check progress information of correspondence, this South Bridge chip 11 can be transferred to this control module 12 with this self check progress information that is received immediately, this control module 12 can drive corresponding system state indicator 13 according to the self check progress information that it received light it, so, can know the abnormality of system in the startup self-detection process according to the light and shade state of this system state indicator 13.
As mentioned above, according to computer system of the present utility model, the information that converts that in system's power up, can receive from the multichannel fundamental voltage of system by this control module 12, and drive connected system state indicator 13 carries out multichannel fundamental voltage power-up state with the light and shade state demonstration according to the result who is received.And power in system and to carry out in the startup self-detection process after finishing, this system state indicator 13 carries out abnormality by the cooperation running of 12 of this Basic Input or Output System (BIOS)s 10, South Bridge chip 11, control module with drive system status indicator lamp 13 and shows, so can be used for the indication of the abnormality of the power-up state of each road voltage of system and startup self-detection.
That is, computer system of the present utility model, can be in system's power up whether multichannel fundamental voltage in the expression system be powered on to finish and detect, and the result that detected is carried out light and shade by system state indicator show, and finish in each road voltage and to carry out in the startup self-detection process after powering on, carry out abnormality by this system state indicator and show.Therefore, by computer system of the present utility model, need not the equipment that on system host board, additionally installs additional and whether reach preset requirement with the power-up state of each road voltage of display system, and can make full use of the hardware resource of existing systems mainboard, thereby can save design cost and not influence the integral layout of motherboard.
The foregoing description is illustrative principle of the present utility model and effect thereof only, but not is used to limit the utility model.Any those skilled in the art all can be under spirit of the present utility model and category, and the foregoing description is modified and changed.Therefore, rights protection scope of the present utility model should be listed as claims.
Claims (4)
1. a computer system powers on according to certain time sequence, and in power up, the multichannel fundamental voltage is finished conversion successively to reach preset requirement in this computer system, it is characterized in that, comprising:
Basic Input or Output System (BIOS) is finished in this system and to be carried out startup self-detection after powering on, and when it carries out startup self-detection, produces a self check progress information;
South Bridge chip connects this Basic Input or Output System (BIOS);
Control module, have a plurality of input ends and output terminal, one of described these input ends are connected with this South Bridge chip, to receive this self check progress information, the part of described these input ends also receives the information that converts from the multichannel fundamental voltage of system respectively, and, export a plurality of control signals by described these output terminals according to information that converts that is received and self check progress information; And
A plurality of system state indicators connect the output terminal of this control module respectively, to receive described these control signals.
2. computer system according to claim 1 is characterized in that, this Basic Input or Output System (BIOS) is connected to this South Bridge chip by short tube pin count bus.
3. computer system according to claim 1 is characterized in that, this control module is the complex logic assembly.
4. computer system according to claim 1 is characterized in that, the output terminal of this control module is general input/output interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202681971U CN201562271U (en) | 2009-11-11 | 2009-11-11 | Computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202681971U CN201562271U (en) | 2009-11-11 | 2009-11-11 | Computer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201562271U true CN201562271U (en) | 2010-08-25 |
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ID=42627419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009202681971U Expired - Fee Related CN201562271U (en) | 2009-11-11 | 2009-11-11 | Computer system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201562271U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479141A (en) * | 2010-11-30 | 2012-05-30 | 英业达股份有限公司 | Processing system for monitoring power-on self-test information |
| CN103810080A (en) * | 2012-11-15 | 2014-05-21 | 昆达电脑科技(昆山)有限公司 | Computer system |
| CN104572226A (en) * | 2015-02-04 | 2015-04-29 | 浪潮(北京)电子信息产业有限公司 | Method and device for detecting mainboard starting abnormity |
| CN104794042A (en) * | 2014-01-22 | 2015-07-22 | 鸿富锦精密工业(武汉)有限公司 | Computer detecting system and method |
| CN105446430A (en) * | 2015-12-28 | 2016-03-30 | 天津浩丞恒通科技有限公司 | Computer mainboard with fault diagnosis function and LPC interface mainboard fault diagnosis card |
-
2009
- 2009-11-11 CN CN2009202681971U patent/CN201562271U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479141A (en) * | 2010-11-30 | 2012-05-30 | 英业达股份有限公司 | Processing system for monitoring power-on self-test information |
| CN103810080A (en) * | 2012-11-15 | 2014-05-21 | 昆达电脑科技(昆山)有限公司 | Computer system |
| CN104794042A (en) * | 2014-01-22 | 2015-07-22 | 鸿富锦精密工业(武汉)有限公司 | Computer detecting system and method |
| CN104572226A (en) * | 2015-02-04 | 2015-04-29 | 浪潮(北京)电子信息产业有限公司 | Method and device for detecting mainboard starting abnormity |
| CN105446430A (en) * | 2015-12-28 | 2016-03-30 | 天津浩丞恒通科技有限公司 | Computer mainboard with fault diagnosis function and LPC interface mainboard fault diagnosis card |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100825 Termination date: 20121111 |