CN201532467U - Structure of base-band circuit for double-frequency GPS satellite signal receiver - Google Patents
Structure of base-band circuit for double-frequency GPS satellite signal receiver Download PDFInfo
- Publication number
- CN201532467U CN201532467U CN2009202721574U CN200920272157U CN201532467U CN 201532467 U CN201532467 U CN 201532467U CN 2009202721574 U CN2009202721574 U CN 2009202721574U CN 200920272157 U CN200920272157 U CN 200920272157U CN 201532467 U CN201532467 U CN 201532467U
- Authority
- CN
- China
- Prior art keywords
- signal
- sign indicating
- indicating number
- module
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Position Fixing By Use Of Radio Waves (AREA)
Abstract
The utility model relates to a structure of a base-band circuit for a double-frequency GPS satellite signal receiver. The base-band circuit mainly comprises an L1 processing circuit and an L2 processing circuit; an input terminal is connected with a radio frequency circuit output terminal, and an output module and a control module are connected with a central processing module. The L1 processing circuit mainly comprises an L1C/A code tracking loop module, an L1 carrier tracking loop module, an L1W code cycle estimation module and an L1P code generation module; the L2 processing circuit comprises an L2 carrier tracking loop module, an L2P code tracking loop module, an L2W code estimation module, an L1 and L2 cross multiplier and an L2 correlator. The L1 and L2 cross multiplier and an L2 correlator are designed and realized in the DSP module arranged in a FPGA circuit module. The speed and performance of the system can be improved, the scale and cost of the system can be reduced, and the anti-interference performance of the receiver is improved. Furthermore, the structure has the advantages of simple structure of the circuit, stable, reliable working performance and wide applicable range.
Description
Technical field
The utility model relates to GPS navigation location and fields of measurement, be particularly related to double-frequency GPS (Global PositioningSystem) satellite-signal receiving and processing device technical field, specifically be meant a kind of baseband circuit structure that realizes the double-frequency GPS satellite signal receiver.
Background technology
Satellite navigation is exactly to receive the navigator fix signal that Navsat sends, and with Navsat as dynamic known location, be determined at current location and speed in real time.The L2 signal capture and the tracking that wherein relate to double-frequency GPS receiver in GNSS (Global Navigation Satellite System, the i.e. GLONASS (Global Navigation Satellite System)) field.Gps satellite signal adopts pseudo-random code (PRN) to carry out band spectrum modulation usually.Gps satellite signal mainly contains C/A sign indicating number (the thick sign indicating number of Coarse, civilian yard) and P sign indicating number (Precise, smart sign indicating number), the C/A sign indicating number is carried on the L1 carrier wave, the P sign indicating number is carried in respectively on L1 and the L2 carrier wave, and the frequency of L1 is 1575.42MHz, and the frequency of L2 is 1227.6MHz, the code check of C/A sign indicating number is 1.023M, and the code check of P sign indicating number is 10.23M.GPS is controlled by US military, and when US military was carried out so-called AS policy, the signal that is modulated on L1 and the L2 carrier wave was then formed by P sign indicating number and the W sign indicating number XOR of maintaining secrecy, and is called as the Y sign indicating number, and the code check of at present known W is characterized as 500K.New gps satellite signal also has L2C and L5 etc., but because the utility model only relates to C/A sign indicating number and P (Y) coded signal that is modulated on L1 and the L2 carrier wave, so other signals are not discussed in this article.The GPS receiver mainly is made of corresponding circuit such as radio frequency, base band and software, wherein base band mainly realizes the acquisition and tracking of pseudo-code and carrier wave thereof, baseband circuit can adopt the mode of special chip to realize, also can realize on FPGA Programmable Logic Device such as (field programmable gate arrays).By contrast, the latter is more flexible than the former, but often is difficult between the latter's travelling speed, power consumption and the cost average out.At present, the baseband circuit of double-frequency GPS receiver is still based on special chip on the market, but the mode that FPGA realizes is also just becoming the possibility of formal product.
Receiver can be divided into single frequency receiving, dual-frequency receiver, multifrequency receiver etc. by the signal frequency quantity of its processing.Also being divided into single-point location and difference location by locator meams, is the higher locator meams of precision and utilize the carrier phase location, especially double frequency or multifrequency carrier phase difference location.In the dual-frequency carrier positioning system, need carry out accurate tracking and measurement to the carrier phase of L1 and L2.All Satellite GPS radiofrequency signals are by having the right-handed polarized antenna reception that the semisphere of approaching gain covers in visual field, these radiofrequency signals are amplified after power splitter is divided into L1 and L2 two paths of signals through low-noise preamplifier, after this two paths of signals process filtering, frequency conversion, the demodulation, change into digital signal by the A/D transducer and send into baseband processor.Baseband processor at first to L1 and the L2 signal of input carry out each passage all necessary with identical front-end processing.L1 after the processing and L2 signal are sent into a plurality of treatment channel simultaneously and are followed the tracks of when realizing multi-satellite.Baseband circuit mainly comprises L1/L2 carrier tracking loop, C/A code tracking loop, C/A sign indicating number interlock circuit, L1-P/L2-P code tracking loop, L1-W/L2-W sign indicating number estimating circuit, L1 and L2 multiply each other circuit, L2 interlock circuit, measurement data latch cicuit etc.What adopt for the tracking of C/A sign indicating number is conventional spread spectrum despreading disposal route, baseband signal is carried out despreading by C/A sign indicating number ring after eliminating carrier wave through the carrier wave ring, leading (the Early of de-spreading circuit output, be the E of back), instant (Prompt, be the P of back) and (Late that lags behind, be the L of back) three kinds of time delayed signal outputs, lead and lag output is used for realizing the tracking of C/A sign indicating number, and real-time signal P output is used for realizing the locking to the carrier wave ring also providing the detection of signal to noise ratio (S/N ratio) and the identification of navigation data simultaneously.For the P sign indicating number, because L1-P has been become the Y sign indicating number with L2-P by the W code encryption of maintaining secrecy, and the W sign indicating number of maintaining secrecy is unknown to civilian users, and this has just caused traditional tracking scheme directly not follow the tracks of the L2 signal.But some features that can utilize the L2 signal realize the tracking to the L2 signal, at present, the L2 signal trace method that has proposed mainly contains the L2 quadratic method, L1 takes advantage of L2 cross-correlation method, the auxiliary quadratic method of P sign indicating number, Z to follow the tracks of L2 phase retrieval method, soft-decision Z tracking, maximum likelihood half a nothing sign indicating number L2 demodulation method.
Civilian double-frequency GPS receiver need realize catching and following the tracks of according to limited W sign indicating number feature to the P sign indicating number of encrypting (being the Y sign indicating number), in this process, will cause the loss of signal, so how to guarantee the quality of L2 signal Processing is become one of difficult point of receiver design.Because first three methods is not have the processing carried out under the situation of despreading at the P sign indicating number, so very big to the loss of signal, tracking effect is very poor, is difficult to realize the tracking to satellite under low signal intensity, is not the main method of using at present.The 4th kind of Z tracking technique drops to W sign indicating number bandwidth 500KHz with signal bandwidth after earlier L1-P and L2-P being carried out despreading and remove the P sign indicating number, reduced the influence of noise to signal.Utilize the L1-P characteristic identical again, multiply each other by L1 and L2 and eliminate the influence of W sign indicating number, greatly improved the performance of system, reduced the loss that the unknown of W sign indicating number brings with the L2-P incidental information.Back two methods are the improvement the 4th kind of method, reach the purpose that improves effect by more complicated processing.But, need be cost all in these methods with the circuit structure and the high performance processor of complexity, not only cost height, and performance is difficult to accomplish reliable and stable, has brought certain obstacle so just for the extensive popularization and application of GPS navigation technology.
The utility model content
The purpose of this utility model is to have overcome above-mentioned shortcoming of the prior art, the baseband circuit structure that provide a kind of and can realize the high-precision fixed bit function of GPS, circuit structure is simple, processing procedure is quick, cost is lower, stable and reliable working performance, the scope of application realize the double-frequency GPS satellite signal receiver comparatively widely.
In order to realize above-mentioned purpose, the baseband circuit structure of realization double-frequency GPS satellite signal receiver of the present utility model is as follows:
This realizes the baseband circuit structure of double-frequency GPS satellite signal receiver, comprise signal pre-processing circuit and several satellite treatment channel, the quantity of described satellite treatment channel is consistent with the number of satellite of being followed the tracks of, usually can be 12, each satellite treatment channel all comprises L1 signal processing circuit and L2 signal processing circuit, described signal pre-processing circuit is realized the pre-service of input signal and automatic gain control, and described signal pre-processing circuit is connected with the central processing module of this receiver with the L2 signal processing circuit by described L1 signal processing circuit respectively, its principal feature is, comprise L1 signal C/A sign indicating number processing baseband circuit module in the described L1 signal processing circuit, L1 signal P sign indicating number processing circuit module comprises L2 signal carrier track loop module in the described L2 signal processing circuit, L2 signal code track loop module, L2 signal W sign indicating number estimating circuit module, L1 signal and L2 signal cross multiplier, L2 signal correction device;
Described signal pre-processing circuit is handled the baseband circuit module by described L1 signal C/A sign indicating number and is connected with described central processing module, and described L1 signal C/A sign indicating number processing baseband circuit module is connected with L2 signal cross multiplier with described L1 signal by described L1 signal P sign indicating number processing circuit module;
Described signal pre-processing circuit is connected with described central processing module by described L2 signal carrier track loop module, and described L2 signal carrier track loop module is connected with described central processing module with L2 signal cross multiplier, L2 signal correction device by described L2 signal code track loop module, L2 signal W sign indicating number estimating circuit module, L1 signal successively;
Described L1 signal and L2 signal cross multiplier, L2 signal correction device are arranged in the built-in DSP module of FPGA circuit module.
FPGA circuit module in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver is the fpga chip of Xilinx company, and described DSP module is the DSP48A module in this fpga chip.
Have 18 totalizers, 18 multipliers and 48 totalizers in the DSP module in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver.
L1 signal in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver and L2 signal cross multiplier comprise first latch in the DSP module, second latch, the 3rd latch, quad latch, the 5th latch, 18 totalizers, 18 multipliers, described L2 signal W sign indicating number estimating circuit module is successively by described first latch, 18 totalizers, quad latch, 18 multipliers, the 5th latch is connected with described L2 signal correction device, described L1 signal P sign indicating number processing circuit module is connected with the input end of described 18 totalizers by described second latch, and described L2 signal W sign indicating number estimating circuit module is connected with the input end of described 18 multipliers by described the 3rd latch.
Also comprise first MUX in L1 signal in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver and the L2 signal cross multiplier, described first MUX is serially connected with between described 18 totalizers and the quad latch, and described second latch is connected with the input end of described first MUX, and the input of described first MUX selects control end to be connected with first pattern control pin of described DSP module.
Also be serially connected with the 6th latch between the 3rd latch in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver and the input end of described 18 multipliers.
L2 signal correction device in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver comprises 48 totalizers and the 7th latch in the DSP module, the output terminal of described L1 signal and L2 signal cross multiplier is connected with described central processing module by described 48 totalizers, the 7th latch successively, and the output terminal of described the 7th latch is connected with the input end of described 48 totalizers.
Also comprise the 8th latch in the L2 signal correction device in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver, second MUX, the 3rd MUX, described second MUX is connected in series between the output terminal and described 48 totalizers of described L1 signal and L2 signal cross multiplier, and the output terminal of described the 7th latch is connected with the input end of described second MUX, the input of described second MUX selects control end to be connected with second pattern control pin of described DSP module, described the 3rd MUX is connected in series between the input end of the output terminal of described the 7th latch and described 48 totalizers, and described L2 signal W sign indicating number estimating circuit module is connected with the input end of described the 3rd MUX by described the 8th latch, and the input of described the 3rd MUX selects control end to be connected with the three-mode control pin of described DSP module.
L1 signal C/A sign indicating number in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver is handled the baseband circuit module and is comprised L1 signal carrier track loop module, L1 signal code track loop module and L1 signal correction device, and described signal pre-processing circuit is connected with described central processing module by described L1 signal carrier track loop module, L1 signal code track loop module, L1 signal correction device successively.
L1 signal carrier track loop module in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver comprises L1 signal carrier digital controlled oscillator and L1 signal complex mixers, described signal pre-processing circuit is connected with described L1 signal code track loop module by described L1 signal complex mixers, and described L1 signal complex mixers is connected with described central processing module by described L1 signal carrier digital controlled oscillator.
L1 signal code track loop module in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver comprises L1 signal code digital controlled oscillator, ten frequency dividers, C/A sign indicating number generator and first multiplier, described L1 signal code digital controlled oscillator is connected with described L1 signal correction device by described ten frequency dividers, C/A sign indicating number generator and first multiplier, described L1 signal complex mixers is connected with the input end of described first multiplier, and described C/A sign indicating number generator is connected with central processing module with described L1 signal correction device respectively.
L1 signal P sign indicating number processing circuit module in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver comprises P1 sign indicating number generator, second multiplier, W1 sign indicating number period generator and W bit integrator, described L1 signal code digital controlled oscillator is by described P1 sign indicating number generator, W1 sign indicating number period generator, W bit integrator is connected with L2 signal cross multiplier with described L1 signal, described P1 sign indicating number generator is connected with described W bit integrator by described second multiplier, and described L1 signal complex mixers is connected with the input end of described second multiplier, and described P1 sign indicating number generator is connected with described central processing module.
L2 signal carrier track loop module in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver comprises L2 signal carrier digital controlled oscillator and L2 signal complex mixers, described signal pre-processing circuit is connected with described L2 signal code track loop module by described L2 signal complex mixers, and described L2 signal complex mixers is connected with described central processing module by described L2 signal carrier digital controlled oscillator.
L2 signal code track loop module in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver comprises L2 signal code digital controlled oscillator, P2 sign indicating number generator and the P2 decoding circuit that disappears, described L2 signal code digital controlled oscillator is connected with described L2 signal W sign indicating number estimating circuit module with the P2 decoding circuit that disappears by described P2 sign indicating number generator successively, described P2 sign indicating number generator is connected with central processing module with described L2 signal W sign indicating number estimating circuit module respectively, and described L2 signal complex mixers is connected with the described P2 of disappearing decoding circuit.
L2 signal W sign indicating number estimating circuit module in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver comprises W2 sign indicating number period generator and W2 sign indicating number integrator, described P2 sign indicating number generator is connected with L2 signal cross multiplier with described L1 signal by described W2 sign indicating number period generator, W2 sign indicating number integrator successively, and the described P2 of disappearing decoding circuit is connected with described W2 sign indicating number integrator.
Adopted the baseband circuit structure of the realization double-frequency GPS satellite signal receiver of this utility model, owing to wherein realize based on the double-frequency GPS receiver baseband circuit of FPGA, consideration on combination property, implementation complexity, power consumption and the cost, signal is being carried out on the basis of many bit sample, after removing the P sign indicating number, despreading utilizes the cycle information of W sign indicating number, on the W sign indicating number cycle, carry out integration, on L1 signal and L2 signal, realize estimation respectively the W sign indicating number; Can carry out the characteristics that many bits high-speed digital signal is handled based on the built-in DSP module of FPGA then, by L1 be multiply by the influence of eliminating unknown W sign indicating number and modulating data mutually with the estimation W sign indicating number of L2, thereby realize tracking to the L2 signal, the speed and the performance of system have not only been improved greatly, greatly reduce the scale that total system realizes simultaneously, effectively reduce cost, further improved simultaneously the interference free performance of receiver, thereby on the basis of the performance that improves system significantly, reduced consumption to the FPGA resource, not only circuit structure is simple, and processing procedure is quick, and cost is lower, stable and reliable working performance, the scope of application are comparatively extensive.
Description of drawings
Fig. 1 is the integrated circuit composition frame chart of double-frequency GPS receiver of the present utility model.
Fig. 2 is the baseband circuit structural entity structural representation of realization double-frequency GPS satellite signal receiver of the present utility model.
Fig. 3 is for utilizing the electrical block diagram of DSP module section in the baseband circuit structure of realization double-frequency GPS satellite signal receiver of the present utility model.
Fig. 4 is based on the overall flow figure of baseband circuit structure realization of the present utility model to the method for GPS L2 signal trace.
Embodiment
In order more to be expressly understood technology contents of the present utility model, describe in detail especially exemplified by following examples.
See also Fig. 1 to shown in Figure 3, this realizes the baseband circuit structure of double-frequency GPS satellite signal receiver, comprise signal pre-processing circuit and several satellite treatment channel, the quantity of described satellite treatment channel is consistent with the number of satellite of being followed the tracks of, and can be 12 usually.
Simultaneously, it is pointed out that baseband portion signal in the utility model through being sent into 12 satellite treatment channel simultaneously after the pre-service, 12 passages are identical herein, can be as required with the FPGA capacity extension or dwindle number of channels.Because 12 channel architectures are identical, only are in order to follow the tracks of different satellites simultaneously, so the structure of a passage only is discussed in the utility model.What provide among Fig. 1 is the structural drawing of a satellite treatment channel, other passage of overlapping 12 passages of box indicating, and comprise the two paths of signals treatment circuit in a passage, i.e. L1 signal processing circuit and L2 signal processing circuit.
Wherein, each satellite treatment channel all comprises L1 signal processing circuit and L2 signal processing circuit, described signal pre-processing circuit is realized the pre-service of input signal and automatic gain control, and described signal pre-processing circuit is connected with the central processing module of this receiver with the L2 signal processing circuit by described L1 signal processing circuit respectively, wherein, comprise L1 signal C/A sign indicating number processing baseband circuit module in the described L1 signal processing circuit, L1 signal P sign indicating number processing circuit module comprises L2 signal carrier track loop module in the described L2 signal processing circuit, L2 signal code track loop module, L2 signal W sign indicating number estimating circuit module, L1 signal and L2 signal cross multiplier 218, L2 signal correction device 220;
Described signal pre-processing circuit 239 is handled the baseband circuit module by described L1 signal C/A sign indicating number and is connected with described central processing module 219, and described L1 signal C/A sign indicating number processing baseband circuit module is connected with L2 signal cross multiplier 218 with described L1 signal by described L1 signal P sign indicating number processing circuit module;
Described signal pre-processing circuit 239 is connected with described central processing module 219 by described L2 signal carrier track loop module, and described L2 signal carrier track loop module is connected with described central processing module 219 with L2 signal cross multiplier 218, L2 signal correction device 220 by described L2 signal code track loop module, L2 signal W sign indicating number estimating circuit module, L1 signal successively;
Described L1 signal and L2 signal cross multiplier 218, L2 signal correction device 220 are arranged in the built-in DSP module of FPGA circuit module.
Wherein, described L1 signal C/A sign indicating number is handled the baseband circuit module and is comprised L1 signal carrier track loop module, L1 signal code track loop module and L1 signal correction device 217, and described signal pre-processing circuit 239 is connected with described central processing module 219 by described L1 signal carrier track loop module, L1 signal code track loop module, L1 signal correction device 217 successively.
Described L1 signal carrier track loop module comprises L1 signal carrier digital controlled oscillator 200 and L1 signal complex mixers 201, described signal pre-processing circuit 239 is connected with described L1 signal code track loop module by described L1 signal complex mixers 201, and described L1 signal complex mixers 201 is connected with described central processing module 219 by described L1 signal carrier digital controlled oscillator 200.
Described L1 signal code track loop module comprises L1 signal code digital controlled oscillator 202, ten frequency dividers 207, C/A sign indicating number generator 209 and first multiplier 210, described L1 signal code digital controlled oscillator 202 is connected with described L1 signal correction device 217 by described ten frequency dividers 207, C/A sign indicating number generator 209 and first multiplier 210, described L1 signal complex mixers 201 is connected with the input end of described first multiplier 210, and described C/A sign indicating number generator 209 is connected with central processing module 219 with described L1 signal correction device 217 respectively.
Described L1 signal P sign indicating number processing circuit module comprises P1 sign indicating number generator 203, second multiplier 208, W1 sign indicating number period generator 211 and W bit integrator 214, described L1 signal code digital controlled oscillator 202 is by described P1 sign indicating number generator 203, W1 sign indicating number period generator 211, W bit integrator 214 is connected with L2 signal cross multiplier 218 with described L1 signal, described P1 sign indicating number generator 203 is connected with described W bit integrator 214 by described second multiplier 208, and described L1 signal complex mixers 201 is connected with the input end of described second multiplier 208, and described P1 sign indicating number generator 203 is connected with described central processing module 219.
This is realized in the baseband circuit structure of double-frequency GPS satellite signal receiver, described L2 signal carrier track loop module comprises L2 signal carrier digital controlled oscillator 205 and L2 signal complex mixers 204, described signal pre-processing circuit 239 is connected with described L2 signal code track loop module by described L2 signal complex mixers 204, and described L2 signal complex mixers 204 is connected with described central processing module 219 by described L2 signal carrier digital controlled oscillator 205.
Described L2 signal code track loop module comprises L2 signal code digital controlled oscillator 206, P2 sign indicating number generator 213 and the P2 decoding circuit 212 that disappears, described L2 signal code digital controlled oscillator 206 is connected with described L2 signal W sign indicating number estimating circuit module with the P2 decoding circuit 212 that disappears by described P2 sign indicating number generator 213 successively, described P2 sign indicating number generator 213 is connected with central processing module 219 with described L2 signal W sign indicating number estimating circuit module respectively, and described L2 signal complex mixers 204 is connected with the described P2 of disappearing decoding circuit 212.
Described L2 signal W sign indicating number estimating circuit module comprises W2 sign indicating number period generator 216 and W2 sign indicating number integrator 215, described P2 sign indicating number generator 213 is connected with L2 signal cross multiplier 218 with described L1 signal by described W2 sign indicating number period generator 216, W2 sign indicating number integrator 215 successively, and the described P2 of disappearing decoding circuit 212 is connected with described W2 sign indicating number integrator 215.
Wherein, described FPGA circuit module is the fpga chip of Xilinx company, and described DSP module is the DSP48A module in this fpga chip; Have 18 totalizers 227,18 multipliers 232 and 48 totalizers 236 in the described DSP module.
Simultaneously, described L1 signal and L2 signal cross multiplier 218 comprise first latch 223 in the DSP module, second latch 224, the 3rd latch 225, quad latch 229, the 5th latch 233,18 totalizers 227,18 multipliers 232, described L2 signal W sign indicating number estimating circuit module is successively by described first latch 223,18 totalizers 227, quad latch 229,18 multipliers 232, the 5th latch 233 is connected with described L2 signal correction device 220, described L1 signal P sign indicating number processing circuit module is connected with the input end of described 18 totalizers 227 by described second latch 224, and described L2 signal W sign indicating number estimating circuit module is connected with the input end of described 18 multipliers 232 by described the 3rd latch 225.
Also comprise first MUX 228 in described L1 signal and the L2 signal cross multiplier 218, described first MUX 228 is serially connected with between described 18 totalizers 227 and the quad latch 229, and described second latch 224 is connected with the input end of described first MUX 228, the input of described first MUX 228 selects control end to be connected with first pattern control pin 61 of described DSP module.
Also be serially connected with the 6th latch 231 between the input end of described the 3rd latch 225 and described 18 multipliers 232.
Moreover, described L2 signal correction device 220 comprises 48 totalizers 236 and the 7th latch 237 in the DSP module, the output terminal of described L1 signal and L2 signal cross multiplier 218 is connected with described central processing module 219 by described 48 totalizers 236, the 7th latch 237 successively, and the output terminal of described the 7th latch 237 is connected with the input end of described 48 totalizers 236.
Also comprise the 8th latch 226 in the described L2 signal correction device 220, second MUX 234, the 3rd MUX 235, described second MUX 234 is connected in series between the output terminal and described 48 totalizers 236 of described L1 signal and L2 signal cross multiplier 218, and the output terminal of described the 7th latch 237 is connected with the input end of described second MUX 234, the input of described second MUX 234 selects control end to be connected with second pattern control pin 69 of described DSP module, described the 3rd MUX 235 is connected in series between the input end of the output terminal of described the 7th latch 237 and described 48 totalizers 236, and described L2 signal W sign indicating number estimating circuit module is connected with the input end of described the 3rd MUX 235 by described the 8th latch 226, and the input of described the 3rd MUX 235 selects control end to be connected with the three-mode control pin 70 of described DSP module.
Simultaneously, L1 signal (L1) in the baseband circuit structure of this realization double-frequency GPS satellite signal receiver and L2 signal (L2) are the A/D sampled output signal that bit wide is at least 3 bits.
In the middle of reality is used, see also shown in Figure 1ly, it is the circuit composition frame chart of double-frequency GPS receiver.Constitute front radio-frequency circuit part of the present utility model by antenna 231, power splitter 232, L1 radio circuit 233 and L2 radio circuit 234.Clock 244 provides standard time clock to radio circuit and baseband circuit 240 simultaneously.Orthogonal signal after L1 radio circuit 233 and L2 radio circuit 234 down coversions and demodulation convert orthogonal digital baseband signal 63-66 to by A/D converter 235-238 and send into baseband processing circuitry 240.Under the situation of sampling rate greater than 2 times of bandwidth, for the wideband Gaussian noise signals sampling, the loss of 1 bit, 2 bits and 3 bit A C is respectively 1.96dB, 0.55dB and 0.16dB.The quantization scheme that exceeds 3 bits is very little to the improvement of loss of signal, in the utility model, adopt 3 bits or be higher than the quantization scheme of 3 bits, the bit wide that also is A/D sampled output signal 63～66 is 3 bits or is higher than 3 bits that for simplicity, follow-up discussion is an example with 3 bits all.The digital baseband signal 63-66 that enters base band is entering signal pre-process circuit 239 at first.Signal pre-processing circuit is mainly finished the signal sampling and the shared signal Processing work of passage of automatic gain control circuit.Signal after handling is divided into L1 (67,68) and L2 (69,70) two-way is given L1 treatment circuit 241 and L2 treatment circuit 242 respectively.L1 treatment circuit 241 and L2 treatment circuit 242 have constituted single channel satellite treatment circuit 243, and design has 12 satellite treatment channel and a noise power estimating channel according to needs the utility model of satellites in view quantity and distribution thereof.But the utility model is not limited only to have the design of 12 satellite treatment channel, can adjust the quantity of satellite treatment channel and the tracking of each passage with the variation of following satellite emission signal as required, to satisfy the needs of system to future development.The clock signal clk 1 that whole baseband circuit 240 and radio circuit common clock 244 produce.Signal that each passage is handled and control signal corresponding 72～74 and CPU 219 finish the signal processing function of whole GPS dual-frequency receiver alternately.
Seeing also shown in Figure 2ly, it is a baseband circuit one-piece construction synoptic diagram of the present utility model.Form L1C/A coded signal treatment circuit by L1 carrier wave NCO (NumberControl Oscillation digital controlled oscillator) 200, L1 complex mixers 201, L1 sign indicating number NCO 202,10 frequency dividers 207, C/A sign indicating number generator 209, multiplier 210 and L1 correlator 217.Constitute L1-P sign indicating number front-end processing circuit by P1 sign indicating number generator 203, multiplier 208, W1 sign indicating number period generator 211 and W bit integrator 214, produce L1_W sign indicating number estimated signal 43.Constitute L2-P sign indicating number treatment circuit by L2 complex mixers 204, L2 carrier wave NCO 205, L2 sign indicating number NCO 206, the P2 decoding circuit 212 that disappears, P2 sign indicating number generator 213, W2 sign indicating number period generator 216 and W2 sign indicating number integrator 215.Produce L2_W sign indicating number estimated signal, signal is divided into leading (Early) 31 of quadrature output, instant (Prompt) 32, hysteresis (Late) 33 signals (being the EPL signal).Multiplication cross device 218 is finished the function that offsets of L1W and L2W sign indicating number, realization is to the elimination of unknown W sign indicating number, carry out integration via the control of C/A sign indicating number periodic signal (Epoch) 50 by 220 pairs of signals of L2 correlator then, final signal send by microprocessor (CPU) 219 and handles.
Realize in the whole double-frequency GPS receiver major function that L2 follows the tracks of is positioned at L1 and L2 multiplier circuit, by multiplying each other of filtered L1 and L2 two paths of signals being realized to encrypting the elimination of P sign indicating number, thereby realization is to the tracking of L2.Demand to system resource when realizing the addition design in the logical circuit of FPGA will increase sharply along with the increase of bit wide, and the increase of addition bit wide also will cause the maximum clock speed of FPGA indoor design seriously to descend.If realize multiplier with the corresponding bit wide of addition in FPGA, this consumption and the reduction of maximum clock speed to resource will be than realizing that totalizer will be even more serious.In the utility model, the 3 bit sample schemes that are different from other 1～2 bit scheme have been adopted at front end, like this at the rear end part of signal Processing, crucial elimination W sign indicating number influence L1 in the circuit and the L2 bit wide partly that multiplies each other and has reached 6～8, and integrating circuit then is 16 and adds up.At this moment will greatly consume the maximum clock speed of fpga logic resource and reduction FPGA as employing common addition and mlultiplying circuit design, thereby influence the performance of total system.Yet this part circuit just can be realized by the DSP module that is had in the FPGA circuit in the utility model.What the DSP module realized is the simple numerical signal processing function, is example with Xilinx company in the market at the DSP48A of fpga chip indoor design, comprising the data latches of 1 18 totalizer, 18 multiplier, 48 totalizer and relevant position and carry logic etc.Inner connecting way by control DSP can be realized integrating function.Because the DSP module belongs to the circuit that is solidificated among the FPGA, have the top speed of FPGA design, also can not take the logical resource of FPGA, in the utility model, adopt these modules will obtain best performance and minimum resource consumption.
See also shown in Figure 3ly again, wherein provided the use-pattern of DSP in the utility model.In the utility model, will realize that multiply each other disappear W decoding circuit and final L2 of complicated L1 and L2 exports integrator and be placed among the DSP and realize.The utility model adopts the quantification of 3 bits in order to reduce loss that quantizes and the performance that improves system to greatest extent in the front-end circuit.See also shown in Figure 2, with the L1 passage is example, the design of L1 carrier wave NCO 200, L1 sign indicating number NCO 202, P1 sign indicating number generator 203, C/A sign indicating number generator 209, frequency divider 207 and W1 sign indicating number period generator 211 and the bit number of input signal 1LI3 and L1Q4 are irrelevant, are according to the fixing design of system's needs.Multiplier 208 and multiplier 210 is owing to multiply each other with the signal 16 and 27 of 1 bit output respectively, and the realization circuit of reality is a Nverter circuit only, and system scale is had no impact.Actual with import relevant have only L1 complex mixers 201, L1 correlator 217 and W bit integrator 214.The output signal 17 of L1 carrier wave NCO 200 and Q8 are 2 bit quantization data, and the output 11 of L1 complex mixers and the 12 signal outputs for 2 bits and the output of 3 bit quantizations are 4 bit bit wides, and only for the input of 1 bit quantization, output just is 3 bit bit wides.If utilize the memory RAM resource among the FPGA, complex mixers can realize by simple logic gate and latch.And total system is very little to the use amount of memory resource, and the memory resource that common FPGA provides is far longer than the needs in the design, thereby can also further reduce the demand to the fpga logic cell capability.Adopt 3 bit quantizations before L1 correlator 217, not increase the scale what are realized as can be seen than 2 bits and 1 bit quantization.And the L1 correlator for guarantee enough surpluses and with the design of cpu i/f, all be 16 bit accumulators usually, 16 bit accumulators are also enough for 3 bit quantizations output bit wide.Thereby adopt the design of 3 bit quantizations output that the L1 passage is not increased too much scale as can be seen.To the L1 passage similar situation is arranged for L2 passage front-end circuit, do not do too much explanation at this.
The utility model uses maximum L1 * L2 circuit 218 and L2 correlator 220 to be put among the intrinsic module DSP of FPGA resource and realizes.The FPGA of the DSP module that employing has does not take the programmable logic cells of FPGA self, but all exist as functional module no matter whether use.As realize multidigit multiplier and totalizer in the fpga logic unit, its speed will descend serious along with the increase of bit wide, and the multiplier that is solidificated among the DSP is not subjected to the influence of bit wide, and have the fastest speed.The input bit wide of DSP is 18, head and shoulders above the input bit wides that produce of 3 bit quantizations, do not have the not enough situation of subsequent conditioning circuit bit wide that front end input signal bit wide causes that improves.Therefore, the realization circuit that the design will take maximum resources is put among the DSP, not only can improve the speed and the performance of system.Also can reduce the scale that total system realizes greatly, the reduction of scale will directly cause the reduction of cost.Adopt this design can save FPGA design scale about 1/3rd, the cost that adopts the FPGA of corresponding low scale to reduce is very considerable.In addition, adopt the input of 3 bit quantizations, also can increase the interference free performance of system by the control of agc circuit.It is helpless that the receiver of 1 bit quantization disturbs the CW continuous wave, and needing 2 bits at least is to quantize input anti-CW continuous wave interference capability just can be provided.Adopt the quantification of 3 bits can further improve the interference free performance of receiver.Other 3 bit quantizations can also reduce and quantize loss, improve signal quality, improve signal to noise ratio (S/N ratio).3 bit quantizations are compared the loss that 2 bits can reduce 0.29dB, and relative 1 bit can reduce the loss of 1.8dB.About antijamming capability and reduce to quantize loss can be referring to below with reference to document:
" GPS principle and application " (second edition), bandit's bright red is translated, the Electronic Industry Press, P187～190 (English master: Understanding GPS:Principles and Applications, Second Edition, Elliott D.Kaplan, Christopher J.Hegarty)
Wherein provided and quantized loss and jamproof simple argumentation.
By above-mentioned analysis as can be seen, adopt 3 bit quantization schemes and adopt the mode of the intrinsic DSP resume module of FPGA complex correlators circuit on the basis of the performance that can improve system significantly, to reduce consumption in the utility model to the FPGA resource.
The gps signal that receiver is received is divided into L1 and L2 two-way by the power splitter of front radio-frequency circuit, enters baseband circuit then after the A/D conversion.The L1 signal enters L1 complex mixers 201 through L1I3 and L1Q4, and the local carrier signal that produces with L1 carrier wave NCO 200 multiplies each other, and eliminates the residual carrier wave of input signal.L1 carrier wave NCO 200 and L1 complex mixers 201 are formed carrier loop, and clock signal is from SCLK 1, and the carrier wave stepping is subjected to microprocessor (CPU) 219 controls.The data latching speed of ms signal 2 control L1 carrier wave NCO 200 produces L1 carrier phase signal 9 and gives microprocessor 219.Microprocessor is according to the I of L1 correlator output
CA40, Q
CA41 and I
CAE-LThe locking of 42 signal controlling carrier loops.L1 sign indicating number NCO 202, frequency divider 207, C/A sign indicating number generator 209 and multiplier 210 constitute the code tracking loop.L1 sign indicating number NCO 202 steppings are subjected to microprocessor 219 control to produce the P bit rate signal 10 of 10.23MHz, produce the required 1.023MHz signal of C/A sign indicating number generator 209, the generation of control C/A sign indicating number through frequency divider 207.The C/A sign indicating number 27 that produces and the orthogonal signal I of L1 complex mixers 201 generations
BB11 and Q
BB12 multiply each other eliminates C/A sign indicating number on the in-phase component, finishes the despreading work of C/A sign indicating number.C/A sign indicating number output 26 produces ms 2 and latchs code phase information constantly, delivers to microprocessor 219 computing of decoding.Equally, microprocessor 219 is according to the locking of L1 correlator output signal control code NCO loop.Above circuit has constituted the processing baseband circuit of C/A sign indicating number.
P1 sign indicating number generator 203, multiplier 208, W1 sign indicating number period generator 211 and W bit integrator 214 have constituted L1-P sign indicating number treatment circuit.The 10.23MHz clock signal 10 that L1 sign indicating number NCO 202 produces offers P1 sign indicating number generator 203 and produces P coded signal 16, and P1 sign indicating number generator 203 also produces the synchronous control signal 17 of W1 sign indicating number period generator 211 simultaneously, controls resetting of W1 sign indicating number period generator.W1 sign indicating number period generator 211 produces the W sign indicating number periodic signal that is used for encrypting the P sign indicating number, and this signal only can reflect the period of change of W sign indicating number, is not really to be used for the W sign indicating number encrypted.Multiplier will multiply each other with L1-P coded signal 16 from the output QBB 13 of L1 complex mixers 201, eliminates the P coded signal in the L1 quadrature component, finishes the despreading work to the L1-P sign indicating number.Output signal WL114 enters W bit integrator and carry out integration under the control of W1 sign indicating number period generator 211, finishes the filtering to the L1_W sign indicating number, realizes the estimation output L1_W 43 to the L1_W sign indicating number.
The latter half among Fig. 2 realizes the L2-P sign indicating number is dealt with the work.L2 carrier wave NCO 205 and L2 complex mixers 204 and microprocessor 219 constitute the carrier tracking loop of L2 signals.The L2I 5 of quadrature output and L2Q 6 and local carrier signal I 21 and Q 22 that L2 carrier wave NCO 205 produces send into L2 complex mixers 204, generate zero carrier digital orthogonal baseband signal IBB 19 and QBB20.L2 sign indicating number NCO 206, P2 sign indicating number generator 213 and P2 sign indicating number 212 circuit that disappear constitute L2 code tracking loop.L2 sign indicating number NCO 206 produces the required 10.23MHz sign indicating number clock of P2 sign indicating number generator 213, the orthogonal signal that L2-P coded signal 25 that the sign indicating number generator produces and L2 complex mixers 204 produce multiply each other in P2 sign indicating number 212 circuit that disappear and finish the despreading of L2-P sign indicating number, produce leading WL2E31, instant WL2P 32 and hysteresis WL2L 33 signals simultaneously.W2 sign indicating number period generator 216 and W2 sign indicating number integrator 215 constitute L2W sign indicating number estimating circuit.Produce instant L2_W P38 of leading L2_W E37. and hysteresis L2_W L39 estimated signal.L1 * L2 circuit 218 is finished the multiplication operations of L1_W sign indicating number estimated signal and L2_W sign indicating number estimated signal, realizes the elimination to the W coded signal and the loaded data signal of the unknown.The leading L2 E44 that produces, instant L2 P45 and hysteresis L2 L46 signal enter L2 correlator 220, and the leading E47 of the output of correlator, instant P48 and hysteresis L49 offer microprocessor 219 and finish L2 carrier wave ring and yard locking that encircles.
The tracking of L2 signal is focused on elimination to unknown W sign indicating number.The W sign indicating number that whole concept is based on the L1 of satellites transmits and P sign indicating number subsidiary above the L2 signal is identical, thus use to the W sign indicating number on the L1 estimate with L2 on the W sign indicating number estimate to multiply each other and eliminate the scheme that L2 goes up the W sign indicating number.Can be written as in the received signal P of base band upstream end L1 and L2 sign indicating number part:
In the formula, P (n) is the P sign indicating number; W (n) is the W sign indicating number; D (n) is a modulating data; Ω is residual carrier wave;
Be phase angle; N is a sampled point.After the process complex mixers was eliminated residual carrier wave and de-spreading circuit elimination P sign indicating number, received signal can be written as:
LPx(n)＝W(n)·D(n) i＝1，2
System carries out integration by W bit (bit) integrator on the W sign indicating number cycle, realize the optimal estimation to the W sign indicating number.Then, finish the elimination of L2 being gone up the modulation D sign indicating number of encrypting the W sign indicating number by L1 * L2 circuit 218 multiplication crosses.Finally realize EPL is exported in the observation of L2 via L2 correlator 220.W2 sign indicating number integrator 215, L1 * L2 circuit 218 and L2 correlator 220 can be connected realization by the inside of configuration DSP, and a DSP module can realize circuit-switched data calculating.Tracking to whole L2 carrier wave ring and sign indicating number ring in the design needs 6 kinds of test datas (being leading, the instant and hysteresis test signal of quadrature output), so each road Satellite Tracking passage needs six DSP to realize.
See also shown in Figure 3ly again, it has only provided road signal in the output of 6 circuit-switched data in the design for adopting the L2 interlock circuit of DSP modular design among figure, for the ease of this paper explanation actual DSP circuit structure has been done partly and simplified.Fig. 3 circuit is by Mode[0～2] the L2P coded signal that can realize having the W sign indicating number that is provided with of pin handles and do not handle two kinds of functions with the L2P coded signal of W sign indicating number.Whether the P coded signal carried out the W code encryption, can obtain by the data on the decoded navigation text.The DSP module comprises that mainly 1 18 bit adder 227,1 18 bit multiplier, 236,3 MUX of 232,1 48 bit adder (228,234,235) and some latchs constitute as can be seen.Input signal WL2 52 sends into 6 DSP modules respectively for any one tunnel, 6 road signals of P2 decoding circuit 212 outputs 6 road signals that disappear and realizes disappearing W sign indicating number and L2 related operation.WL2 signal 52 53 fens two-way of signal after by W bit integrator 222 enter DSP modules A and C input end, and do corresponding expansion by the input end bit wide.The signal 43 of WL1 signal 14 after by W bit integrator 214 is 6 road DSP module shared signals, sends into the B pin of 6 road these passages DSP module simultaneously.WL2P_Q signal 51 is the Cos component of the P2 decoding circuit 212 output WL2P32 that disappear.D 223-226 is the latch cicuit of corresponding DSP module input pin.Totalizer 227 realizes the add operation mutually of L1_W estimated signal and L2_W estimated signal, and MUX 228 according to the input of the control selection latch D 229 of first pattern control pin (Mode[0]) 61 is and signal 58 or B pin latch signal 55.If select the output 58 of totalizer can realize maximum likelihood algorithm, and select the output 55 of latch D 224 to realize conventional Z track algorithm.The output 60 of latch D229 and L2_W 53 signal 62 by latch is latched by latch D 233 and to send into MUX 234 after multiplier 232 multiplies each other.L2_W 53 signals of C pin input are simultaneously sent into MUX 235 by latch D226.236 pairs of totalizers are sued for peace from the signal 66 of MUX 234 and the signal 67 of MUX 235 respectively, are latched and are exported by the P pin of DSP module by latch D237.Output signal is also sent into MUX 234 and 235 respectively simultaneously.Select latch D 233 output signals 64 as output when MUX 234, when MUX 235 was selected P pin output signal 68 as output, what this circuit was realized was to have W code encryption L2P sign indicating number treatment circuit.When MUX 234 selects signals 68 as output, when MUX 235 was selected signals 48 as output, this circuit is realized was to not with the L2P sign indicating number treatment circuit of W code encryption.The totalizer 236 of DSP module rearmost end all is designed to correlator circuit (promptly realizing by integrating circuit) with related circuit in dual mode.
See also shown in Figure 4ly again, should realize method based on above-mentioned baseband circuit structure to the GPSL2 signal trace, comprising following steps:
(1) described central processing unit is provided with L1 signal C/A sign indicating number to handle the baseband circuit module is trapped state, by adjusting C/A sign indicating number and L1 signal carrier the C/A sign indicating number is searched for;
(2) after the C/A sign indicating number obtains to catch, C/A sign indicating number and carrier wave are drawn and lock C/A sign indicating number ring and carrier wave ring, carry out tracking, begin to follow the tracks of the back and determine the navigation message zero-time, receive navigation message according to synchronous head information to L1 signal C/A sign indicating number;
(3) navigation message that is received is decoded, obtain ephemeris, almanac, temporal information, and the P1 sign indicating number generator 203 in the starting L1 signal P sign indicating number processing circuit module;
(4) described P1 sign indicating number generator 203 utilizes the status information of L1 signal P sign indicating number, and the P2 sign indicating number generator 213 in the starting L2 signal code track loop module, utilize L1 signal carrier value the initial search rate of L2 signal carrier to be set in proportion according to L1 signal and L2 signal carrier relation;
(5) whether determine L2 signal P sign indicating number by the W code encryption according to the navigation message of L1 signal C sign indicating number gained, and described DSP module working method is set in view of the above is to have the working method of W code encryption or not with the working method of W code encryption.
(6) described central processing module 219 reads the L2 signalling channel result data of described DSP module output, and according to the adjustment of the described L2 signal processing circuit of this result Data Control.
(7) adjust the time-delay of L2 signal P sign indicating number, search L2 signal P sign indicating number correlation peak location makes that L2 signal P sign indicating number obtains to catch;
(8) after L2 signal P sign indicating number obtains to catch, L2 signal P sign indicating number is drawn locking L2 signal P sign indicating number sign indicating number ring and L2 signal P sign indicating number carrier wave ring;
(9) output L1 signal and L2 signal carrier phase and carrier wave counting, and carry out follow-up data processing.
In the middle of reality was used, system saw also Fig. 4 to realizing to the tracing process of GPS L2 signal, and whole trace flow mainly was divided into for nine steps:
The first step 300---it is trapped state that the L1C/A sign indicating number is set, and by adjusting C/A sign indicating number and L1 carrier wave the C/A sign indicating number is searched for, and the C/A sign indicating number comprises 1023 states, constitutes two-dimensional search with carrier wave.
The 3rd step 302---navigation message is decoded, obtain information such as ephemeris, almanac, time, and starting L1-P sign indicating number.
The 4th goes on foot 303---and the P sign indicating number is made of four pn code generators, and after the starting of L1-P sign indicating number, L2-P sign indicating number corresponding state can obtain from L1-P sign indicating number generator.At this moment, from L1-P sign indicating number generator replication status information, starting L2-P sign indicating number generator utilizes the L1 carrier value according to L1 and L2 carrier wave relation the initial search rate of L2 carrier wave to be set, owing to there is the L1 carrier wave auxiliary, L2 does not need carrier wave is carried out blind search.
The 5th step 304---according to whether determining the L2P sign indicating number by the W code encryption, and be provided with in view of the above that DSP works in the working method that has the W code encryption or not with the working method of W code encryption by the navigation message of L1C sign indicating number gained.
The 6th step 305---microprocessor reads the L2 passage result data of DSP module output, and controls the adjustment of L2 circuit according to result of calculation.
The 7th step 306---because the ionosphere time-delay is different with L2 to L1, need to adjust the time-delay of L2-P sign indicating number, search L2-P sign indicating number correlation peak location makes the L2-P sign indicating number obtain to catch.
The 8th step 307---after obtaining to catch, the L2-P sign indicating number is drawn locking L2-P sign indicating number sign indicating number ring and locking L2-P sign indicating number carrier wave ring.
The 9th step 308---output L1 and L2 carrier phase and carrier wave counting are for follow-up data processing.
More than the implementation of given double-frequency GPS receiver L2 signal processing circuit, can be aided with the global design that corresponding control program and subsequent algorithm can realize double-frequency GPS receiver according to above scheme.
Adopted the baseband circuit structure of above-mentioned realization double-frequency GPS satellite signal receiver, owing to wherein realize based on the double-frequency GPS receiver baseband circuit of FPGA, consideration on combination property, implementation complexity, power consumption and the cost, signal is being carried out on the basis of many bit sample, after removing the P sign indicating number, despreading utilizes the cycle information of W sign indicating number, on the W sign indicating number cycle, carry out integration, on L1 signal and L2 signal, realize estimation respectively the W sign indicating number; Can carry out the characteristics that many bits high-speed digital signal is handled based on the built-in DSP module of FPGA then, by L1 be multiply by the influence of eliminating unknown W sign indicating number and modulating data mutually with the estimation W sign indicating number of L2, thereby realize tracking to the L2 signal, the speed and the performance of system have not only been improved greatly, greatly reduce the scale that total system realizes simultaneously, effectively reduce cost, further improved simultaneously the interference free performance of receiver, thereby on the basis of the performance that improves system significantly, reduced consumption to the FPGA resource, not only circuit structure is simple, and processing procedure is quick, and cost is lower, stable and reliable working performance, the scope of application are comparatively extensive.
In this instructions, the utility model is described with reference to its certain embodiments.But, still can make various modifications and conversion obviously and not deviate from spirit and scope of the present utility model.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (15)
1. baseband circuit structure that realizes the double-frequency GPS satellite signal receiver, comprise signal pre-processing circuit and several satellite treatment channel, the quantity of described satellite treatment channel is consistent with the number of satellite of being followed the tracks of, each satellite treatment channel all comprises L1 signal processing circuit and L2 signal processing circuit, described signal pre-processing circuit is connected with the central processing module of this receiver with the L2 signal processing circuit by described L1 signal processing circuit respectively, it is characterized in that, comprise L1 signal C/A sign indicating number processing baseband circuit module in the described L1 signal processing circuit, L1 signal P sign indicating number processing circuit module comprises L2 signal carrier track loop module in the described L2 signal processing circuit, L2 signal code track loop module, L2 signal W sign indicating number estimating circuit module, L1 signal and L2 signal cross multiplier (218), L2 signal correction device (220);
Described signal pre-processing circuit (239) is handled the baseband circuit module by described L1 signal C/A sign indicating number and is connected with described central processing module (219), and described L1 signal C/A sign indicating number processing baseband circuit module is connected with L2 signal cross multiplier (218) with described L1 signal by described L1 signal P sign indicating number processing circuit module;
Described signal pre-processing circuit (239) is connected with described central processing module (219) by described L2 signal carrier track loop module, and described L2 signal carrier track loop module is connected with described central processing module (219) with L2 signal cross multiplier (218), L2 signal correction device (220) by described L2 signal code track loop module, L2 signal W sign indicating number estimating circuit module, L1 signal successively;
Described L1 signal and L2 signal cross multiplier (218), L2 signal correction device (220) are arranged in the built-in DSP module of FPGA circuit module.
2. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 1 is characterized in that, described FPGA circuit module is the fpga chip of Xilinx company, and described DSP module is the DSP48A module in this fpga chip.
3. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 2 is characterized in that, has one 18 totalizers (227), one 18 multipliers (232) and one 48 totalizers (236) in the described DSP module.
4. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 3, it is characterized in that, described L1 signal and L2 signal cross multiplier (218) comprise first latch (223) in the DSP module, second latch (224), the 3rd latch (225), quad latch (229), the 5th latch (233), 18 totalizers (227), 18 multipliers (232), described L2 signal W sign indicating number estimating circuit module is successively by described first latch (223), 18 totalizers (227), quad latch (229), 18 multipliers (232), the 5th latch (233) is connected with described L2 signal correction device (220), described L1 signal P sign indicating number processing circuit module is connected by the input end of described second latch (224) with described 18 totalizers (227), and described L2 signal W sign indicating number estimating circuit module is connected by the input end of described the 3rd latch (225) with described 18 multipliers (232).
5. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 4, it is characterized in that, also comprise first MUX (228) in described L1 signal and the L2 signal cross multiplier (218), described first MUX (228) is serially connected with between described 18 totalizers (227) and the quad latch (229), and described second latch (224) is connected with the input end of described first MUX (228), and the input of described first MUX (228) selects control end to be connected with first pattern control pin (61) of described DSP module.
6. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 4 is characterized in that, also is serially connected with the 6th latch (231) between the input end of described the 3rd latch (225) and described 18 multipliers (232).
7. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 3, it is characterized in that, described L2 signal correction device (220) comprises 48 totalizers (236) and the 7th latch (237) in the DSP module, the output terminal of described L1 signal and L2 signal cross multiplier (218) is connected with described central processing module (219) by described 48 totalizers (236), the 7th latch (237) successively, and the output terminal of described the 7th latch (237) is connected with the input end of described 48 totalizers (236).
8. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 7, it is characterized in that, also comprise the 8th latch (226) in the described L2 signal correction device (220), second MUX (234), the 3rd MUX (235), described second MUX (234) is connected in series between the output terminal and described 48 totalizers (236) of described L1 signal and L2 signal cross multiplier (218), and the output terminal of described the 7th latch (237) is connected with the input end of described second MUX (234), the input of described second MUX (234) selects control end to be connected with second pattern control pin (69) of described DSP module, described the 3rd MUX (235) is connected in series between the input end of the output terminal of described the 7th latch (237) and described 48 totalizers (236), and described L2 signal W sign indicating number estimating circuit module is connected by the input end of described the 8th latch (226) with described the 3rd MUX (235), and the input of described the 3rd MUX (235) selects control end to be connected with the three-mode control pin (70) of described DSP module.
9. according to the baseband circuit structure of each described realization double-frequency GPS satellite signal receiver in the claim 1 to 8, it is characterized in that, described L1 signal C/A sign indicating number is handled the baseband circuit module and is comprised L1 signal carrier track loop module, L1 signal code track loop module and L1 signal correction device (217), and described signal pre-processing circuit (239) is connected with described central processing module (219) by described L1 signal carrier track loop module, L1 signal code track loop module, L1 signal correction device (217) successively.
10. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 9, it is characterized in that, described L1 signal carrier track loop module comprises L1 signal carrier digital controlled oscillator (200) and L1 signal complex mixers (201), described signal pre-processing circuit (239) is connected with described L1 signal code track loop module by described L1 signal complex mixers (201), and described L1 signal complex mixers (201) is connected with described central processing module (219) by described L1 signal carrier digital controlled oscillator (200).
11. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 10, it is characterized in that, described L1 signal code track loop module comprises L1 signal code digital controlled oscillator (202), ten frequency dividers (207), C/A sign indicating number generator (209) and first multiplier (210), described L1 signal code digital controlled oscillator (202) is by described ten frequency dividers (207), C/A sign indicating number generator (209) is connected with described L1 signal correction device (217) with first multiplier (210), described L1 signal complex mixers (201) is connected with the input end of described first multiplier (210), and described C/A sign indicating number generator (209) is connected with central processing module (219) with described L1 signal correction device (217) respectively.
12. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 11, it is characterized in that, described L1 signal P sign indicating number processing circuit module comprises P1 sign indicating number generator (203), second multiplier (208), W1 sign indicating number period generator (211) and W bit integrator (214), described L1 signal code digital controlled oscillator (202) is by described P1 sign indicating number generator (203), W1 sign indicating number period generator (211), W bit integrator (214) is connected with L2 signal cross multiplier (218) with described L1 signal, described P1 sign indicating number generator (203) is connected with described W bit integrator (214) by described second multiplier (208), and described L1 signal complex mixers (201) is connected with the input end of described second multiplier (208), and described P1 sign indicating number generator (203) is connected with described central processing module (219).
13. baseband circuit structure according to each described realization double-frequency GPS satellite signal receiver in the claim 1 to 8, it is characterized in that, described L2 signal carrier track loop module comprises L2 signal carrier digital controlled oscillator (205) and L2 signal complex mixers (204), described signal pre-processing circuit (239) is connected with described L2 signal code track loop module by described L2 signal complex mixers (204), and described L2 signal complex mixers (204) is connected with described central processing module (219) by described L2 signal carrier digital controlled oscillator (205).
14. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 13, it is characterized in that, described L2 signal code track loop module comprises L2 signal code digital controlled oscillator (206), the P2 sign indicating number generator (213) and the P2 decoding circuit (212) that disappears, described L2 signal code digital controlled oscillator (206) is connected with described L2 signal W sign indicating number estimating circuit module with the P2 decoding circuit (212) that disappears by described P2 sign indicating number generator (213) successively, described P2 sign indicating number generator (213) is connected with central processing module (219) with described L2 signal W sign indicating number estimating circuit module respectively, and described L2 signal complex mixers (204) is connected with the described P2 of disappearing decoding circuit (212).
15. the baseband circuit structure of realization double-frequency GPS satellite signal receiver according to claim 14, it is characterized in that, described L2 signal W sign indicating number estimating circuit module comprises W2 sign indicating number period generator (216) and W2 sign indicating number integrator (215), described P2 sign indicating number generator (213) is connected with L2 signal cross multiplier (218) with described L1 signal by described W2 sign indicating number period generator (216), W2 sign indicating number integrator (215) successively, and the described P2 of disappearing decoding circuit (212) is connected with described W2 sign indicating number integrator (215).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202721574U CN201532467U (en) | 2009-11-09 | 2009-11-09 | Structure of base-band circuit for double-frequency GPS satellite signal receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202721574U CN201532467U (en) | 2009-11-09 | 2009-11-09 | Structure of base-band circuit for double-frequency GPS satellite signal receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201532467U true CN201532467U (en) | 2010-07-21 |
Family
ID=42527870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009202721574U Expired - Lifetime CN201532467U (en) | 2009-11-09 | 2009-11-09 | Structure of base-band circuit for double-frequency GPS satellite signal receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201532467U (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011054225A1 (en) * | 2009-11-09 | 2011-05-12 | 上海华测导航技术有限公司 | Baseband circuit structure for realizing dual-frequency global positioning system (gps) satellite signal receiver and method thereof |
| CN102096081A (en) * | 2010-12-14 | 2011-06-15 | 东莞市泰斗微电子科技有限公司 | Carrier wave and pseudo-random code stripping circuit |
| CN103152072A (en) * | 2013-01-31 | 2013-06-12 | 南京航空航天大学 | P code generating method at random time |
| CN103163535A (en) * | 2013-03-15 | 2013-06-19 | 电子科技大学 | P code direct capturing method based on digital signal processor (DSP) |
| CN104253774A (en) * | 2014-09-16 | 2014-12-31 | 重庆邮电大学 | System and method for estimating Doppler frequency offset under high-dynamic environment |
| CN105607076A (en) * | 2015-12-23 | 2016-05-25 | 北京时代民芯科技有限公司 | Beidou 2nd generation B1 and B3 double-frequency receiver |
| CN111245450A (en) * | 2020-03-13 | 2020-06-05 | 华为技术有限公司 | Intelligent wearable device |
-
2009
- 2009-11-09 CN CN2009202721574U patent/CN201532467U/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011054225A1 (en) * | 2009-11-09 | 2011-05-12 | 上海华测导航技术有限公司 | Baseband circuit structure for realizing dual-frequency global positioning system (gps) satellite signal receiver and method thereof |
| CN102096081A (en) * | 2010-12-14 | 2011-06-15 | 东莞市泰斗微电子科技有限公司 | Carrier wave and pseudo-random code stripping circuit |
| CN103152072A (en) * | 2013-01-31 | 2013-06-12 | 南京航空航天大学 | P code generating method at random time |
| CN103163535A (en) * | 2013-03-15 | 2013-06-19 | 电子科技大学 | P code direct capturing method based on digital signal processor (DSP) |
| CN104253774A (en) * | 2014-09-16 | 2014-12-31 | 重庆邮电大学 | System and method for estimating Doppler frequency offset under high-dynamic environment |
| CN104253774B (en) * | 2014-09-16 | 2017-07-25 | 重庆邮电大学 | Doppler shift estimating system and method under a kind of high dynamic environment |
| CN105607076A (en) * | 2015-12-23 | 2016-05-25 | 北京时代民芯科技有限公司 | Beidou 2nd generation B1 and B3 double-frequency receiver |
| CN105607076B (en) * | 2015-12-23 | 2018-01-19 | 北京时代民芯科技有限公司 | A kind of Beidou II B1 and B3 dual-frequency receivers |
| CN111245450A (en) * | 2020-03-13 | 2020-06-05 | 华为技术有限公司 | Intelligent wearable device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101710180A (en) | Structure of base band circuit for realizing double frequency GPS satellite signal receiver and method thereof | |
| CN201532467U (en) | Structure of base-band circuit for double-frequency GPS satellite signal receiver | |
| CN102608626B (en) | High-sensitivity satellite navigation signal capturing method and system | |
| CN100554994C (en) | Obtain the device and method of spread-spectrum signal | |
| CN102901973B (en) | Beidou satellite-based method for fast capturing signals in real time | |
| CN101310192B (en) | Sample sequence processing signals | |
| CN100360953C (en) | Radio signal receiver with device for calibrating multi-way signal effect and method for starting receiver | |
| CN102890280B (en) | Compatibility capturing method of multi-mode GNSS (Global Navigation Satellite System) combination receiver | |
| CN101946188A (en) | Handle the satellite radio signal that is received | |
| CN104536016A (en) | GNSS new-system signal capturing device and method | |
| CN100501441C (en) | Method and system for locating a GPS correlated peak signal | |
| CN102116865A (en) | Supersensitive carrier tracking method for global navigation satellite system (GNSS) signal | |
| CN102854516A (en) | Method and system for estimating carrier-to-noise ratio in GNSS (Global Navigation Satellite System) receiver | |
| CN107450084A (en) | A kind of high sensitivity GNSS receiver and reacquisition implementation method based on CSAC | |
| US20070253471A1 (en) | Gps Receiver Using Differential Correlation | |
| CN104765052A (en) | GEO navigation satellite high-sensitivity carrier tracking method | |
| CN104931980B (en) | Carrier phase measurement half cycle obscures release method | |
| Hurskainen et al. | Multicore software-defined radio architecture for GNSS receiver signal processing | |
| CN102221701A (en) | Signal acquisition method, signal acquisition apparatus and electronic device | |
| CN102162853B (en) | Reception signal integrating method and receiver | |
| CN102857469A (en) | Quaternary phase-shift keying signal tracking method and device | |
| CN201126474Y (en) | Circuit for capturing GPS and Galileo satellite signal | |
| CN105068095A (en) | Tracking system and method for improving satellite pseudo range precision | |
| CN102023291A (en) | GPS (global position system) signal high-speed capturing device and method | |
| CN204462393U (en) | A kind of circuit structure of satellite-signal process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: COMNAV Free format text: FORMER OWNER: SHANGHAI HUACE NAVIGATION TECHNOLOGY CO., LTD. Effective date: 20121025 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 200233 XUHUI, SHANGHAI TO: 201103 MINHANG, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20121025 Address after: 2, E building, No. 2080, Lane 50, Lianhua Road, 201103, Shanghai, Minhang District Patentee after: ComNav Technology Ltd. Address before: 200233 building 35, building 680, 5 Guiping Road, Shanghai Patentee before: CHC Technology Co., Ltd. |
|
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 2, E building, No. 2080, Lane 50, Lianhua Road, 201103, Shanghai, Minhang District Patentee after: SHANGHAI SINAN SATELLITE NAVIGATION TECHNOLOGY CO., LTD. Address before: 2, E building, No. 2080, Lane 50, Lianhua Road, 201103, Shanghai, Minhang District Patentee before: ComNav Technology Ltd. |
|
| DD01 | Delivery of document by public notice |
Addressee: Yuan Yuping Document name: Notification of Passing Examination on Formalities |
|
| CX01 | Expiry of patent term |
Granted publication date: 20100721 |
|
| CX01 | Expiry of patent term |