CN201383850Y - Wideband phase lock loop frequency synthesizer and digital television reception terminal - Google Patents

Abstract

The utility model provides a wideband phase lock loop frequency synthesizer which comprises a tuner (10), a high-pass filter (20) and an amplifier (30), wherein the tuner (10) is used for converting the frequency of input radio frequency signals into a set intermediate frequency, and at least comprises a first phase lock loop circuit (PLL1) including a plurality of narrowband VCOs, and a serial control interface for setting the frequency dividing ratio of the first phase lock loop circuit (PLL1) to produce a first local oscillation signal (LO1) with a specific frequency, wherein the first phase lock loop circuit (PLL1) is used for producing the first local oscillation signal (LO1); the serial control interface is connected with the first phase lock loop circuit (PLL1); and the high-pass filter (20) and the amplifier (30) are coupled with a resonant tank of the first phase loop ring circuit (PLL1). The wideband phase lock loop frequency synthesizer has the advantages of low cost and good phase noise and spurious rejection indicators, and can be widely used in the front end equipment of various televisions adopting tuners.

Description

Broadband phase-looked loop frequency synthesizer and receiving terminal for digital television

Technical field

The utility model relates to a kind of frequency synthesizer, especially relates to a kind of utilization and is integrated in the inner wideband frequency synthesizer that is obtained by a plurality of arrowbands voltage controlled oscillators (VCO) and broadband phase-looked loop circuit (PLL) of tuner (Tuner).

Background technology

Frequency synthesizer is a key modules in transceiver and the clock generation circuit.The function of frequency synthesizer is: with certain Frequency point is the center, near the certain frequency scope this central point, can produce any certain frequency in this frequency range by certain control method.Usually, requirement to a frequency synthesizer adjustable extent is: adjustable extent reaches 20% of centre frequency, be used for compensating frequency synthesizer integrated chip when caused performance change of production process of semiconductor process and frequency of utilization synthesizer integrated chip variation of ambient temperature to the influence of systematic function.For the application of broadband application or multiband, the adjustable extent that then needs is bigger.

As shown in Figure 1, the structure of Chang Yong wideband frequency synthesizer comprises: parametric frequency divider, phase frequency detector, active loop filter, broadband voltage-controlled oscillator (VCO, Voltage Controlled Oscillator) and feedback divider; Loop filter can adopt high supply power voltage, and wide tuning voltage scope is provided, and the collocation wideband voltage controlled oscillator can provide wide reference frequency output.But, the wideband frequency synthesizer of employing active loop filter construction, because the operational amplifier in the wideband frequency synthesizer can be introduced extra noise, so the phase noise index is bad; And adopt independent wideband voltage controlled oscillator to have the shortcoming that cost is higher, price is more expensive.

The utility model content

The utility model proposes a kind of utilization and be integrated in the inner wideband frequency synthesizer by a plurality of arrowbands voltage controlled oscillators (VCO) and broadband phase-looked loop circuit (PLL) acquisition of tuner (Tuner),, phase noise with low cost to obtain and spuious inhibition index be the wideband frequency synthesizer preferably.

For solving technical problem of the present utility model, the utility model discloses a kind of broadband phase-looked loop frequency synthesizer, and it comprises:

With the radiofrequency signal frequency conversion of input is the tuner of the IF-FRE of setting, and it comprises at least: comprise first phase-locked loop circuit of a plurality of arrowband VCO, produce first local oscillation signal; Be used to set the frequency dividing ratio of first phase-locked loop circuit, make the serial control interface of first local oscillation signal that produces characteristic frequency, it connects first phase-locked loop circuit;

To the high pass filter that first local oscillation signal carries out filtering, it is coupled in the resonant groove path of first phase-locked loop circuit;

With the amplifier of the first local oscillation signal rate of doing work processing and amplifying, it connects high pass filter.

Preferably, described high pass filter connects described resonant groove path by coupling capacitance.

Preferably, described first voltage controlled oscillator is the arrowband voltage controlled oscillator.

Preferably, described frequency dividing ratio comprises integer part and fractional part; The output frequency that described integer part equals to expect is divided by reference frequency and round; Described fractional part equal output frequency to expectation multiply by divided by reference frequency and after deducting described integer part round up after 64 near integer.

Preferably, to be arranged at address in first phase-locked loop circuit be among 02 the LO1C2 register to described integer part.

Preferably, to be arranged at address in first phase-locked loop circuit be the 5th and the 6th of 03 LO2C1 register to low two of described fractional part, and all the other 4 of described fractional part be arranged at address in first phase-locked loop circuit be 01 LO1C1 register hang down 4.

Preferably, described reference frequency is the frequency of oscillation of crystal oscillator 16MHz.

Preferably, described tuner also comprises:

Second local oscillator by second voltage controlled oscillator and second phase-locked loop circuit constitute produces second local oscillation signal, and second phase-locked loop circuit connects described serial control interface;

First, second frequency mixer that connects first phase-locked loop circuit and second phase-locked loop circuit respectively, and first, second frequency mixer connects by filter;

Receive the variable gain low-noise amplifier of input radio frequency signal, it connects first frequency mixer;

Be connected the variable gain amplifier of second mixer output.

Preferably, described second voltage controlled oscillator is the arrowband voltage controlled oscillator that has with the described first voltage controlled oscillator different center frequency.

Compared with prior art, the utlity model has following beneficial effect:

The utility model is the local oscillation signal that resonant groove path leaked that utilizes tuner, local oscillation signal power is amplified, obtain a wideband frequency synthesizer, have with low cost, phase noise and spuious inhibition index advantage preferably, can be widely used among the various television headend equipment such as modulator.

Description of drawings

Fig. 1 is the structural representation of existing wideband frequency synthesizer;

Fig. 2 is the structural representation of the wideband frequency synthesizer that the utility model proposes;

Fig. 3 is the electrical block diagram of tuner among Fig. 2;

Fig. 4 is the electrical block diagram of phase-locked loop circuit among Fig. 3;

Fig. 5 is the electrical block diagram of high pass filter and amplifier among Fig. 2.

Embodiment

The utility model is the local oscillator that resonant groove path leaked (the Local Oscillator that utilizes tuner (Tuner), LO) signal, local oscillation signal power is amplified, obtain one cheap, make an uproar and wideband frequency synthesizer that spuious inhibition index is comparatively excellent mutually.Therefore, wideband frequency synthesizer of the present utility model is used in the equipment with tuner, such as the set-top box of cable TV.

As shown in Figure 2, the wideband frequency synthesizer that the utility model proposes is composed in series by tuner 10, high pass filter 20 and the amplifier 30 of phase loop circuit with lock, the local oscillation signal that resonant groove path leaked of tuner 10 is exported to high pass filter 20 filtering low frequency noises, undertaken exporting certain frequency signal after the processing and amplifying by amplifier 30.

Tuner 10 can adopt the monolithic tuning chip that is used in the CATV set-top-box, such as being the tuning chip of MT2060 for model.MT2060 is a single-chip multifrequency tuner that advances rank type, low electric power consumption, uses in digital cable environment, needs on the low synthetic distortion and the high-effect cable modem of noise, the digital machine devices such as box, and makes it reach optimization; And can receive the frequency of 48MHz～860MHz, and convert medium standard frequency 30MHz～60MHz to.The low near-end phase place noise of MT2060 is held concurrently it and can be used in number and analog signal, and comprises each field of video signal, message and high-speed information, and its internal structure is seen shown in Figure 3:

Respectively by first voltage controlled oscillator (Voltage Controlled Oscillator, VOC) VOC1 and first phase-locked loop circuit (Phase-Locked Loop, PLL) (Local Oscillator LO), produces the first local oscillation signal LO1 to first local oscillator of PLL1 formation; Second local oscillator by the second voltage controlled oscillator VOC2 and the second phase-locked loop circuit PLL2 constitute produces the second local oscillation signal LO2; 2 frequency mixer MIX1 and MIX2 that receive the first local oscillation signal LO1 and the second local oscillation signal LO2 respectively; Frequency is radiofrequency signal (the Radio Frequency of 48MHz～860MHz, RF) from variable gain low-noise amplifier (Variable-gain Low Noise Amplifiers, VLNA) after the input, on the IF-FRE that the double conversion by frequency mixer MIX1 and MIX2 is set the input rf signal frequency spectrum shift to the user; And two variable gain amplifiers (Automatic GainControl AGC) is used for finishing automatic gain control (AGC) function; Serial control interface is used for its register is configured, and finishes the function of appointment.

Because the power of the first local oscillation signal LO1 that leaks out in the resonant groove path position of the first phase-locked loop circuit PLL1 is the strongest, therefore, the utility model is by the resonant groove path (VCO_CH1) at the first phase-locked loop circuit PLL1, take out the first local oscillation signal LO1 that leaks by a coupling capacitance C441, as shown in Figure 4.

Because the first local oscillation signal LO1 power that is coupled out is less, a little more than 70dBuv, also needs it is amplified, and could drive the frequency mixer MIX1 and the MIX2 of back.The first local oscillation signal LO1 that takes out through high pass filter 20 filtering, after outer spuious of filtering band, is amplified through amplifier 30 again.Wherein, the electrical block diagram of high pass filter 20 and amplifier 30 as shown in Figure 5.The excursion of the first local oscillation signal LO1 is 1088MHz～2214MHz, and therefore, the utility model can obtain the wideband frequency synthesizer of a 1270MHz～2070MHz.

For the first phase-locked loop circuit PLL1 that makes tuner 10 produces the specific output frequency that the user needs, need carry out the control command write operation to the register of the first phase-locked loop circuit PLL1 inside by serial control interface realizes the frequency dividing ratio of the first phase-locked loop circuit PLL1 is provided with: because the first phase-locked loop circuit PLL1 is the phase-locked loop of a fractional frequency division, its frequency dividing ratio comprises integer part DIV1 and fractional part NUM ₁If the output frequency of expectation is f _LO, then the computing formula of frequency dividing ratio is:

Expression round numbers part.f _REFRepresent reference frequency, be the frequency of oscillation of crystal oscillator 16MHz.

${\mathrm{NUM}}_1=\mathrm{floor}(64\×\frac{f_{\mathrm{LO}}-{\mathrm{DIV}}_1\×f_{\mathrm{REF}}}{f_{\mathrm{REF}}}),$ Floor () expression is rounded up to immediate integer.

DIV ₁And NUM ₁The address of the register at place and being defined as follows shown in the table 1, last of this table 1 classified its default value as.

Table 1

As known from Table 1,, need the register of configuration to comprise for the frequency dividing ratio of the first phase-locked loop circuit PLL1 is set: LO1C1, LO1C2 and LO2C1, default value is then composed in the position that certain is not used for register in assignment; The control register that is positioned at address " 0x0C " in addition also must be configured.Therefore configuration register process and the order setpoint frequency the time is as follows:

Register Value；

0x0C 0xFF；

0x01 0x30+NUM ₁＞＞2; "＞＞" the expression right-shift operation;

0x02 DIV ₁；

0x03 (NUM ₁?mod?4)＜＜4

After being configured, register,, judges whether the first phase-locked loop circuit PLL1 has entered lock-out state by reading the value of address for the register of " 0x06 " through first scheduled time (such as 5ms).Wherein, the address is defined as follows shown in the table 2 for the register of " 0x06 ":

Table 2

Be " 0x80 " if obtain the address for the value of the register of " 0x06 ", promptly " L1LK " position is 1, represents that then the first phase-locked loop circuit PLL1 has entered lock-out state; If surpass second scheduled time (such as 200ms), the address still is 0 for the value of the register of " 0x06 ", then can judge the first phase-locked loop circuit PLL1 success locking of failing.

In addition, because the voltage controlled oscillator in the tuner 10 is to be made of the different arrowband voltage controlled oscillator of a plurality of centre frequencies, therefore no longer need high-tension tuning voltage, entire chip adopts the 3.3V power supply, to the power supply design easily; In addition, compare with wideband voltage controlled oscillator, the discriminator sensitivity of arrowband voltage controlled oscillator is lower, and therefore the phase noise index of output is better, and its output phase noise objective is as follows:

1KHz-82dBc/Hz

10KHz-86dBc/Hz

100KHz-107dBc/Hz

In addition, the minimum frequency stepping of the wideband frequency synthesizer that the utility model proposes is 16MHz/64, i.e. 250KHz, and spuious inhibition index is greater than 56dBc.

Claims (8)

1, a kind of broadband phase-looked loop frequency synthesizer is characterized in that, comprising:

With the radiofrequency signal frequency conversion of input is the tuner (10) of the IF-FRE of setting, and it comprises at least: comprise first phase-locked loop circuit (PLL1) of a plurality of arrowband VCO, produce first local oscillation signal (LO1); With the frequency dividing ratio that is used to set first phase-locked loop circuit (PLL1), make the serial control interface of first local oscillation signal (LO1) that produces characteristic frequency, it connects first phase-locked loop circuit (PLL1);

To the high pass filter (20) that first local oscillation signal (LO1) carries out filtering, it is coupled in the resonant groove path of first phase-locked loop circuit (PLL1);

With the amplifier (30) of first local oscillation signal (LO1) rate of doing work processing and amplifying, it connects high pass filter (20).

According to the described broadband phase-looked loop frequency synthesizer of claim 1, it is characterized in that 2, described high pass filter (20) connects described resonant groove path by coupling capacitance (C441).

According to the described broadband phase-looked loop frequency synthesizer of claim 1, it is characterized in that 3, described first voltage controlled oscillator (VOC1) is the arrowband voltage controlled oscillator.

According to the described broadband phase-looked loop frequency synthesizer of claim 1, it is characterized in that 4, it is among 02 the LO1C2 register that the integer part of described frequency dividing ratio is arranged at address in first phase-locked loop circuit (PLL1).

5, according to the described broadband phase-looked loop frequency synthesizer of claim 1, it is characterized in that, to be arranged at address in first phase-locked loop circuit (PLL1) be the 5th and the 6th of 03 LO2C1 register to low two of the fractional part of described frequency dividing ratio, and all the other 4 of described fractional part be arranged at address in first phase-locked loop circuit (PLL1) be 01 LO1C1 register hang down 4.

According to the described broadband phase-looked loop frequency synthesizer of claim 1, it is characterized in that 6, described tuner (10) also comprises:

Second local oscillator by second voltage controlled oscillator (VOC2) and second phase-locked loop circuit (PLL2) constitute produces second local oscillation signal (LO2), and second phase-locked loop circuit (PLL2) connects described serial control interface;

First, second frequency mixer (MIX1 and MIX2) that connects first phase-locked loop circuit (PLL1) and second phase-locked loop circuit (PLL2) respectively, and first, second frequency mixer (MIX1 and MIX2) is connected by filter;

Receive the variable gain low-noise amplifier of input radio frequency signal, it connects first frequency mixer (MIX1);

Be connected the variable gain amplifier of second frequency mixer (MIX2) output.

According to the described broadband phase-looked loop frequency synthesizer of claim 6, it is characterized in that 7, described second voltage controlled oscillator (VOC2) is for having the arrowband voltage controlled oscillator with described first voltage controlled oscillator (VOC1) different center frequency.

8, a kind of receiving terminal for digital television is characterized in that, comprises each described broadband lock ring frequency synthesizer of claim 1 to 7.

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