CN201374192Y - Flash memory device - Google Patents
Flash memory device Download PDFInfo
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- CN201374192Y CN201374192Y CN200820215150U CN200820215150U CN201374192Y CN 201374192 Y CN201374192 Y CN 201374192Y CN 200820215150 U CN200820215150 U CN 200820215150U CN 200820215150 U CN200820215150 U CN 200820215150U CN 201374192 Y CN201374192 Y CN 201374192Y
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Abstract
The utility model discloses a flash memory device, which comprises a microprocessor, a host computer interface, an internal buffer memory, a flash memory controller array and a flash memory chip array which are connected through a flash memory bus; the data line width of a flash memory controller (401) is in (N multiplied by W) bits, and the flash memory controller (401) has a data repeating and reusing unit (514) and a data transfer logical unit (654); a control bus (410) is respectively connected with the data bus and a flash memory chip (402); the data repeating and reusing unit (514) copies the command into N equal parts, and transfers the command to the flash memory chip (402) through the control bus (410); the data transfer logical unit (654) can uniformly divide the data in (N multiplied by W) bits into N equal parts, or can restore the data in N equal parts back to the data in (N multiplied by W) bits; and the data bus can transfer the state information of the flash memory chip (402). The utility model can improve the storage capacity, lower the cost and reduce the size.
Description
Technical field
The utility model relates to a kind of flash memory device, more specifically, relates to a kind of flash memory device of many flash chips.
Background technology
Flash memory because its have high density, high capacity, characteristics such as lower read-write operation is consuming time, and is non-volatile and more and more wider be used to various fields; Compare with mechanical disk, a main benefit of use flash memory solid-state disk is the superior anti-vibration resistance of itself, another main benefit is the system performance of its remarkable improvement, mainly show random access speed faster (per second 10 megabyte), it only needs lower power consumption simultaneously, and can be applicable to bigger operating temperature range.But, some drawbacks limit that flash chip self exists the application of this class storer.One, because flash chip monolithic density (having only several thousand megabyte usually) still is far smaller than mechanical disk (a hundreds of thousands megabyte usually), so jumbo flash disk must be made up of a lot of flash chips (flash array), just can be used as the general data storer, to substitute mechanical disk.
Although the access speed of existing flash disk is fast much than mechanical disk, but the read or write speed of monolithic flash chip or single internal bus approximately is subject to per second 25 megabyte, interfacing (optical fiber interface per second 200 to 400 megabyte with medium, serial ATA interface per second 150 to 300 megabyte, serial scsi interface per second 300 to 600 megabyte) compare, also differ greatly.In addition, before writing flash chip, flash chip must be wiped free of and confirm wiping of its success, and it is relatively slow to write flash chip, and this also can reduce the performance of system significantly.
In the general flash memory device a large amount of flash chips is arranged, numerous flash chips is lined up several line number row, constitutes the high-capacity flash memory array.On macroscopic view, all flash chips are while concurrent reading and concurrent writings, the concurrent reading and concurrent writing of while really of different flash controllers, yet, to a specific flash controller, if we check its internal bus, all data transmission are serial on internal bus, data are transferred to the first row flash chip earlier, and data are transferred to the second row flash chip earlier then, by that analogy.The data rate of flash memory row is subject to the internal bus that this is shared.
Chinese patent application 200710072980.6,200710073655.1,200710074355.5 etc. provides similar flash controller and flash memory array management way, in itself, the data transmission of flash array remains on the row internal bus of sharing serial.
Flash chip producer usually produces 8 or 16 s' flash chip, in order to support the not flash chip of isotopic number and different manufacturers, flash controller also is manufactured into 8 bit data live width flash controllers (hereinafter to be referred as " 8 bit flash memory controller ") or 16 bit data live width flash controllers (hereinafter to be referred as " 16 bit flash memory controller ") usually.These two kinds of flash controllers Comparatively speaking, 1.5 times of the volume of 16 bit flash memory controllers the chances are 8 bit flash memory controllers, 1.5 times of its price also the chances are 8 bit flash memory controllers.In the general flash memory device all is that 16 bit flash memory controllers connect 16 bit flash memory chips, and 8 bit flash memory controllers connect 8 bit flash memory chips.The equal capacity flash memory device that adopts above-mentioned two kinds of different connected modes to produce is compared, and 16 flash memory device readwrite performance is better as can be known, but the cost of flash controller is higher, and volume is bigger; Though 8 flash memory device flash controller volume is less, low-cost, read or write speed but is restricted.
The utility model content
The purpose of this utility model is to provide a kind of flash memory device, and it can improve capacity, and further reduce cost, reduced volume.
For achieving the above object, the utility model is achieved through the following technical solutions:
Flash memory device, generally comprise array, the flash chip formed by internal bus microprocessor linked, host interface, inner buffer, flash controller and constitute the flash memory cell array, flash controller connects flash memory cell, all flash controller arrays are shared an internal bus, described flash controller contains a data repetition and Multiplexing Unit and a data transmission logical block, and the data bus of described flash controller is N
*(N is the natural number greater than 2 in the W position, W is a natural number), flash memory cell is made up of N flash chip, the data bus of flash chip is the W position, flash chip in flash controller control bus and all flash memory cells is connected respectively, and the data bus of flash controller is divided into the N equal portions, and be connected respectively with N flash chip of corresponding with it flash memory cell, data repeat with multiplexing logical block can with from flash controller write or reading order copies as the N equal portions, the data command bus can be transferred to N flash chip respectively with order, and the data transfer logic unit can be with N
*The data of W position are divided into the N equal portions or are N with the reduction of data of N equal portions
*The data of W position, the data command bus can with data in flash controller the data transfer logic unit and flash chip between transmit, can also transmit simultaneously the status information of each flash chip.
As a kind of preferred version of the present utility model, the flash controller that this technical scheme can apply to 16 bit data live widths is controlled the flash memory cell array of 8 bit data live widths.This flash memory device comprises the flash controller of a microprocessor, one or more host interface, internally cached, a plurality of 16 bit data live widths and the flash chip array of 8 bit data live widths.Flash memory device receives the operational order that host application program is sent by host interface, interface is passed to interface controller to order then, Host Command is resolved to the operational order of bottom by embedded software in the interface controller and microcontroller, issue flash controller then, last flash controller becomes the flash memory control signal to command analysis, controls the operation of flash array.Flash array is divided into several line number row, and different flash controllers is used for controlling different flash memory row, and each flash controller selects all flash chips of controlling within these row with a shared internal bus by chip slapper.Flash memory cell on the each row and column is made up of the flash chip of two 8 bit data live widths: chip 0 and chip 1.The flash chip connected mode of this novelty utilizes the flash controller of one 16 bit data live width to connect the flash chip of two 8 bit data live widths, the capacity of flash disk is increased, volume reduces, cost reduces.The control bus of flash controller need be connected on two flash chips simultaneously, like this, two flash chips will receive flash command, flash command address, reading simultaneously, flash controller can read the ready signal of two flash chips simultaneously, to determine the state of flash chip.Flash controller is delivered to flash command on two flash chips simultaneously, and two flash chips are all finished order by the time, just can continue next step operation.16 Bit datas that transmission is come out in the flash controller all are divided into strange and even byte.The byte of even number is linked flash chip 0, and odd byte is then linked flash chip 1.Like this, 16 bit data bus of flash controller just have been fully utilized.
As a kind of preferred version of the present utility model, after the status information of flash chip reads by data bus, can repeat to read by main frame through data with the one group of data that is treated as of Multiplexing Unit, also can not handle direct separated into two parts and read by main frame.
As a kind of preferred version of the present utility model, the data command bus of flash controller can be connected with the flash chip dislocation, promptly need not to connect successively in order.
As a preferred embodiment of the present invention, the concrete status information of each flash chip of flash memory cell also can be delivered to flash controller by ready signal.
As a preferred embodiment of the present invention, the data command bus is multiplexing single line, also can be not multiplexing.
As a preferred embodiment of the present invention, control bus is shared.
For the flash controller of 16 given bit data live widths, the present invention can connect the flash chip of two 8 bit data live widths, thereby can increase the capacity of flash disk; Compare with the flash chip of 16 bit data live widths with the flash controller of 16 bit data live widths, the capacity of flash disk has increased by one times; Compare with the flash chip of 8 bit data live widths with the flash controller of 8 bit data live widths, the capacity of flash disk has increased by one times, and read or write speed has also increased by one times; Compare with the flash chip of two 8 bit data live widths with the flash controller of two 8 bit data live widths, the cost of flash controller has reduced about 30 percent;
Owing to adopt a multi-step controller to connect the connected mode of a plurality of flash chips, having increased simultaneously data in flash controller repeats and multiplexing logical block, data transfer logic unit, make from the control command of main frame and data after passing through the relevant treatment of flash controller, order and data can be transferred to a plurality of flash chips that are attached thereto simultaneously, thereby can realize that a controller controls a plurality of flash chips.After taking this technical scheme, can reduce use amount, the increase capacity of flash controller or reduce cost, reduced volume.For example, the flash memory device that connects two 8 chips with each 16 level controller is connected 16 chips and compares with each 16 level controller, can not increase the flash memory device volume and not undermine under the prerequisite of its readwrite performance, increase the capacity of memory storage; Be connected two 8 chips with two 8 chips of two 8 level controller connections with one 16 level controller and compare, can under the prerequisite that does not undermine readwrite performance, reduce the quantity of controller, reduce cost, dwindle the volume of memory storage.
In addition, adopt the utility model can further reduce the quantity of encapsulation, reduce cost and volume, less on the other hand flash controller also can further reduce the workload of CPU.
Simultaneously should be appreciated that the memory device of this utility model indication does not include only nand flash memory, the nonvolatile memory device that also comprises simultaneously other kinds, such as, NOR Flash, Ovonic Universal Memory (OUM), and Magnetoresistive RAM (MRAM).
Description of drawings
Below in conjunction with the drawings and specific embodiments the utility model is described in further detail.
Fig. 1 is existing flash memory storage apparatus basic structure synoptic diagram.
Fig. 2 is the synoptic diagram how 16 bit data live width flash controllers connect 16 bit data live width flash chips.
Fig. 3 is the synoptic diagram how 8 bit data live width flash controllers connect 8 bit data live width flash chips.
Fig. 4 is the synoptic diagram that how 16 bit data live width flash controllers connect two 8 bit data live width flash chips among the utility model embodiment.
Fig. 5 is the hardware pipeline figure that how control command is transferred to each flash chip among the utility model embodiment.
Fig. 6 is the hardware pipeline figure that data stored by flash memory writes and reads among the utility model embodiment.
Fig. 7 is how the utility model is with a N
*The flash controller of W bit data live width is connected to the synoptic diagram of the flash chip of N W bit data live width.
Embodiment
Fig. 1 is existing flash memory storage apparatus basic structure synoptic diagram, can explain application of the present utility model, can reach more superior memory property and capacity by utilizing method of attachment described in the utility model.Memory device 100 shown in Figure 1 comprises an embedded microprocessor 110, host interface 160 and 120, one flash memory internal buss 130 of 161, one memory buffer of a host interface controller, flash controller 140 and a flash chip array 150.The quantity of flash controller and in each row module the quantity of flash chip depend on system and dispose.
Embedded microprocessor 110 is realized the calculating and the control function of storer 100.Particularly, microprocessor 110 receives the storage signal of sending from host interface 160, decoding and fill order.In order to finish the order of main frame, when and how the requirement that microprocessor 110 needs according to optimal system performance is gone to control data is transmitted in flash chip array 150 and cushions between the storer 120 to the FlashDMA in the 140h with flash controller 140a; And when and how control be transmitted in the HostDMA of data with 160 li of host interface controllers between memory buffer 120 and the host interface 160.Flash controller 140 comprises that a series of row module flash controller 140a are to 140h.The FlashDMA of each row module flash controller and it, by the internal bus of sharing, controlling flash memory row 150a, a 150b ... 150h, each row module comprises a series of flash memory lines unit.In existing flash memories, each flash memory provisional capital is an independently physical memory chip.Row module flash controller by the chip slapper signal data transmission to each flush memory device.When the data transmission of certain flash memory lines finishes, and the data of this row also are being busy with writing fashionable, and flash chip allows its chip selection signal to be cancelled.Thereby all need transfer to the data of each flash memory row can being arranged on the row module controls data bus by pipeline system.
In order to describe the utility model better, Fig. 2, Fig. 3 have shown the connected mode between present flash controller and the flash chip.
Fig. 4 has shown how the utility model connects together with two 8 bit flash memory chips 402 16 bit flash memory controllers 401 with 403.The control bus 410 of flash controller is used for transfer instruction and addressing information to the control separated time 411 of flash chip 402, also is transferred to the control separated time 412 of flash chip 403 simultaneously.Therefore, flash chip 402 and 403 can receive same instruction simultaneously and look for the address, and two devices will can be carried out from the instruction of flash controller 401 simultaneously.16 data bus is through being divided into least-significant byte 420 and most-significant byte 421 during the data transfer logic unit in the flash controller, and least-significant byte is connected to flash chip 402, and simultaneously, most-significant byte is connected to flash chip 403.When the instruction of sending from flash controller 401 is to write, the even byte of coming from 16 bit flash memory data buss will be stored in flash chip 402 by data bus 420; Odd byte then is stored in flash chip 403 by bus 421.When the instruction of sending is when reading, even byte will be read by data bus 420 from flash chip 402, and odd byte will be read by data bus 421 from flash chip 403.Data bus and control bus can be multiplexing, promptly same single line.
However, even if same instruction is dealt into flash chip 402 and 403 simultaneously, flash chip 402 and 403 also may not finish execution command simultaneously, and they can reply out different states at the same time.Therefore need read the status information of flash chip, the status information of two flash chips can be transferred to flash controller 401 by 8 bit data bus 420 and 421 respectively, also can be to deliver to flash controller by ready signal.Status information by data bus transmission than the ready signal transmission in detail, can learn and whether finish, whether success.
Fig. 5 has shown how control command among the utility model embodiment is transferred to the hardware pipeline figure of each flash chip.Order of the prior art is at least-significant byte, so be duplicated into two parts when the order of least-significant byte repeats with Multiplexing Unit 514 through data, a command transfer is given flash chip 402, and another same command transfer is given flash chip 403.
Fig. 6 and Fig. 7 have shown writing the storage data and reading the hardware pipeline of storing data of flash controller respectively.
Fig. 6 show data stored by flash memory to write the hardware data flow process as follows: embedded software is provided with dma controller 652, and hardware ECC circuit 653 also operates on this 16 position datawire.This 16 bit data is divided into even bytes and odd bytes by data transfer logic unit 654, and even bytes is written to flash chip 402, and odd bytes is written to flash chip 403, and this comprises data stored by flash memory itself and the error checking and correction position that is produced.Fig. 7 show data stored by flash memory to read the hardware data flow process as follows: embedded software is provided with dma controller 652, read even bytes in the external flash chip 402 and the odd bytes in the flash chip 403, hardware ECC circuit 653 also operates on this 16 bit data, also reads the odd bytes check bit in the even bytes check bit sum flash chip 403 in the external flash chip 402 simultaneously.Even bytes and odd bytes are reduced to 16 data through the processing of data transfer logic unit 654, are transferred to flash controller, comprise data stored by flash memory itself and the error checking and correction position that is produced.
How Fig. 8 has summarized the utility model with a N
*The flash controller of W bit wide is linked on the flash chip of N W bit wide.
The control bus 840 that comes from flash controller carries instruction and addressing information to flash chip 0,1,2 ...., 7 control bus 810,811 ... .., 817.Thereby all flash chips 802,803 ...., 807 all receive same instruction and look for the address.
The N that comes out from flash controller
*The w bit data bus is divided into the N section.Data bus [w-1 to the 0] position of flash controller is connected to [w-1 to 0] position of flash chip 0; The data bus [2 of flash controller
*W-1 is to w] position be connected to flash chip 1 [w-1 to 0] position; By that analogy ... the data bus [N of .. flash controller
*W-1 is to (N-1)
*W] position be connected to flash chip N-1 [w-1 to 0] position; Although be sent on all flash chips in same same order of time, these flash chips are unnecessary yet finishes instruction in the identical time.The status information of flash chip will be sent flash controller back to by the corresponding data line.
Claims (7)
1. flash memory device, comprise at least one microprocessor that connects by the flash memory bus, at least one host interface, at least one inner buffer, the array that the flash controller of long numeric data live width is formed, the flash chip of long numeric data live width constitutes the flash memory cell array, each flash controller connects a row flash memory cell, it is characterized in that: described flash controller (401) contains data to be repeated and a Multiplexing Unit (514) and a data transmission logical block (654), the data live width of described flash controller is the N*W position, N is the natural number greater than 2, W is a natural number, described flash memory cell is that W bit flash memory chip (402) is formed by N data live width, the end that described flash controller control bus (410) is connected with flash chip has N port, and a corresponding with it flash memory cell N flash chip (402) connects respectively, and the data command bus of described flash controller is divided into the N equal portions, and be connected respectively with N the flash chip (402) of corresponding with it flash memory cell, described data repeat the write or read order from flash controller to be copied as the N equal portions with multiplexing logical block (514), described control bus (410) can be transferred to the write or read order respectively N flash chip (402), described data transfer logic unit (654) can be divided into the N equal portions with the data of (N*W) position, and can be (N*W) bit data further with the reduction of data of N equal portions, described data command bus can be transmitted data between data transfer logic unit (654) and flash chip (402), the data command bus can also be transmitted the status information of each flash chip (402) simultaneously.
2. flash memory device according to claim 1, it is characterized in that: described flash memory cell is made of two 8 bit flash memory chips (402), described flash controller (401) is 16 bit data live widths, wherein least-significant byte is connected on the flash chip, and most-significant byte is connected on the other flash chip.
3. flash memory device according to claim 2 is characterized in that: described data transfer logic unit (654) is divided into odd bytes or even bytes two equal portions with 16 bit data.
4. according to the described flash memory device of any one claim of claim 1 to 3, it is characterized in that: the status information of described flash chip (402) can be sent to flash controller (401) by ready signal.
5. according to the described flash memory device of any one claim of claim 1 to 3, it is characterized in that: described data bus and command line can be two not multiplexing lines.
6. according to the described flash memory device of any one claim of claim 1 to 3, it is characterized in that: after the status information of described flash chip reads by the data command bus, can repeat to read by main frame through data, also can not handle direct separated into two parts data and read respectively by main frame with the one group of data that is treated as of Multiplexing Unit (654).
7. flash memory device according to claim 1 is characterized in that: the data command bus of flash controller can be connected with the flash chip dislocation, promptly need not to connect successively in order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200820215150U CN201374192Y (en) | 2008-12-12 | 2008-12-12 | Flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200820215150U CN201374192Y (en) | 2008-12-12 | 2008-12-12 | Flash memory device |
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| CN201374192Y true CN201374192Y (en) | 2009-12-30 |
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| CN200820215150U Expired - Lifetime CN201374192Y (en) | 2008-12-12 | 2008-12-12 | Flash memory device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111554225A (en) * | 2020-05-20 | 2020-08-18 | Tcl华星光电技术有限公司 | Display device, and speckle eliminating system and speckle eliminating method thereof |
| CN113703683A (en) * | 2021-08-28 | 2021-11-26 | 江苏华存电子科技有限公司 | Single device for optimizing redundant storage system |
-
2008
- 2008-12-12 CN CN200820215150U patent/CN201374192Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111554225A (en) * | 2020-05-20 | 2020-08-18 | Tcl华星光电技术有限公司 | Display device, and speckle eliminating system and speckle eliminating method thereof |
| CN111554225B (en) * | 2020-05-20 | 2023-02-28 | Tcl华星光电技术有限公司 | Display device, and speckle eliminating system and speckle eliminating method thereof |
| CN113703683A (en) * | 2021-08-28 | 2021-11-26 | 江苏华存电子科技有限公司 | Single device for optimizing redundant storage system |
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| GR01 | Patent grant | ||
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| TR01 | Transfer of patent right |
Effective date of registration: 20170303 Address after: Pudong New Area Zhangjiang hi tech road 201203 Shanghai City No. 1158 Zhang No. 2 Building 7 floor Patentee after: Brite Semiconductor (Shanghai) Corporation Address before: Suzhou City, Jiangsu province 215021 international science and Technology Park No. 1355 Jinji Lake Avenue Suzhou industrial park two D102-2 Patentee before: Suzhou Liangzhi Technology Co., Ltd. |
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| CX01 | Expiry of patent term |
Granted publication date: 20091230 |
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| CX01 | Expiry of patent term |