CN201319644Y - Screen electrifying sequential circuit for LCD color television sets - Google Patents
Screen electrifying sequential circuit for LCD color television sets Download PDFInfo
- Publication number
- CN201319644Y CN201319644Y CNU200820214371XU CN200820214371U CN201319644Y CN 201319644 Y CN201319644 Y CN 201319644Y CN U200820214371X U CNU200820214371X U CN U200820214371XU CN 200820214371 U CN200820214371 U CN 200820214371U CN 201319644 Y CN201319644 Y CN 201319644Y
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- China
- Prior art keywords
- television set
- triode
- capacitor
- timing sequence
- resistance
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Abstract
The utility model discloses a screen electrifying sequential circuit for LCD color television sets, which comprises a television set CPU, a dynatron Q1, an MOS tube U3 and a capacitor C2, wherein the dynatron Q1 is connected with the television set CPU for receiving control signals transmitted from the television set CPU; the MOS tube U3 is connected with the dynatron Q1 through a resistor R3; and the capacitor C2 is connected with the grid electrode G of the MOS tube U3. Control signals (ON_PANEL) transmitted from the television set CPU control the base electrode of the NPN dynatron Q1; the collector electrode of the dynatron Q1 is used for controlling the grid electrode G of the MOS tube U3; and the valves of the resistor R3 and the capacitor C2 which are connected with the grid electrode G of the MOS tube U3 are regulated to control the delay time of the MOS tube U3, and thereby, the requirement for controlling the electrifying sequent of Vcc-Panel is satisfied. When the screen electrifying sequential circuit is used for supply power to LCD screen electrifying sequent, the MOS tube U3 can safely and reliably work; and thereby, the utility model further ensures the safety of the whole system and the reliability of the products.
Description
[technical field]
The utility model relates to technical field of television sets, particularly a kind of screen electrifying timing sequence circuit of LCD color television set.
[background technology]
Along with the development of television technologies, television set begins to change to panel TV from the CRT TV, and the LCD flat panel television set is the occuping market leading position.At present, in the designing technique of LCD color television set, require relatively stricter for television set screen electrifying timing sequence, particularly the electrifying timing sequence for the TCON plate all has clear and definite sequential requirement, the electrifying timing sequence of each LCD screen manufacturer also has nothing in common with each other, for example the screen TCON plate electrifying timing sequence requirement of LG company production is 0.5us-20ms, and the screen TCON plate electrifying timing sequence that Qi Mei company produces requirement is 0.5us-10ms.The correctness of electrifying timing sequence is to all there being certain influence in useful life of the safety of whole system for TV set and television product.The requirement that does not meet electrifying timing sequence that the electrifying timing sequence that present each system for TV set is adopted has has certain influence to the safety of system for TV set, though and the electrifying timing sequence that has meets the requirements, but the operating voltage of key point is incorrect, thereby to also exerting an influence the useful life of product.So be necessary to research and develop a kind of for system for TV set fail safe and useful life of television product equal screen electrifying timing sequence circuit of beneficial LCD color television set.
[utility model content]
For addressing the above problem, main purpose of the present utility model is to provide a kind of screen electrifying timing sequence circuit of LCD color television set.
For achieving the above object, technical scheme of the present invention is:
A kind of screen electrifying timing sequence circuit of LCD color television set includes television set CPU, connects the capacitor C 2 of metal-oxide-semiconductor U3 that television set CPU is connected with triode Q1 with the triode Q1 of the control signal that receives CPU and send, by a resistance R 3 and the grid G that is connected in metal-oxide-semiconductor U3.
Further, be connected with resistance R 17 between the base stage of triode Q1 and the television set CPU, the 5Vstb power supply provides quiescent operation voltage for the base stage of triode Q1 by resistance R 15, resistance R 17.
Further, the grounded emitter of triode Q1, and base stage also is connected with the capacitor C 15 of a ground connection.
Further, the collector electrode of triode Q1 also is connected with 12V voltage by resistance R 2, inductance L 2; Be connected with the capacitor C 1 of a ground connection between inductance L 2 and the resistance R 2.
Compared to prior art, the utility model is from the base stage of control signal (ON_PANEL) the control NPN triode of CPU, the collector electrode of triode controls the grid G of metal-oxide-semiconductor U3, decide the conducting of metal-oxide-semiconductor U3 and end by the height of the voltage of metal-oxide-semiconductor U3 grid G, the resistance R 3 that adjustment metal-oxide-semiconductor U3 grid G is connected and the value size of capacitor C 2 are controlled the length of metal-oxide-semiconductor U3 delay time, thereby reach the requirement of the electrifying timing sequence of control Vcc-Panel.Adopt this circuit to the power supply of LCD screen electrifying timing sequence, can make metal-oxide-semiconductor U3 safety, work reliably, thereby further guarantee the safety and the reliability of products of whole system.
[description of drawings]
Fig. 1 is the circuit theory diagrams of the screen electrifying timing sequence circuit of the utility model LCD color television set.
[embodiment]
See also shown in Figure 1, the screen electrifying timing sequence circuit of the utility model LCD color television set includes television set CPU, connects television set CPU with metal-oxide-semiconductor U3 that receives triode Q1 from the control signal (ON-PANEL) of CPU, is connected with triode Q1 by a resistance R 3 and the capacitor C 2 that is connected in metal-oxide-semiconductor U3 grid G.Wherein, be connected with resistance R 17 between the base stage of triode Q1 and the television set CPU, the 5Vstb power supply provides quiescent operation voltage for the base stage of triode Q1 by resistance R 15, resistance R 17.The base stage of triode Q1 also is connected with the capacitor C 15 of a ground connection.The grounded emitter of triode Q1.12V voltage is connected to the collector electrode of triode Q1 by inductance L 2 and resistance R 2.Be connected with the capacitor C 1 of a ground connection between inductance L 2 and the resistance R 2.12V voltage also is connected to the source S of capacitor C 2 and metal-oxide-semiconductor U3.The drain D of metal-oxide-semiconductor U3 connects TV set power Vcc-panel, and by a capacitor C A31 ground connection.Described triode Q1 is a NPN type triode, and described metal-oxide-semiconductor U3 is P channel MOS tube U3.
The base stage of control signal (ON_PANEL) the control triode Q1 that sends from television set CPU, during operate as normal, the control signal of CPU (ON_PANEL) is a high level, is low level during standby.Resistance R 15 and resistance R 17 provide quiescent operation voltage for triode Q1 by 5Vstb, 17 metering functions of resistance R, and capacitor C 15 is used for the filtering noise jamming.Inductance L 2 is serially connected between 12V power supply and the metal-oxide-semiconductor U3 to the power supply of LCD screen, is used for the high frequency noise jamming of filtering 12V power supply.And the effect of capacitor C 1 is to leach the high frequency noise jamming.Resistance R 2 is quiescent operation voltage to be provided for the collector electrode of triode Q1 by 12V.In the moment of start, because the control signal of sending from CPU (ON_PANEL) is a high level, so the base stage of triode Q1 is a high level, triode Q1 saturation conduction, the collector potential of triode Q1 is a low level after the conducting, because the effect of capacitor C 2,12V voltage charges to capacitor C 2 by resistance R 3, the voltage at capacitor C 2 two ends can not suddenly change, so the grid G of metal-oxide-semiconductor U3 remains high level in the moment of triode Q1 conducting, metal-oxide-semiconductor U3 still ended in the moment of triode Q1 conducting, only along with the prolongation in charging interval, when the current potential of the grid G of metal-oxide-semiconductor U3 drops to (Vg-Vs) less than Vgs, just conducting of metal-oxide-semiconductor U3.By adjusting the resistance size of resistance R 3, thus charge constant that can control capacitance C2, and then the conducting of control metal-oxide-semiconductor U3, further reach the requirement of the electrifying timing sequence of control Vcc-Panel.
The utility model is from the base stage of control signal (ON_PANEL) the control NPN triode of CPU, the collector electrode of triode controls the grid G of metal-oxide-semiconductor U3, decide the conducting of metal-oxide-semiconductor U3 and end by the height of the voltage of metal-oxide-semiconductor U3 grid G, the size of the resistance R 3 that adjustment metal-oxide-semiconductor U3 grid G is connected and the value of capacitor C 2 is controlled the length of metal-oxide-semiconductor U3 delay time, thereby reaches the requirement of the electrifying timing sequence of control Vcc-Panel.Adopt this circuit to the power supply of LCD screen electrifying timing sequence, can make the safe and reliable work of metal-oxide-semiconductor U3, thereby further guarantee the safety and the reliability of products of whole system.
Most preferred embodiment described above only is that the utility model is set forth and illustrated, but is not limited to disclosed any concrete form, and it is possible carrying out many modifications and variations.
Claims (7)
1. the screen electrifying timing sequence circuit of a LCD color television set, include television set CPU, it is characterized in that: also include and connect metal-oxide-semiconductor U3 that television set CPU is connected with triode Q1 with the triode Q1 of the control signal that receives CPU and send, by a resistance R 3 and the capacitor C 2 that is connected in metal-oxide-semiconductor U3 grid G.
2. the screen electrifying timing sequence circuit of LCD color television set as claimed in claim 1, it is characterized in that: be connected with resistance R 17 between the base stage of triode Q1 and the television set CPU, the 5Vstb power supply provides quiescent operation voltage for the base stage of triode Q1 by resistance R 15, resistance R 17.
3. the screen electrifying timing sequence circuit of LCD color television set as claimed in claim 2 is characterized in that: the grounded emitter of triode Q1, base stage are connected with the capacitor C 15 of a ground connection.
4. the screen electrifying timing sequence circuit of LCD color television set as claimed in claim 3 is characterized in that: the collector electrode of triode Q1 also is connected with 12V voltage by resistance R 2, inductance L 2; Be connected with the capacitor C 1 of a ground connection between inductance L 2 and the resistance R 2.
5. the screen electrifying timing sequence circuit of LCD color television set as claimed in claim 4, it is characterized in that: 12V voltage also is connected to the source S of capacitor C 2 and metal-oxide-semiconductor U3.
6. the screen electrifying timing sequence circuit of LCD color television set as claimed in claim 5 is characterized in that: the drain D of metal-oxide-semiconductor U3 connects TV set power Vcc-panel, and by a capacitor C A31 ground connection.
7. the screen electrifying timing sequence circuit of LCD color television set as claimed in claim 6 is characterized in that: described triode Q1 is a NPN type triode, and described metal-oxide-semiconductor U3 is the P channel MOS tube.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNU200820214371XU CN201319644Y (en) | 2008-12-12 | 2008-12-12 | Screen electrifying sequential circuit for LCD color television sets |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNU200820214371XU CN201319644Y (en) | 2008-12-12 | 2008-12-12 | Screen electrifying sequential circuit for LCD color television sets |
Publications (1)
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CN201319644Y true CN201319644Y (en) | 2009-09-30 |
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CNU200820214371XU Expired - Fee Related CN201319644Y (en) | 2008-12-12 | 2008-12-12 | Screen electrifying sequential circuit for LCD color television sets |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105553261A (en) * | 2016-02-19 | 2016-05-04 | 京东方科技集团股份有限公司 | DC-DC conversion control module, DC-DC converter and display device |
CN105959607A (en) * | 2015-12-30 | 2016-09-21 | 天津天地伟业数码科技有限公司 | Power supply low-power circuit of hard disk video device and design method thereof |
CN110728961A (en) * | 2019-10-22 | 2020-01-24 | 南京熊猫电子制造有限公司 | Delay control circuit and control method on liquid crystal display |
-
2008
- 2008-12-12 CN CNU200820214371XU patent/CN201319644Y/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105959607A (en) * | 2015-12-30 | 2016-09-21 | 天津天地伟业数码科技有限公司 | Power supply low-power circuit of hard disk video device and design method thereof |
CN105553261A (en) * | 2016-02-19 | 2016-05-04 | 京东方科技集团股份有限公司 | DC-DC conversion control module, DC-DC converter and display device |
US10163399B2 (en) | 2016-02-19 | 2018-12-25 | Boe Technology Group Co., Ltd. | DC-DC conversion control module, DC-DC converter, and display device |
CN110728961A (en) * | 2019-10-22 | 2020-01-24 | 南京熊猫电子制造有限公司 | Delay control circuit and control method on liquid crystal display |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090930 Termination date: 20151212 |
|
EXPY | Termination of patent right or utility model |