CN201311708Y - Remote receiving control circuit and control chip using same - Google Patents
Remote receiving control circuit and control chip using same Download PDFInfo
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- CN201311708Y CN201311708Y CNU2008202348527U CN200820234852U CN201311708Y CN 201311708 Y CN201311708 Y CN 201311708Y CN U2008202348527 U CNU2008202348527 U CN U2008202348527U CN 200820234852 U CN200820234852 U CN 200820234852U CN 201311708 Y CN201311708 Y CN 201311708Y
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Abstract
The utility model discloses a remote receiving control circuit and a control chip using same. The control circuit comprises a vibrator, a timer, a small signal processing circuit, a decoding circuit and a logic output circuit. The vibrator outputs pulse signals to the timer, and the pulse signals are output to the decoding circuit after being frequency-divided to provide reference clock pulse to the decoding circuit. Remote signals are output to the decoding circuit after being treated by the small signal processing circuit, and to the logic output circuit after being decoded by the decoding circuit. A motor is driven by a periphery driving circuit. The small signal processing circuit comprises a series two-stage signal amplifying circuit, wherein an output terminal of a second stage signal amplifying circuit is connected with a hysteresis comparator, and an output terminal of the hysteresis comparator is the output terminal of the small signal processing circuit. The remote receiving control circuit and the control chip using same reduce packing cost of chip manufacturers and simplify user's wiring design.
Description
Technical field
The control chip that the utility model discloses a kind of circuit and adopts this circuit to make, particularly a kind of remote-control reception control circuit and the control chip that adopts this circuit to make thereof.
Background technology
Along with the reach of science, telecontrol engineering is used more and more widely in daily life, and is too numerous to enumerate, and the form of existing remote-control reception control circuit also is varied, and application is very extensive.Wherein bigger purposes also is that the common purposes of people is applied on the remote-controlled toy vehicle exactly, as the reception of remote signal.At present, the remote-control receiving circuit that is adopted in toy car is used mainly contains two kinds of circuit, and a kind of is to adopt MCU to realize its flexible function, good reliability, but cost height; Another kind is that special-purpose integrated circuit is realized, it is multiple functional, good reliability, many but its shortcoming is exactly a peripheral cell, pin is many, packaging cost is higher, and mostly the small-signal treatment circuit of the integrated circuit of special use of the prior art is to adopt two-stage to amplify small-signal is amplified, and adopt bandpass filter in the small-signal with clutter carry out filtering, its pin is many, and wiring complexity and effect are undesirable.
Summary of the invention
Many at above-mentioned remote-control reception control circuit of the prior art and the chip pin of mentioning thereof, the packaging cost height, shortcomings such as wiring complexity and filter effect are undesirable, the utility model provides a kind of new remote-control reception control circuit and the control chip that adopts this circuit to make thereof, its control circuit comprises oscillator, timer, the small-signal treatment circuit, decoding circuit, the logic output circuit, the oscillator output pulse signal is given timer, pulse signal is exported to decoding circuit behind the timer frequency division, for decoding circuit provides the reference clock pulse, input to decoding circuit after the remote signal process small-signal processing circuit processes, after the decoding circuit decoding, export to the logic output circuit, by the peripheral drive circuit drive motor, wherein, the small-signal treatment circuit comprises the two-stage signal amplifying circuit that is connected in series, small-signal to input amplifies, the output terminal of second level amplifying circuit is connected with hysteresis comparator, the clutter that has in the small-signal is carried out filtering, the output terminal of hysteresis comparator is the output terminal of small-signal treatment circuit, the control chip that adopts this circuit to make comprises positive supply pin and the negative supply pin to the control circuit power supply, comprise the VI pin that is connected with first order input amplifier, the VO pin that is connected with first order amplification circuit output end, the BW pin and the FW pin that comprise two logic output control positive and negative rotation of motor, also include and connect OSCI pin and the OSCO pin that oscillation resistance is used, OSCI pin and OSCO pin are connected to resistance R 1 two ends respectively, or resistance R 1 is integrated in inside, thereby save OSCI pin and OSCO pin, set up the RT pin and the LF pin of two logic output control positive and negative rotation of motor.
The technical scheme that its technical matters that solves the utility model adopts is: a kind of remote-control reception control circuit, control circuit comprises oscillator, timer, the small-signal treatment circuit, decoding circuit, the logic output circuit, the oscillator output pulse signal is given timer, pulse signal is exported to decoding circuit behind the timer frequency division, for decoding circuit provides the reference clock pulse, input to decoding circuit after the remote signal process small-signal processing circuit processes, after the decoding circuit decoding, export to the logic output circuit, by the peripheral drive circuit drive motor, the small-signal treatment circuit comprises the two-stage signal amplifying circuit that is connected in series, the output terminal of second level amplifying circuit is connected with hysteresis comparator, and the output terminal of hysteresis comparator is the output terminal of small-signal treatment circuit.
A kind of control chip that adopts foregoing circuit to make, comprise chip body and be arranged on the interior control circuit of main body, described control circuit comprises oscillator, timer, the small-signal treatment circuit, decoding circuit, the logic output circuit, the oscillator output pulse signal is given timer, timer is 15 frequency dividers that interconnective T trigger constitutes, pulse signal is exported to decoding circuit behind the timer frequency division, for decoding circuit provides the reference clock pulse, input to decoding circuit after the remote signal process small-signal processing circuit processes, after the decoding circuit decoding, export to the logic output circuit, by the peripheral drive circuit drive motor, control chip comprises positive supply pin and the negative supply pin to the control circuit power supply, comprise the VI pin that is connected with first order input amplifier, the VO pin that is connected with first order amplification circuit output end, comprise two BW pin and FW pins that drive output control positive and negative rotation of motor, also include OSCI pin and OSCO pin that the connection oscillation resistance is used, OSCI pin and OSCO pin are connected to resistance R 1 two ends respectively.
A kind of control chip that adopts foregoing circuit to make, comprise chip body and be arranged on the interior control circuit of main body, described control circuit comprises oscillator, timer, the small-signal treatment circuit, decoding circuit, the logic output circuit, the oscillator output pulse signal is given timer, timer is 14 frequency dividers that interconnective T trigger constitutes, pulse signal is exported to decoding circuit behind the timer frequency division, for decoding circuit provides the reference clock pulse, input to decoding circuit after the remote signal process small-signal processing circuit processes, after the decoding circuit decoding, export to the logic output circuit, by the peripheral drive circuit drive motor, control chip comprises positive supply pin and the negative supply pin to the control circuit power supply, comprise the VI pin that is connected with first order input amplifier, the VO pin that is connected with first order amplification circuit output end, the pin that comprises two groups of logic output control positive and negative rotation of motor, first group of pin comprises BW pin and FW pin, and second group of pin comprises RT pin and LF pin.
The technical scheme that its technical matters that solves the utility model adopts further comprises:
Described two-stage signal amplifying circuit is the phase inverter amplifying circuit.
Be parallel with feedback resistance R2 between phase inverter input end and the output terminal in the described first order signal amplification circuit, be parallel with capacitor C 2 with feedback resistance R2.
Be parallel with feedback resistance R3 between phase inverter input end and the output terminal in the signal amplification circuit of the described second level.
Described two-stage signal amplifying circuit is operational amplifier, the input end in the same way of two-stage amplifier is connected and is connected with reference voltage, first order amplifier reverse input end is the input end of small signal amplification circuit, the output terminal of first order amplifier is connected by internal resistance R5 with the reverse input end of second level amplifier, and the output terminal of second level amplifier is connected with the input end of hysteresis comparator.
Be parallel with feedback resistance R3 between inverting input and the amplifier output terminal in the first order signal amplification circuit in the described two-stage signal amplifying circuit, be parallel with capacitor C 2 with feedback resistance R3.
Described oscillator adopts five phase inverters that are connected in series successively, is parallel with between the output terminal of the input end of first phase inverter and the 3rd phase inverter between the output terminal of the input end of resistance R 1, the first phase inverter and the 4th phase inverter and is parallel with capacitor C 1.
Described timer is the frequency divider that interconnective T trigger constitutes more than 14.
The beneficial effects of the utility model are: the utility model adopts two-stage amplifier that small-signal is amplified, and adopt hysteresis comparator as the clutter filtering, saved the complexity of circuit greatly, the pin of integrated chip is reduced to 8, reduce the packaging cost of chip manufacturer on the one hand, also simplified user's wiring design on the other hand.
Below in conjunction with the drawings and specific embodiments the utility model is described further.
Description of drawings
Fig. 1 is the internal control integrated circuit block scheme of the utility model embodiment one.
Fig. 2 is the internal control integrated circuit part schematic diagram of the utility model embodiment one.
Fig. 3 is the internal control integrated circuit block scheme of the utility model embodiment two.
Fig. 4 is the internal control integrated circuit part schematic diagram of the utility model embodiment two.
Fig. 5 is that the utility model embodiment one decoding circuit is formed block scheme.
Fig. 6 is the utility model embodiment one function identification synoptic diagram.
Fig. 7 is that the utility model embodiment two decoding circuits are formed block scheme.
Fig. 8 is the utility model embodiment two form type code synoptic diagram.
Fig. 9 is the utility model embodiment two functions identification synoptic diagram.
Figure 10 is the small-signal treatment circuit circuit theory diagrams of the utility model distortion.
Embodiment
Present embodiment is the utility model preferred implementation, and other all its principles are identical with present embodiment or approximate with basic structure, all within the utility model protection domain.
Please referring to accompanying drawing 1 and accompanying drawing 3; what the utility model open request was protected is a kind of remote-control reception control circuit; its circuit comprises oscillator, timer, small-signal treatment circuit, decoding circuit, logic output circuit; the oscillator output pulse signal is given timer; pulse signal is exported to decoding circuit behind the timer frequency division; for decoding circuit provides the reference clock pulse; input to decoding circuit after the remote signal process small-signal processing circuit processes; after the decoding circuit decoding, export to the logic output circuit, by the peripheral drive circuit drive motor.
Please referring to accompanying drawing 2 and accompanying drawing 4, oscillatory circuit among embodiment one and the embodiment two, its principle is that the annular vibration adds the RC frequency selection circuit, internal circuit is integrated five phase inverters and a capacitor C 1, five phase inverters are connected in series successively, and capacitor C 1 is connected in parallel between the output terminal of the input end of first phase inverter and the 4th phase inverter.Timer among embodiment one and the embodiment two, its principle is the frequency divider that utilizes 14 T triggers (being the T trigger that adopts JK flip-flop that J pin and K pin are interconnected to constitute among embodiment one and the embodiment two) to constitute, wherein the Q port of previous stage is connected with the CLK port of back one-level, as VJK and VSR when being high, the every one-period of crossing of the CLK of each trigger, the Q port of output is turned into the state opposite with initial state, so just the signal (input signal is the oscillator signal of chip) of oscillatory circuit input has been carried out multiple frequency division, for other part work of circuit provide reference frequency, F16 wherein, F32, F64, F128, F256 corresponds respectively to 16 frequency divisions of clock, 32 frequency divisions, 64 frequency divisions, 128 frequency divisions, 256 frequency divisions.Small-signal treatment circuit among embodiment one and the embodiment two, be to adopt the two-stage amplifying circuit that small-signal is amplified, by hysteresis comparator the small-signal after amplifying is carried out the clutter filtering then, principle among embodiment one and the embodiment two is to utilize two phase inverters to do small-signal to amplify, be parallel with resistance R 3 (the inner integrated component of integrated chip) between second level phase inverter input end and the output terminal, the output terminal of first order phase inverter is connected with the input end of second level phase inverter, please specifically referring to accompanying drawing, the input end VI of the U13-A of first order phase inverter forms negative feedback by outer meeting resistance R2, make the dc point of VI be stabilized in 1/2nd supply voltages, and the ac small signal of input end VI input can be amplified, 2 pairs of high-frequency signals of capacitor C have the good restraining effect, also play the self-oscillatory effect of eliminating circuit on the other hand, second level phase inverter U14-A is integrated feedback resistance R3 in inside, play the further amplification of signal, the output terminal of second level phase inverter U14-A is connected with hysteresis comparator U12-A, and hysteresis comparator U12-A central point is approximately 1/2nd supply voltages, about 500 millivolts of hysteresis voltages, has very strong antijamming capability, can guarantee useful signal is amplified, and filtering interference signals, and send next part to carry out signal Processing.Logic output circuit among embodiment one and the embodiment two, A are and the tie point of in-line coding circuit that Y is the drive output mouth.Because the cmos circuit area is little, power consumption is few, inner pipe can not be done very big, for can the driven peripheral circuit, the driving output of IC generally will strengthen, adopt field effect transistor Q1 and field effect transistor Q2 to drive among embodiment one and the embodiment two, driving force is a milliampere level, could drive external circuit (general peripheral circuit is the base stage that connects triode by current-limiting resistance) like this.Decoding circuit among embodiment one and the embodiment two adopts the decoding circuit of remote-controlled chip of the prior art.
The utility model mainly is that the small-signal treatment circuit is improved, and the chip of the utility model circuit application according to arrange different with function of its inner structure and pin, specifically are divided into following two kinds of specific embodiments and describe.
Embodiment one: please referring to accompanying drawing 1 and accompanying drawing 3, be provided with OSCI pin and OSCO pin in the present embodiment, be used to connect the usefulness of oscillation resistance R1, its oscillation frequency can be adjusted by the resistance R 1 of outside, when resistance R 1=100K ohm, the about 76KHz of the frequency of CLK, OSCI pin and OSCO pin are respectively the input end of first phase inverter in the oscillatory circuit and the output terminal of the 3rd phase inverter, the input end of first order phase inverter U13-A in the small-signal treatment circuit is the VI pin, the output terminal of first order phase inverter U13-A is the VO pin, be used to connect external negative feedback resistor R2 and capacitor C 2 between VI pin and the VO pin, drive output circuit and be provided with two output pins, be respectively BW pin and FW pin, be used to control the rotating of motor, the positive-negative power pin is given the circuit supply in the chip.In the present embodiment, in use, as long as between OSCI pin and OSCO pin, be connected with resistance R 1, between VI pin and VO pin, connect negative feedback resistor R2 and capacitor C 2, and the BW pin is connected with two electrodes of external control circuit control motor respectively with the FW pin gets final product.Please referring to accompanying drawing 5 and accompanying drawing 6, decoding circuit is divided into the validity of frequency identification and signal and judges, frequency identification is (to come self-timer by the sampled signal of IC itself, frequency is higher than the signal that is sampled of input) come the signal of input is sampled, utilize counter to calculate the cycle of each input signal, (allow deviation when input signal at 1KHz or 250Hz, certain serious forgiveness is just arranged) time, the validity circuit of meeting enabling signal is further judged, surpass 32 when the signal continuous effective cycle of 1KHz or 250Hz, signal validity judges that will export corresponding signal controls back one-level output.When input signal is to meet the demands in 1KHz and continuous effective cycle, the FW of chip is (effectively high) effectively.
Embodiment two: please referring to accompanying drawing 2 and accompanying drawing 4, in the present embodiment oscillatory circuit partial interior integrated the vibration needed phase inverter, electric capacity and resistance, so its oscillation frequency fix, when resistance R 1=220K ohm, during capacitor C 1=18P, the about 128KHz of the frequency of CLK.The input end of first order phase inverter U13-A in the small-signal treatment circuit is the VI pin, the output terminal of first order phase inverter U13-A is the VO pin, be used to connect external negative feedback resistor R2 and capacitor C 2 between VI pin and the VO pin, the logic output circuit is provided with two groups of output pins, every group of two output pins are respectively first group of BW pin and FW pin, second group of RT pin and LF pin, be respectively applied for the rotating of two motors of control, the positive-negative power pin is given the circuit supply in the chip.In the present embodiment, in use, as long as between VI pin and VO pin, connect negative feedback resistor R2 and capacitor C 2, and BW pin and FW pin be connected with two electrodes of external control circuit control motor respectively, RT pin and LF pin are connected with two electrodes that external control circuit is controlled another motor respectively get final product.Please referring to accompanying drawing 7, accompanying drawing 8 and accompanying drawing 9, decoding circuit can be divided into preamble code identification, three parts such as function code counting and function identification, its sampled signal by IC itself (is come self-timer, frequency is higher than the signal that is sampled of input) come the signal of input is sampled, utilize counter to calculate the cycle of each input signal, when the preamble code identification circuit recognizes input signal is preamble code, will start the function code counting circuit counts function code, when transferring preamble code to, finishes signal counting at last, the function identification circuit that send of counting gained is discerned, one-level output after the corresponding signal controlling of output at last, as: when the N=10 time with regard to corresponding FW output effectively (effectively high).
The foregoing description all is as small signal amplifier with phase inverter, the utility model can also adopt operational amplifier as small signal amplifier, please referring to accompanying drawing 10, / 2nd supply voltages input to the input end in the same way of two-stage amplifier respectively, first order amplifier reverse input end is connected with the VI pin, the output terminal of first order amplifier is connected through resistance R 5 with the reverse input end of second level amplifier, and the output terminal of second level amplifier is connected with the input end of hysteresis comparator.
The utility model improves the small-signal processing section, makes chip pin quantity significantly reduce, and has reduced the packaging cost of chip manufacturer on the one hand, has also simplified user's wiring design on the other hand.
Claims (10)
1, a kind of remote-control reception control circuit, control circuit comprises oscillator, timer, the small-signal treatment circuit, decoding circuit, the logic output circuit, the oscillator output pulse signal is given timer, impulse oscillation signal is exported to decoding circuit behind the timer frequency division, for decoding circuit provides the reference clock pulse, input to decoding circuit after the remote signal process small-signal processing circuit processes, after the decoding circuit decoding, export to the logic output circuit, driving circuit drive motor by the periphery, it is characterized in that: described small-signal treatment circuit comprises the two-stage signal amplifying circuit that is connected in series, the output terminal of second level amplifying circuit is connected with hysteresis comparator, and the output terminal of hysteresis comparator is the output terminal of small-signal treatment circuit.
2, remote-control reception control circuit according to claim 1 is characterized in that: described two-stage signal amplifying circuit is the phase inverter amplifying circuit.
3, remote-control reception control circuit according to claim 2 is characterized in that: be parallel with feedback resistance R2 between phase inverter input end and the output terminal in the described first order signal amplification circuit, be parallel with capacitor C 2 with feedback resistance R2.
4, remote-control reception control circuit according to claim 2 is characterized in that: be parallel with feedback resistance R3 between phase inverter input end and the output terminal in the signal amplification circuit of the described second level.
5, remote-control reception control circuit according to claim 1, it is characterized in that: described two-stage signal amplifying circuit is operational amplifier, the input end in the same way of two-stage amplifier is connected and is connected with reference voltage, first order amplifier reverse input end is the input end of small signal amplification circuit, the output terminal of first order amplifier is connected through internal resistance R5 with the reverse input end of second level amplifier, and the output terminal of second level amplifier is connected with the input end of hysteresis comparator.
6, remote-control reception control circuit according to claim 5, it is characterized in that: be parallel with feedback resistance R3 between inverting input and the amplifier output terminal in the first order signal amplification circuit in the described two-stage signal amplifying circuit, be parallel with capacitor C 2 with feedback resistance R3.
7, according to any described remote-control reception control circuit in the claim 1 to 6, it is characterized in that: described oscillator adopts five phase inverters that are connected in series successively, be parallel with between the output terminal of the input end of first phase inverter and the 3rd phase inverter between the output terminal of the input end of resistance R 1, the first phase inverter and the 4th phase inverter and be parallel with capacitor C 1.
8, according to any described remote-control reception control circuit in the claim 1 to 6, it is characterized in that: described timer is the frequency divider that interconnective T trigger constitutes more than 14.
9, a kind of control chip that adopts control circuit as claimed in claim 1 to make, comprise chip body and be arranged on the interior control circuit of main body, described control circuit comprises oscillator, timer, the small-signal treatment circuit, decoding circuit, the logic output circuit, the oscillator output pulse signal is given timer, timer is 15 frequency dividers that interconnective T trigger constitutes, pulse signal is exported to decoding circuit behind the timer frequency division, for decoding circuit provides the reference clock pulse, input to decoding circuit after the remote signal process small-signal processing circuit processes, after the decoding circuit decoding, export to the logic output circuit, drive drive motor by peripheral drive circuit, it is characterized in that: described control chip comprises positive supply pin and the negative supply pin to the control circuit power supply, comprise the VI pin that is connected with first order input amplifier, the VO pin that is connected with first order amplification circuit output end, the BW pin and the FW pin that comprise two logic output control positive and negative rotation of motor, also include OSCI pin and OSCO pin that the connection oscillation resistance is used, OSCI pin and OSCO pin are connected to resistance R 1 two ends respectively.
10, a kind of control chip that adopts control circuit as claimed in claim 1 to make, comprise chip body and be arranged on the interior control circuit of main body, described control circuit comprises oscillator, timer, the small-signal treatment circuit, decoding circuit, the logic output circuit, the oscillator output pulse signal is given timer, timer is 14 frequency dividers that interconnective T trigger constitutes, pulse signal is exported to decoding circuit behind the timer frequency division, for decoding circuit provides the reference clock pulse, input to decoding circuit after the remote signal process small-signal processing circuit processes, after the decoding circuit decoding, export to the logic output circuit, by the peripheral drive circuit drive motor, it is characterized in that: described control chip comprises positive supply pin and the negative supply pin to the control circuit power supply, comprise the VI pin that is connected with first order input amplifier, the VO pin that is connected with first order amplification circuit output end, the pin that comprises two groups of logic output control positive and negative rotation of motor, first group of pin comprises BW pin and FW pin, and second group of pin comprises RT pin and LF pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008202348527U CN201311708Y (en) | 2008-12-10 | 2008-12-10 | Remote receiving control circuit and control chip using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008202348527U CN201311708Y (en) | 2008-12-10 | 2008-12-10 | Remote receiving control circuit and control chip using same |
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| Publication Number | Publication Date |
|---|---|
| CN201311708Y true CN201311708Y (en) | 2009-09-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2008202348527U Expired - Fee Related CN201311708Y (en) | 2008-12-10 | 2008-12-10 | Remote receiving control circuit and control chip using same |
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| CN (1) | CN201311708Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106341146A (en) * | 2015-07-08 | 2017-01-18 | 电力集成瑞士有限公司 | Data communication receiver and power converter |
-
2008
- 2008-12-10 CN CNU2008202348527U patent/CN201311708Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106341146A (en) * | 2015-07-08 | 2017-01-18 | 电力集成瑞士有限公司 | Data communication receiver and power converter |
| CN106341146B (en) * | 2015-07-08 | 2020-07-17 | 电力集成瑞士有限公司 | Data communication receiver and power converter |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090916 Termination date: 20161210 |
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| CF01 | Termination of patent right due to non-payment of annual fee |