CN201303304Y - Multi-channel high-speed servomotor control device based on FPGA - Google Patents
Multi-channel high-speed servomotor control device based on FPGA Download PDFInfo
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- CN201303304Y CN201303304Y CNU2008202225599U CN200820222559U CN201303304Y CN 201303304 Y CN201303304 Y CN 201303304Y CN U2008202225599 U CNU2008202225599 U CN U2008202225599U CN 200820222559 U CN200820222559 U CN 200820222559U CN 201303304 Y CN201303304 Y CN 201303304Y
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Abstract
The utility model discloses a multi-channel high-speed servomotor control device based on FPGA, which comprises a data/control bus, and the data/control bus is respectively connected with an FPGA control module, at least two drive modules which are arranged in parallel, at least two photoelectric code discs which are independently arranged and a plurality of ADC modules which are independently arranged, wherein the FPGA control module comprises a core control unit, and the core control unit is respectively connected with a digital display unit, an interface unit, a storage unit and at least two motor control units which are arranged in parallel, and the drive modules, the photoelectric code discs, the ADC modules and the motor control units are respectively corresponding to a high-speed servomotor. The control device can simultaneously control a plurality of high-speed servomotors according to the working characteristics of the high-speed servomotors, which has higher reliability, excellent control real-time performance and flexible operation, and can satisfy the relevant technique requirements of complex environment spots such as machine tools, weave, cannon and the like.
Description
Technical field
The utility model belongs to electromechanical equipment manufacturing technology field, relates to a kind of control device of motor, is specifically related to a kind of multi-channel high-speed servomotor control device based on FPGA.
Background technology
Along with the progress that power electronics and microelectric technique are maked rapid progress, have simple in structure, volume is little, in light weight, efficient is high, the high-speed servo motor of power factor advantages of higher, its application is constantly expanded.Because the rotating speed of high-speed servo motor is very high, need in the course of the work constantly its rotating speed to be adjusted, so the control device that requires high-speed servo motor to be controlled adjustment has high performance arithmetic speed and good control real-time.The present control device of the high-speed servo motor that uses, adopting with general processor or specific IC is that the arithmetic system of core realizes its calculation function; With the general processor is the arithmetic system of core, and the limitation of framework is carried out in existence in proper order, needs a large amount of operational orders just can finish the work, and can't realize needed ultrahigh speed calculation process ability under the particular demands; With specific IC is the arithmetic system of core, specific IC has calculation process ability at a high speed, each specific IC can only control a high-speed servo motor, limitation in the tangible flexibility is arranged on the linkage of a plurality of high-speed servo motor controls, therefore, the control device of existing high-speed servo motor based on these two kinds of control modes can not be accomplished simultaneously a plurality of high-speed servo motors to be controlled in real time, does not satisfy the correlation technique requirement at complex environment scenes such as lathe, weaving, cannon.
Summary of the invention
The purpose of this utility model provides a kind of multi-channel high-speed servomotor control device based on FPGA, this control device is according to the work characteristics of high-speed servo motor, can control a plurality of high-speed servo motors simultaneously, and reliability height, good, the flexible operation of control real-time can satisfy the correlation technique requirement at complex environment scenes such as lathe, weaving, cannon.
The technical scheme that the utility model adopted is, a kind of multi-channel high-speed servomotor control device based on FPGA, comprise data/control bus, data/control bus respectively with the FPGA control module, at least two parallel driver modules that are provided with, at least two independent photoelectric code disks that are provided with are connected with at least two independent ADC modules that are provided with, the FPGA control module comprises key control unit, key control unit respectively with digital display unit, interface unit, memory cell is connected driver module with at least two parallel motor control units that are provided with, photoelectric code disk, ADC module and motor control unit form corresponding one by one with high-speed servo motor respectively.
Feature of the present utility model also is,
A plurality of motor control units are connected with data/control bus respectively.
Interface unit is the RS232/485 standard data interface.
The CPU of key control unit adopt the StratixII2S60 chip.
Driver module comprises photoelectricity isolated location, pre-amplifier unit and the MOSFET power bridge that connects successively, and the photoelectricity isolated location is connected with data/control bus.
The utility model multi-channel high-speed servomotor control device has the following advantages:
1. can integrated to greatest extent peripheral logic, realize the singualtion design, improve the global reliability of system;
2. adopt and independently customize arithmetic logic and parallel processing mechanism, reach high performance computing requirement, the control real-time is good;
3. adopt the design of hardware sequencer and redundancy logic, improve interference free performance;
4. adopt the StratixII2S60 chip of Altera, built-in NiosII operating system by parallel processing mechanism, can realize the interchannel real-time interlock of each Electric Machine Control;
5. be applicable to various power, the highest 40,000 high-speed servo motors that change that are no more than of rotating speed;
Description of drawings
Fig. 1 is the structural representation of the utility model control device;
Fig. 2 is the workflow diagram of the utility model control device.
Among the figure, 1.FPGA control module, 2. data/control bus, 3. driver module, 4. high-speed servo motor, 5. photoelectric code disk, 6.ADC module, 7. power module, 8. computer/pda/ numeric keypad.
Wherein, the digital display unit of 1-1., 1-2. key control unit, 1-3. interface unit, 1-4. motor control unit, 1-5. memory cell, 3-1. photoelectricity isolated location, 3-2. pre-amplifier unit, 3-3.MOSFET power bridge.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is elaborated.
The structure of the utility model control device, as shown in Figure 1.This control device comprises data/control bus 2, and data/control bus 2 is respectively with FPGA control module 1, at least two parallel driver modules 3 that are provided with, be connected with ADC module 6 with the corresponding respectively photoelectric code disk 5 of the quantity of driver module 3.FPGA control module 1 comprises key control unit 1-2, key control unit 1-2 is connected with digital display unit 1-1, memory cell 1-5, interface unit 1-3 and parallel two motor control unit 1-4 that are provided with respectively at least, FPGA control module 1 is connected with data/control bus 2 by each motor control unit 1-4, and each motor control unit 1-4, photoelectric code disk 5, ADC module 6 form corresponding one by one with driver module 3.
Each driver module 3 comprises photoelectricity isolated location 3-1, pre-amplifier unit 3-2 and the MOSFET power bridge 3-3 that joins successively, each photoelectricity isolated location 3-1 is connected with data/control bus 2 respectively, and each driver module 3 connects with a corresponding high-speed servo motor 4 respectively by MOSFET power bridge 3-3.
Each high-speed servo motor 4 is connected with ADC module 6 with corresponding photoelectric code disk 5 respectively.
FPGA control module 1 also is connected with power module 7, and FPGA control module 1 is joined by interface unit 1-3 and computer/pda/ numeric keypad 8, and interface unit 1-3 adopts the RS232/485 standard data interface.
The CPU that key control unit 1-2 adopts is the StratixII2S60 chip.
The signal of 6 couples of input and output FPGA of ADC module control module 1 carries out digital-to-analogue conversion.
The rotor information of photoelectric code disk 5 location high-speed servo motors 4.
FPGA control module 1 is used to realize driving the required all functions of high-speed servo motor, as the generation of PWM ripple, position decoding, brake and overcurrent protection, driving sequencing control and the control state machine etc. of rotor, kernel control module 1-2 wherein is used to realize the real-time interlock between a plurality of high-speed servo motor 4 control units, and digital display unit 1-1 is used for showing in real time the ruuning situation of each high-speed servo motor 4; Memory cell 1-5 is used for the stored information report.
By computer/PDA/ numeric keypad 8 the Electric Machine Control parameter is imported FPGA control module 1.
The utility model control device, with fpga chip StratixII2S60 is core, the generation of motor-driven waveform, closed-loop control computing and host computer communication function are integrated in one, the driver module 3 and a plurality of independent photoelectric code disk 5 that is provided with that comprise FPGA control module 1, a plurality of mutual disjunct ADC module 6, a plurality of parallel settings, FPGA control module 1 links to each other with the ADC module 6 of a plurality of parallel settings by data/control bus 2, and each ADC module 6 connects corresponding with it a driver module 3 and a photoelectric code disk 5 respectively.
The workflow of the utility model control device, as shown in Figure 2.
MOSFET power bridge 3-3, photoelectric code disk 5 and ADC module 6 in this control device are connected with corresponding high-speed servo motor 4 respectively.Start this control device, each module of initialization, the interlock scheme input FPGA control module 1 that each high-speed servo motor that will design in advance by computer/PDA/ numeric keypad 8 is 4 deposits the interlock register management unit among the CPU of key control unit 1-2 in.Then, high-speed servo motor 4 by storage in advance among the key control unit 1-2 reading cells 1-5 starts required relevant parameter, and this relevant parameter that will read deposits the interlock register management unit among the CPU of key control unit 1-2 in, to improve arithmetic speed, at this moment, high-speed servo motor 4 soft starts, read the interlock scheme of 4 of each high-speed servo motors from interlock register management unit, utilize computer/PDA/ numeric keypad 8 to carry out real-time management by interface unit 1-3 distich dynamic register file administrative unit, if do not read the interlock scheme of current latest configuration, then be configured to last interlock scheme.If read the interlock scheme of current latest configuration, then carry out the interlock configuration of 4 of each high-speed servo motors, and obtain the positional information of each high-speed servo motor 4 by photoelectric code disk 5, simultaneously, in-position PID closed-loop control obtains the velocity information of corresponding servomotor 4, then, admission velocity PID closed-loop control, read busbar voltage, bus current, every voltage, every current information afterwards, enters into current PI D closed-loop control, realization is to the real-time control of high-speed servo motor 4, then, determine whether to stop the operation of this control device, if need not stop, then generate this report information, and this report information is stored in the interlock register management unit, return and read interlock information, proceed operation, if need stop, then this control device is out of service.
Claims (5)
1. multi-channel high-speed servomotor control device based on FPGA, it is characterized in that, this device comprises data/control bus (2), data/control bus (2) respectively with FPGA control module (1), at least two parallel driver modules (3) that are provided with, the independent photoelectric code disk (5) that is provided with is connected with at least two independent ADC modules (6) that are provided with, described FPGA control module (1) comprises key control unit (1-2), key control unit (1-2) respectively with digital display unit (1-1), interface unit (1-3), memory cell (1-5) is connected described driver module (3) with at least two parallel motor control units (1-4) that are provided with, photoelectric code disk (5), ADC module (6) and motor control unit (1-4) form corresponding one by one with high-speed servo motor (4) respectively.
2. control device according to claim 1 is characterized in that, described a plurality of motor control units (1-4) are connected with data/control bus (2) respectively.
3. control device according to claim 1 is characterized in that, described interface unit (1-3) is the RS232/485 standard data interface.
4. control device according to claim 1 is characterized in that, the CPU of described key control unit (1-2) adopts the StratixII2S60 chip.
5. control device according to claim 1, it is characterized in that, described driver module (3) comprises photoelectricity isolated location (3-1), pre-amplifier unit (3-2) and the MOSFET power bridge (3-3) that connects successively, and photoelectricity isolated location (3-1) is connected with data/control bus (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008202225599U CN201303304Y (en) | 2008-11-21 | 2008-11-21 | Multi-channel high-speed servomotor control device based on FPGA |
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| CNU2008202225599U CN201303304Y (en) | 2008-11-21 | 2008-11-21 | Multi-channel high-speed servomotor control device based on FPGA |
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| CN201303304Y true CN201303304Y (en) | 2009-09-02 |
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| CNU2008202225599U Expired - Fee Related CN201303304Y (en) | 2008-11-21 | 2008-11-21 | Multi-channel high-speed servomotor control device based on FPGA |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103048955A (en) * | 2012-12-04 | 2013-04-17 | 常州大学 | Field programmable analogue array (FPAA) and field programmable gate array (FPGA)-based intelligent reconfigurable flexible motor control system |
| CN101741295B (en) * | 2009-12-31 | 2013-07-17 | 陕西捷普控制技术有限公司 | Single FPGA chip-based driving system for multiple rear-earth permanent-magnet synchronous motors |
| EP2953260A1 (en) * | 2014-06-02 | 2015-12-09 | Innoserv Fa Inc. | Servo motor drive |
| CN105137852A (en) * | 2015-06-26 | 2015-12-09 | 上海沈德医疗器械科技有限公司 | Multichannel ultrasonic driver parallel controller of phase-control HIFU (High Intensity Focused Ultrasound) system |
| CN106240145A (en) * | 2016-07-29 | 2016-12-21 | 西安电子科技大学 | The polychrome flexible steel roller printing machine automatic voltage regulating system controlled based on monolithic FPGA |
| CN106716840A (en) * | 2014-10-17 | 2017-05-24 | 密克罗奇普技术公司 | Analog-to-digital conversion with micro-coded sequencer |
| CN106712613A (en) * | 2016-12-22 | 2017-05-24 | 兰州空间技术物理研究所 | Stepping motor crossing redundant driving control system |
| CN109781209A (en) * | 2019-03-01 | 2019-05-21 | 杭州依美洛克医学科技有限公司 | Liquid relief and liquid level detection circuit |
-
2008
- 2008-11-21 CN CNU2008202225599U patent/CN201303304Y/en not_active Expired - Fee Related
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741295B (en) * | 2009-12-31 | 2013-07-17 | 陕西捷普控制技术有限公司 | Single FPGA chip-based driving system for multiple rear-earth permanent-magnet synchronous motors |
| CN103048955A (en) * | 2012-12-04 | 2013-04-17 | 常州大学 | Field programmable analogue array (FPAA) and field programmable gate array (FPGA)-based intelligent reconfigurable flexible motor control system |
| CN103048955B (en) * | 2012-12-04 | 2015-10-28 | 常州大学 | The flexible electric machine control system of a kind of intelligent reconstruction based on FPAA and FPGA |
| EP2953260A1 (en) * | 2014-06-02 | 2015-12-09 | Innoserv Fa Inc. | Servo motor drive |
| CN106716840A (en) * | 2014-10-17 | 2017-05-24 | 密克罗奇普技术公司 | Analog-to-digital conversion with micro-coded sequencer |
| CN106716840B (en) * | 2014-10-17 | 2021-03-30 | 密克罗奇普技术公司 | Analog-to-digital conversion with micro-coded sequencer |
| CN105137852A (en) * | 2015-06-26 | 2015-12-09 | 上海沈德医疗器械科技有限公司 | Multichannel ultrasonic driver parallel controller of phase-control HIFU (High Intensity Focused Ultrasound) system |
| CN105137852B (en) * | 2015-06-26 | 2019-01-25 | 上海沈德医疗器械科技有限公司 | Phased high intensity focused ultrasound system channel ultrasonic driver parallel control device |
| CN106240145A (en) * | 2016-07-29 | 2016-12-21 | 西安电子科技大学 | The polychrome flexible steel roller printing machine automatic voltage regulating system controlled based on monolithic FPGA |
| CN106240145B (en) * | 2016-07-29 | 2018-05-25 | 西安电子科技大学 | Polychrome flexible steel roller printing machine automatic voltage regulating system based on monolithic FPGA controls |
| CN106712613A (en) * | 2016-12-22 | 2017-05-24 | 兰州空间技术物理研究所 | Stepping motor crossing redundant driving control system |
| CN106712613B (en) * | 2016-12-22 | 2019-04-05 | 兰州空间技术物理研究所 | A kind of stepper motor crossing redundancy driving control system |
| CN109781209A (en) * | 2019-03-01 | 2019-05-21 | 杭州依美洛克医学科技有限公司 | Liquid relief and liquid level detection circuit |
| CN109781209B (en) * | 2019-03-01 | 2023-12-08 | 杭州依美洛克医学科技有限公司 | Pipetting and liquid level detection circuit |
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| C14 | Grant of patent or utility model | ||
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090902 Termination date: 20121121 |