CN201243297Y - Decoder for modem - Google Patents
Decoder for modem Download PDFInfo
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- CN201243297Y CN201243297Y CNU2008200407978U CN200820040797U CN201243297Y CN 201243297 Y CN201243297 Y CN 201243297Y CN U2008200407978 U CNU2008200407978 U CN U2008200407978U CN 200820040797 U CN200820040797 U CN 200820040797U CN 201243297 Y CN201243297 Y CN 201243297Y
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- converter
- fpga
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- decoder
- modem
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Abstract
Disclosed is a encoder for a modem, which comprises a singlechip, a DDS, a singlechip, a FPGA, a DSP component, an A/D converter, and a D/A converter; the clock signal output generated by the DDS is connected with the clock input interfaces of the FPGA, the DSP component, the A/D converter and the D/A converter; the singlechip is connected with the control interface of the MODEM formed by the FPGA; and the A/D converter and the D/A converter are all connected with the input interface and the output interface of the FPGA. The encoder for the modem can perform the encoding and decoding in the embedded software of speed self-adapting for the digital communication system and in the transmission software of outburst data for the MODEM system.
Description
Technical field
The utility model relates to analog communication and digital communication technology, relates in particular to the decoder device that uses in the variable bit rate modulation-demodulation device.
Background technology
Advantages such as digitlization is the trend of present radiotechnics development, and it has the reliability height, flexibility is strong and easily extensive integrated come into one's own day by day.Often will be in the communication according to the situation and the communication type change communication speed of communication channel, and keep the lower error rate, utilize digital communication technology can reach this requirement.
In the existing code cascading scheme: channel coding theorem points out that along with the increase of code length n, the decoding error probability approaches zero by index.Therefore want reliable communication just must use long code, but along with the increase of code length, the complexity of decoder, amount of calculation also increase thereupon, consequently are difficult to be applied in the practical matter.In order to solve performance and the contradiction that realizes difficulty, Forney proposes the cascaded code notion, promptly several short sign indicating numbers is serially connected and forms the long coded combination of a code length, what divides the process of establishment long code finish, and reduces the complexity of decodings at different levels with this.Usually cascaded code divides two-stage.
Usually when making up cascaded code, inside and outside sign indicating number selects to have complementary sign indicating number type.As what adopt at the utility model China and foreign countries sign indicating number is the RS sign indicating number, and ISN is selected convolution code, the advantage of RS sign indicating number and convolution code serial concatenation of codes is to combine the ability of RS sign indicating number burst-error-correction and the ability that convolution code is entangled random error, obtain error-correcting performance preferably under relatively low complexity, this cascaded code combining form is used as standard recommendation by CCSDS.And in structure grouping convolution level joined mark, key is the parameter N of block code, K, the parameter n of d and convolution code, the comparatively suitable problem of how arranging in pairs or groups between k and the m.If the symbol of outer sign indicating number RS sign indicating number is taken from GF (2^M) territory, it is proper that the coding bound degree m of convolution code equals M.For constraint degree is the convolution code of m, and the length of the most probable error pattern of interior decoder output is m, when this mistake is input to the RS decoder, only is equivalent to a symbol error in the RS sign indicating number, therefore brings into play RS sign indicating number error correcting capability easily.If m is too short, then the decoding error probability of Viterbi decoder is bigger, directly has influence on the performance of outer sign indicating number RS sign indicating number.And when adopting the bigger convolution code of m, though the decoding error probability can be lower, the complexity of Viterbi decoder increases with the m index, therefore should not select too much.The code check R of ISN convolution code generally selects 1/2 or 1/3 for use, and this is that to requiring about 10^ (3) of the ISN error rate, this convolution code with R=1/2 or 1/3 is easy to reach, and the realization of decoder also is easier to because in the cascaded code system.If select the higher convolution code of code check for use, then be not easy to reach the requirement of the error rate.The error rate requirement of the selection major decision whole system of outer sign indicating number code check, i.e. the whole system coding gain that will obtain.In general, when the error rate one timing, along with the increase error correcting capability of code length is more and more higher, but the complexity of decoder also increases thereupon, and after code length is greater than certain numerical value, to the performance improvement of whole system also not clearly, therefore must require and decoding complexity according to the error rate of whole system, multianalysis is relatively selected the code check of rational inside and outside sign indicating number.
The utility model content
The utility model purpose is the decoder that proposes a kind of variable-rate modems, and the decoder that cooperates transmission rate to change according to channel conditions, can error correction coding and decoding, and the information rate excursion is 8kbps-2Mbps; E
b/ N
0During=8dB, the error rate≤10
-6Especially obtain requiring and decoding complexity, select the decoder of the code check of rational inside and outside sign indicating number according to the error rate of whole system.
Technical solution of the present utility model is: the decoder of modulator-demodulator, it is characterized in that forming by single-chip microcomputer, DDS, single-chip microcomputer, FPGA, DSP device, A/D converter and D/A converter, the clock signal output that DDS produces connects the clock input port of FPGA, DSP device, A/D converter, D/A converter, single-chip microcomputer connects the control interface of the MODEM of FPGA formation, and A/D converter and D/A converter all connect input and the output interface of FPGA.The data-interface of FPGA and DSP device is connected to each other, and coding, shaping filter, matched filtering, symbol timing, frequency offset estimating, Viterbi decoding, RS decoder digital processing function are finished by FPGA and DSP; System platform is finished the processing of different business and different rates, and hardware configuration can dynamic load.
The utility model reads in the data that will transmit from main control computer and writes input buffer cell (ping-pong structure), by the RS encoder data of buffering are read with the channel speed (processing clock only needs to get final product more than or equal to channel speed) of twice then and carry out the RS coding, send into the convolutional encoding unit after data behind the coding and the string conversion and carry out convolutional encoding, then will be through the I after the convolutional encoding, the Q two paths of data is sent into the interleaver I of equivalent construction respectively, Q, at last coded data is sent into the output buffering and with channel speed data are read the modulator unit of sending into the rear end from the output buffering simultaneously, control unit is responsible for all module control signals and is produced.
If (its bandwidth of filtering is π/D) to X but at first use a digital filter
D(e
J ω) carry out filtering, make X
D(e
J ω) in only contain spectrum component (corresponding analog frequency be π f less than π/D
S/ D), carrying out D again and doubly extract, aliasing just can not take place in the frequency spectrum after then extracting.Can get complete D times withdrawal device, the integral multiple interpolation just is meant inserts (I-1) individual null value between two primary sample points, if establishing the primary sample sequence is x (n), then the sequence after the interpolation is x
I(m):
The utility model beneficial effect: be implemented in digital communication rate adaptation embedded software and the MODEM system burst data transmission software and carry out coding and decoding, but extensive use.When signal to noise ratio is hanged down, adopt lower rate transmissions to guarantee the low error rate; Perhaps when certain signal to noise ratio, adopt lower rate transmissions to save power.Especially obtain requiring and decoding complexity, obtain the decoder of the code check of rational inside and outside sign indicating number according to the error rate of whole system.
Description of drawings
Fig. 1 is the utility model coding and decoding flow chart
Fig. 2 be the utility model device block diagram,
Fig. 3 is the modulator principle figure that the utility model constitutes
Fig. 4 be the clock generating block diagram,
Fig. 5 is the utility model demodulator flow chart
Fig. 6 is AD, the DA circuit diagram of the utility model device
Fig. 7 is microprocessor and peripheral circuit diagram
Fig. 8 is dsp chip and peripheral circuit diagram
Embodiment
The multistage realization of multistage realization (b) interpolation that realize to extract according to Fig. 1 flow process in Fig. 2 device is adopted based on FPGA (encode, interweave, deinterleave, decoding etc.), and DSP is the scheme of assisting.
1.1 modulator design
The modulator principle block diagram inserts circuit, mapper, pulse shaper, D/A converter, low pass filter and timing sequence generating circuit etc. by interface circuit, RS encoder, convolution coder, interleaver, decoding, information and forms as shown in Figure 3.
(1) RS coding
The RS sign indicating number that adopts is RS (126, a 112) sign indicating number, and primitive polynomial is
p(x)＝x
8+x
7+x
2+x+1
(2) convolutional encoding
The convolution code that adopts is (2,1,7), and its encoder generator polynomial is respectively:
G
1(X)＝1+X+X
2+X
3+X
6
G
2(X)＝1+X
2+X
3+X
5+X
6
(3) interweave
Convolutional interleave, interleave depth are MB, and be MB (B-1) time of delay.
(4) mapping
The modulation signal of DPSK can be expressed as
S(k)＝Acos(2πf
ct+θ
k)
θ wherein
k=θ
K-1+ Δ θ
k
θ
kBe the absolute phase of k symbol, Δ θ
kIt is the phase changing capacity between k symbol and k-1 the symbol.
(5) realization of forming filter
Forming filter is the root-raised cosine filter of rolloff-factor α.
(6) D/A conversion
D/A converter is finished the conversion of digital signal to analog signal, and D/A converter has two data input ports and two outputs, finishes the D/A switch of I (quadrature) branch road and Q (homophase) branch road respectively.
(7) clock generating is shown in Fig. 4 block diagram
Modulator-demodulator needs various clocks, and frequency division obtained after various required clocks produced a unified clock by DDS.
1.2 demodulator design: the input of base band demodulator is from the zero intermediate frequency quadrature detector, catch and symbol timing acquisition through the laggard line frequency difference of mould/number conversion, signal behind frequency offset correction is sent into matched filter, and its output can be done Differential Detection and decoding, as Fig. 5 demodulator principle and flow chart.The A/D conversion: A/D converter is used for the I of zero intermediate frequency input and the mould/number conversion of Q branch road.
(1) frequency offset correction: record multispectral reining in after the frequency deviation, it is transformed into frequency control word, send into digital controlled oscillator, produce orthogonal sine and cosine signal, the input signal after this signal and the A/D conversion carries out conjugate multiplication, can realize frequency offset correction.
(2) matched filtering: matched filter is the root-raised cosine filter of rolloff-factor α, same forming filter.
(3) regularly recover: bit timing recovery adopts " lead-lag detection method ", the lead-lag detection method produces the lead-lag margin of error to M times of symbol rate sampling of input analog baseband signal back by following formula, and this margin of error is by the sampling clock of digital phase-locked loop control A/D converter.
(4) Differential Detection: the signal of establishing matched filter output is x (n), and calculus of differences is output as
y(n)＝x(n)·x
*(n-1)
(6) deinterleaving: deinterleave circuit and interleave circuit are similar, and the interleaver input is from I, the synthetic quantitative information of Q two-way alternate group of demodulator.
(7) Viterbi decoding: the Viterbi decoder of convolution code adopts FPGA to realize, shown in the block diagram that Figure 11 decoder adopts the FPGA realization.
(8) RS decoding: RS decoding is realized by FPGA equally.The utility model adopts (2,1,7) Viterbi coding, (126,112) RS coding.Channel cascaded encoding scheme such as Figure 12 of adopting.
1.3 power supply: outside input supply voltage converts the needed various voltages of modulator-demodulator to through power conversion chip.
The utility model adopts the Cyclone device based on a kind of brand-new low-cost framework, has just taken into full account the saving of cost at the beginning of design, so brand-new programmable solution can be provided for the application of Price Sensitive.
Need and have ready conditions to embed second party specialty eda tool if having, we use matlab6.5 and CCS as the debugging and verification platform according to actual conditions.After design content was configured to circuit board EP1C20, the variable that will observe by the interface of DSP and FPGA read in computer, handled with its coding and decoding function result comparing then by matlab, the correctness of checking design.
Device of the present utility model is formed: system is made up of devices such as A/D converter, D/A converter, DDS, single-chip microcomputer, FPGA, DSP, DDS produces needed clock, single-chip microcomputer is finished the interface control with main control computer and MODEM, and digital processing functions such as coding, shaping filter, matched filtering, symbol timing, frequency offset estimating, Viterbi decoding, RS decoder are finished by FPGA and DSP.System platform is finished the processing of different business and different rates, and hardware configuration can dynamic load.There are four kinds of schemes to select, the one, based on FPGA, dsp software is auxilliary; The 2nd, with FPGA and special chip (Viterbi coding and decoding and RS coding and decoding integrated circuit) combination; The 3rd, based on dsp software, FPGA is auxilliary; The 4th, based on dsp software and special chip, FPGA hardware is auxilliary.Consider that system upgrade needs (raisings of system transmissions speed) and system's versatility, flexibility, employing is based on FPGA (encode, interweave, deinterleave, decoding etc.), and DSP is the scheme of assisting.
The FPGA that selects for use in the utility model is that altera corp releases the minimum FPGA device series of products Cyclone of the present cost of industry a few days ago.From 2,910 to 20,060 logical blocks of Cyclone device capacity (240,000 gates or more than 100 ten thousand system doors) and the embedding memory of 288kb nearly.The special interface circuit of each Cyclone device is all integrated single data rate SDRAM and double data rate (DDR) (DDR) SDRAM and FCRAM device is supported multiple single-ended I/O standard, comprises LVTTL, LVCOMS, PCI, SSTL-2 and SSTL-3.And having nearly 129 low-voltage differential signals (LVDS) compatible channels, each channel performance can be up to 311Mbps.Wherein embedding memory has many advantages, not only supports various memory modules, but also support the byte enable operation, based on the error correction of parity check and the port store design that do not wait bit wide.These functions are used for some specific occasion can save designer's design time, as sign indicating number process object difference in the utility model because inside and outside the cascaded code (outer yard is that object, ISN are object with the bit with the byte), so between will be done extra conversion, if but utilize the not equipotential wide port function of Cyclone embedded memory just can finish.Whole system is mainly realized by programming devices such as single-chip microcomputer, DSP, FPGA, is achieved as follows function by single-chip microcomputer, DSP, FPGA are carried out embedded programming:
(1) variable bit rate modulation adopts the digital interpolation filter to realize.
(2) if sampling and Digital Down Convert, many speed filtering technique realize that variable Rate receives.
(3) signal demodulation techniques comprise sign synchronization, carrier synchronization, matched filtering, frequency offset estimating etc.
(4) encoding and decoding technology comprises convolutional encoding, RS coding, Viterbi decoding, RS decoding.
The utility model research has reached re-set target, and promptly the information rate excursion is 8kbps-2Mbps; E
b/ N
0During=8dB, the error rate≤10
-6Development along with radio network technique, become a kind of trend at transmitted over wireless networks video and audio frequency, the utility model can be used for army's military exercises, public security, fire-fighting People's Armed Police floor manager and exploration, and other urgent emergency commading system, it mainly acts on is can be with real time bidirectional transmission lteral data, audio frequency, video between scene and the command centre, to improve commander's accuracy and promptness.The occasions such as real-time monitoring that also are used for urban transportation.
The FPGA of 2 Viterbi decoding realizes
Realize the Viterbi decoding algorithm with FPGA, method commonly used has serial realization, Parallel Implementation and string and combination to realize, serial only utilizes an ACS unit serial to realize the renewal of the path metric value of each state in realizing, realize that so the most outstanding advantage is to save hardware resource, but this method also there is apparent in view shortcoming: the low and complex time of decoder throughput.For example realize the decoder of a constraint length K=7, have 2
K-1=64 states, code word of every like this reception needs 64 master clock cycles just can finish processing procedure at least, because each built-in function unit needs stream treatment in specific implementation, such 64 processing clock cycles are just not much of that, and so realization will make inner sequential quite complicated, need to do accurate control, so just aggravated the workload of hardware designs greatly.
The AD sampling section mainly is made up of two parts among Fig. 6: 1, operational amplifier TL082 adjusts the level of analog input signal, makes the incoming level of AD converter within the scope that requires; 2, high-performance single-ended-differential conversion chip AD8138 is converted to differential signal with single-ended signal, to improve the sampling precision of AD converter; 3, AD9238 samples simultaneously to I, Q two-way analog signal, and the digital signal of sampling is sent into FPGA.The DA conversion portion mainly is made up of three parts: 1, AD9761 converts the digital signal of FPGA output to pulse signal; 2, low pass filter LT1568 pulse signals filtering, filtering image frequency component; 3, operational amplifier TL082 carries out the ratio amplification to filtered baseband signal, to arrive the output signal level of system requirements.
Microprocessor adopts the high-performance single chip computer AT MEGA128L of atmel corp among Fig. 7, this single-chip microcomputer adopts reduced instruction set computer, most of instruction is one-cycle instruction, the efficient height, and sheet contains richs in natural resources such as hardware multiplier, UART, FLASH, EEPROM, hardware watchdog, PWM, ADC.The outside MAX706 that adopts has improved system reliability greatly as resetting chip.
Dsp chip adopts the TMS320VC5410A of TI company among Fig. 8, and the disposal ability of this processor can reach 160MIPS, and inside contains 18 hardware multipliers, and MAC, CSSU, 40 bit accumulators are specially adapted to digital signal processing algorithms such as FFT, FIR.In addition, adopt the ROM of high-capacity FLASH chip SST39VF800A, can store lot of data as TMS320VC5410A.This part adopts DDS special chip AD9851 to produce system clock among Fig. 9.This circuit has output clock flexibility and changeability, and output frequency precision is better than 20mHz.The output clock frequency can accurately be set by microprocessor, is specially adapted to the realization of variable-rate modems.
Claims (1)
1, the decoder of modulator-demodulator, it is characterized in that forming by single-chip microcomputer, DDS, single-chip microcomputer, FPGA, DSP device, A/D converter and D/A converter, the clock signal output that DDS produces connects the clock input port of FPGA, DSP device, A/D converter, D/A converter, single-chip microcomputer connects the control interface of the MODEM of FPGA formation, and A/D converter and D/A converter all connect input and the output interface of FPGA.
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|---|---|---|---|
| CNU2008200407978U CN201243297Y (en) | 2008-07-23 | 2008-07-23 | Decoder for modem |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200407978U CN201243297Y (en) | 2008-07-23 | 2008-07-23 | Decoder for modem |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208961A (en) * | 2011-05-17 | 2011-10-05 | 中国电子科技集团公司第十研究所 | Low-delay R-S coder/decoder realization method applicable to CCSDS (Consultative Committee for Space Data Systems) standard |
-
2008
- 2008-07-23 CN CNU2008200407978U patent/CN201243297Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208961A (en) * | 2011-05-17 | 2011-10-05 | 中国电子科技集团公司第十研究所 | Low-delay R-S coder/decoder realization method applicable to CCSDS (Consultative Committee for Space Data Systems) standard |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: NANJING ENGINE INFORMATION + TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: NANJING MAGNET TECHNOLOGY CO., LTD. Effective date: 20130318 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 210036 NANJING, JIANGSU PROVINCE TO: 210000 NANJING, JIANGSU PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20130318 Address after: 210000, room 55, 103 Hong Kong court, Qinhuai District, Jiangsu, Nanjing Patentee after: Nanjing Anze Information Technology Co., Ltd. Address before: 210036, room 101, Jiangdong North Road, Gulou District, Nanjing, Jiangsu 303, China Patentee before: Nanjing Magnet Technology Co., Ltd. |
|
| CX01 | Expiry of patent term |
Granted publication date: 20090520 |
|
| CX01 | Expiry of patent term |