CN201210410Y - Electricity drop transient memory used for passive RFID label chip - Google Patents
Electricity drop transient memory used for passive RFID label chip Download PDFInfo
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- CN201210410Y CN201210410Y CNU2008200807237U CN200820080723U CN201210410Y CN 201210410 Y CN201210410 Y CN 201210410Y CN U2008200807237 U CNU2008200807237 U CN U2008200807237U CN 200820080723 U CN200820080723 U CN 200820080723U CN 201210410 Y CN201210410 Y CN 201210410Y
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Abstract
A power-fail transient memory for passive radio frequency identification tag relates to the memory technology of circuit field. The utility model supplies power by supply voltage VDD, comprising a reference current supply for supplying bias current to memory unit and judgment logic; a controlling unit for generating a controlling signal to operate the memory unit according to the reset signal RESET given by the digital circuit and to-be-stored information STM-IN; a bias voltage generation circuit for converting the reference current generated by the reference current source into the voltage reference as the reference signal of judging the logic; a memory unit for transiently storing the to-be-stored information according to the instruction of the controlling unit; a judgment logic comparing the relationship between the memory unit memory content and the voltage reference and converting the analog signals into digital signal STM-OUT to output to the digital circuit. The utility model is able to transiently store the state information of the tag chip before power-fail or the middle state of the digital circuit to improve the efficiency and stability of the short distance wireless communication.
Description
Technical field
The utility model relates to the memory technology of circuit field, especially for the power-failure transient memory of chips such as radio-frequency (RF) identification (RFID) electronic tag.
Background technology
Along with the fast development of integrated circuit (IC) design technology, the RFID technology just is being widely used in the every field of productive lifes such as industrial automation, business automation and communications and transportation control and management.Typical R FID system is divided into three parts: read write line, RFID label and the information processing terminal.Read write line is used for label such as is read and write at operation, label be in the rfid system storage by the carrier of sign individual information.
For passive RFID tags, the power supply of chip is generally obtained by the electromagnetic field that antenna component induction read write line produces.Because some non-ideal factors such as environment, label temporary transient power down may occur and recover such situation again rapidly in the recognition process.Such as in the tag recognition process, an object passes through in the middle of card reader and label, blocks or sponge the part electromagnetic wave, the label power down, and power supply recovers again when object leaves in the middle of card reader and label.If certain label power down in the recognition process, and the status information of this label loses can make read write line normally to distinguish this label and other label in being in simultaneously by original program, read write line need start anew to distinguish all interior labels again.Obviously, this will reduce the efficient of read write line recognition label, i.e. the tag recognition number of unit interval.
In order to address this problem, some RFID communication protocol requires under the temporary transient preservation of the information such as state of living in of label before power down.When after power down a period of time, powering on once more, check the information of preserving in the storer, and, make the state before label enters power down according to the value of being preserved.Volatile memory of the prior art canned data after power down can be lost immediately, and nonvolatile memory will keep for a long time in the information of power down background storage, all can not satisfy the requirement of RFID communication protocol to state storage.
Summary of the invention
In order to solve above-mentioned problems of the prior art, the purpose of this utility model provides a kind of power-failure transient memory that is used for passive radio-frequency identification labeled chip.It can improve the efficient and the stability of this short-distance wireless communication with the intermediateness short time storage of status information before the label chip power down or digital circuit.
In order to reach the foregoing invention purpose, the technical solution of the utility model realizes as follows:
The power-failure transient memory that is used for passive radio-frequency identification labeled chip, its design feature are that it is comprised by supply voltage VDD power supply:
Reference current source is for storage unit and decision logic provide bias current;
Control module is the interface circuit of digital circuit and storage unit, the reset signal RESET that provides according to digital circuit and wait to deposit information STM_IN and produce control signal storage unit is operated;
Bias-voltage generating circuit is the interface circuit of reference current source and decision logic, and the reference current that reference current source is produced is converted to reference voltage, as the reference signal of decision logic;
Storage unit according to the instruction of control module, is treated the information of depositing and is carried out the transient state storage;
Decision logic, relatively the relation of cell stores content and reference voltage becomes digital signal STM_OUT to export to digital circuit analog signal conversion.
In above-mentioned power-failure transient memory, described reference current source is made of the current reference generation circuit of band gap reference and the inferior current source of Weir.
In above-mentioned power-failure transient memory, described control module is by phase inverter, Sheffer stroke gate, rejection gate, constitute with door or door, transmission gate and MUX.
In above-mentioned power-failure transient memory, described bias-voltage generating circuit is made of current mirror and resistive components and parts, and resistance element adopts resistance, diode or metal-oxide-semiconductor.
In above-mentioned power-failure transient memory, described storage unit is made of charge switch, discharge switch and memory capacitance.Charge switch, discharge switch adopt the electron device that has switching characteristic and leak electricity under off state, memory capacitance adopts the electron device with capacitance characteristic.
In above-mentioned power-failure transient memory, the charging voltage of described cell stores electric capacity is produced by bias-voltage generating circuit.The quantity of electric charge of memory capacitance and the time of being stored by the control of the leakage current under the metal-oxide-semiconductor off state in charge switch, discharge switch transient state, the shutoff leakage current of charge switch is less than the shutoff leakage current of discharge switch.
In above-mentioned power-failure transient memory, described decision logic is made of hysteresis comparator, sense amplifier, operational amplifier and phase inverter.
The utility model is owing to adopted said structure, with a kind of storage organization that is similar to dynamic RAM (DRAM), electric charge is stored and is utilized the non-ideal characteristic (there is electric leakage down in off state) of charge and discharge switch constitute short time power-failure transient memory circuit by memory capacitance.The utility model is applicable to the short time storage after the status information power down of the desired label chip of RFID communication protocol, also can be used for the occasion that other needs storage of information power-failure transient or the storage of circuit intermediateness transient state.
Be described further below in conjunction with the drawings and specific embodiments the utility model.
Description of drawings
Fig. 1 is a structural representation of the present utility model;
Fig. 2 is an external interface synoptic diagram of the present utility model;
Fig. 3 is the circuit theory diagrams of the utility model embodiment;
Voltage when Fig. 4 is the utility model power down operations, signature tune line chart.
Embodiment
Referring to Fig. 1 and Fig. 2, the utility model is comprised by supply voltage VDD power supply: reference current source, and the current reference that comprises band gap reference and the inferior current source of Weir produces circuit and constitutes, for storage unit and decision logic provide bias current; Control module, by phase inverter, Sheffer stroke gate, rejection gate, constitute with door or door, transmission gate and MUX, be the interface circuit of digital circuit and storage unit, the reset signal RESET that provides according to digital circuit and wait to deposit information STM_IN and produce control signal storage unit is operated; Bias-voltage generating circuit, be made of current mirror and resistive components and parts, resistance element adopts resistance, diode or metal-oxide-semiconductor, is the interface circuit of reference current source and decision logic, the reference current that reference current source is produced is converted to reference voltage, as the reference signal of decision logic; Storage unit, by charge switch, discharge switch and memory capacitance constitute, charge switch, discharge switch adopts the electron device that has switching characteristic and leak electricity under off state, memory capacitance adopts the electron device with capacitance characteristic, the charging voltage of memory capacitance is produced by bias-voltage generating circuit, the quantity of electric charge of memory capacitance and by charge switch, the time of the leakage current control transient state storage in the discharge switch under the metal-oxide-semiconductor off state, the shutoff leakage current of charge switch is less than the shutoff leakage current of discharge switch, storage unit is treated the information of depositing and is carried out the transient state storage according to the instruction of control module; Decision logic is made of hysteresis comparator, sense amplifier, operational amplifier and phase inverter, and relatively the relation of cell stores content and reference voltage becomes digital signal STM_OUT to export to digital circuit analog signal conversion.
Referring to Fig. 3, wherein capacitor C 1, metal-oxide-semiconductor M1～M11 and electric capacity R0 constitute reference current source, M12～M14 constitutes bias-voltage generating circuit, M15～M16 and M17 are respectively charging and the discharge switch of memory capacitance C2, M18～M27 constitutes hysteresis comparator, and M29～M30 constitutes the buffering output of phase inverter as circuit.The utility model power-failure transient memory (Off Power Short Term Memory) that is formed by the foregoing circuit structure satisfies stores a period of time T1 second to logical one behind power supply power-fail, the accurate sense information of energy when T1 powers in the time once more, power down surpasses the T1 function that second, storing value made zero.For logical zero, need in control module, convert logical one to and be stored again, also need to add the anti-phase output of one-level at the decision logic output terminal, circuit structure is similar will not be given unnecessary details.
Referring to Fig. 4, when the utility model uses, reference current source produces bias current, bias-voltage generating circuit converts reference current to reference voltage (curve 4), reset signal RESET and the control signal of waiting to deposit information STM_IN (curve 1) process control module generation memory capacitance charge and discharge switch pipe.Supply voltage VDD (curve 2) just often, control signal is deposited information STM_IN (curve 1) real-time change according to be written waiting, write information in the memory capacitance, and through decision logic output, output signal STM_OUT (curve 5) and the time-delay of waiting to deposit on information STM_IN (curve 1) only time.During power down, control signal all becomes low, and all electric capacity are turned off to the path on ground, and by the imperfection that discharges and recharges in switch, the leakage current when memory capacitance voltage (curve 3) will turn-off by switch slowly discharges.When power up in the regular hour just often, decision logic read memory capacitance voltage (curve 3) and and reference voltage (curve 4) compare, thereby provide storing value.
Claims (7)
1, be used for the power-failure transient memory of passive radio-frequency identification labeled chip, it is characterized in that, it is comprised by supply voltage VDD power supply:
Reference current source is for storage unit and decision logic provide bias current;
Control module is the interface circuit of digital circuit and storage unit, the reset signal RESET that provides according to digital circuit and wait to deposit information STM_IN and produce control signal storage unit is operated;
Bias-voltage generating circuit is the interface circuit of reference current source and decision logic, and the reference current that reference current source is produced is converted to reference voltage, as the reference signal of decision logic;
Storage unit according to the instruction of control module, is treated the information of depositing and is carried out the transient state storage;
Decision logic, relatively the relation of cell stores content and reference voltage becomes digital signal STM_OUT to export to digital circuit analog signal conversion.
2, power-failure transient memory according to claim 1 is characterized in that, described reference current source is made of the current reference generation circuit of band gap reference and the inferior current source of Weir.
3, power-failure transient memory according to claim 1 is characterized in that, described control module is by phase inverter, Sheffer stroke gate, rejection gate, constitute with door or door, transmission gate and MUX.
4, power-failure transient memory according to claim 1 is characterized in that, described bias-voltage generating circuit is made of current mirror and resistive components and parts, and resistance element adopts resistance, diode or metal-oxide-semiconductor.
5, power-failure transient memory according to claim 1, it is characterized in that, described storage unit is made of charge switch, discharge switch and memory capacitance, charge switch, discharge switch adopt the electron device that has switching characteristic and leak electricity under off state, memory capacitance adopts the electron device with capacitance characteristic.
6, power-failure transient memory according to claim 1 or 5, it is characterized in that, the charging voltage of described cell stores electric capacity is produced by bias-voltage generating circuit, the quantity of electric charge of memory capacitance and the time of being stored by the control of the leakage current under the metal-oxide-semiconductor off state in charge switch, discharge switch transient state, the shutoff leakage current of charge switch is less than the shutoff leakage current of discharge switch.
7, power-failure transient memory according to claim 1 is characterized in that, described decision logic is made of hysteresis comparator, sense amplifier, operational amplifier and phase inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200807237U CN201210410Y (en) | 2008-05-21 | 2008-05-21 | Electricity drop transient memory used for passive RFID label chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200807237U CN201210410Y (en) | 2008-05-21 | 2008-05-21 | Electricity drop transient memory used for passive RFID label chip |
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| Publication Number | Publication Date |
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| CN201210410Y true CN201210410Y (en) | 2009-03-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2008200807237U Expired - Lifetime CN201210410Y (en) | 2008-05-21 | 2008-05-21 | Electricity drop transient memory used for passive RFID label chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101587743B (en) * | 2008-05-21 | 2012-01-04 | 北京同方微电子有限公司 | Power-failure transient memory used for passive radio-frequency identification labeled chip |
| CN104285255A (en) * | 2012-05-07 | 2015-01-14 | 高通股份有限公司 | Circuits configured to remain in a non-program state during a power-down event |
| CN104573792A (en) * | 2014-12-17 | 2015-04-29 | 北海市蕴芯电子科技有限公司 | Electricity discharging self-feedback circuit of low-frequency half-duplex passive radio frequency card |
-
2008
- 2008-05-21 CN CNU2008200807237U patent/CN201210410Y/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101587743B (en) * | 2008-05-21 | 2012-01-04 | 北京同方微电子有限公司 | Power-failure transient memory used for passive radio-frequency identification labeled chip |
| CN104285255A (en) * | 2012-05-07 | 2015-01-14 | 高通股份有限公司 | Circuits configured to remain in a non-program state during a power-down event |
| CN104285255B (en) * | 2012-05-07 | 2017-03-29 | 高通股份有限公司 | It is configured to the circuit of non-programmed state is maintained at during power loss event |
| CN104573792A (en) * | 2014-12-17 | 2015-04-29 | 北海市蕴芯电子科技有限公司 | Electricity discharging self-feedback circuit of low-frequency half-duplex passive radio frequency card |
| CN104573792B (en) * | 2014-12-17 | 2017-08-04 | 北海市蕴芯电子科技有限公司 | A kind of low frequency half-duplex passive RF card rushes down electric self-feedback ciucuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20090318 Effective date of abandoning: 20080521 |