CN201117293Y - Memory writing protection circuit and television with the same - Google Patents
Memory writing protection circuit and television with the same Download PDFInfo
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- CN201117293Y CN201117293Y CNU2007201573896U CN200720157389U CN201117293Y CN 201117293 Y CN201117293 Y CN 201117293Y CN U2007201573896 U CNU2007201573896 U CN U2007201573896U CN 200720157389 U CN200720157389 U CN 200720157389U CN 201117293 Y CN201117293 Y CN 201117293Y
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Abstract
The utility model discloses a memory written protection circuit, which aims at preventing a system from doing clerical error operation on a memory, and the structure is that one side of a reading-writing control port is connected with a voltage pull up branch circuit, and the other side is connected with ground through a switch access of a controlled switch circuit, the control end of the controlled switch circuit receives control signals which are output by CPU, and the reading-writing status of a memory is controlled by the CPU. The memory written protection circuit of the utility model has simple structure, which is easy to be achieved, can effectively improve written operation of the memory, and prevents the probability of clerical error operation from happening. The utility model simultaneously discloses a television which is applied in the memory written protection circuit, which can obviously improve the reliability and stability of television operation, and thereby the television is beneficial for improving the property quality of an integral machine.
Description
Technical field
The utility model belongs to the memory circuitry technical field, specifically, relates to a kind of for preventing that memory devices from being rewritten custom-designed memory write holding circuit by mistake and using the televisor of described circuit.
Background technology
For present tv product, increasing televisor adopts eeprom memory to store some data, such as information datas such as the state of channel frequency, machine, user-defined volumes; The essential data of other start also can write wherein.The existing memory holding circuit generally all is that storer is arranged on the state of can writing; if in the complete machine powering process or in the frequent switching on and shutting down process; because certain unpredictable operation makes data in the eeprom memory by improper rewriting or wipe; to cause complete machine work to occur unusual or can not start shooting, have a strong impact on the complete machine quality of tv product.
The utility model content
The purpose of this utility model is to provide a kind of memory write holding circuit, by design read-write control circuit on the read-write control port of storer, can significantly improve the write operation of storer, reduces the possibility of mistake write operation.
For solving the problems of the technologies described above; the concrete structure of the memory write holding circuit that the utility model proposed is: the read-write control port of storer connects on the one hand and draws branch road on the voltage; by the switch ways ground connection of gate-controlled switch circuit, the control end of described gate-controlled switch circuit receives the control signal of CPU output on the other hand.
Wherein, draw branch road can adopt pull-up resistor to be connected realization with direct supply on the described voltage, when needs are arranged on storer read states, controlling described gate-controlled switch circuit by CPU ends, described direct supply affacts on the read-write control port of storer by pull-up resistor, makes it be in a high level read states.
Further, in order in the circuit performance history, to make things convenient for the technician that storer is carried out debugging operations, on the read-write control port of described storer, also be connected with a debug circuit, in described debug circuit, include a manual break-make unit, be connected between the read-write control port and ground of described storer.
Wherein, described manual break-make unit preferably adopts jumper wire device, the simple structure forms such as switch or wire interconnecting piece of alloting realize, by the connection or the cut-off state of the described break-make of manual change unit, realizes the read-write operation of technician to storer.
Further again; in order to save the port resource of CPU; the utility model carries out multiplexing to the standby signal output pin of CPU; the control end that connects described gate-controlled switch circuit; the Opportunity awaiting control for linear signal is used for the read-write control signal of storer, makes storer when standby, be in the write-protect state, the mistake write operation that the transient voltage instability of avoiding starting shooting causes; and after start, enter the state of can writing, to finish normal read-write operation.
Based on above-mentioned storage protection circuit structure; the utility model has proposed a kind of televisor of using described storage protection circuit again; comprise eeprom memory and CPU, by connecting the ON-OFF control circuit of drawing branch road and controlling on the voltage on the read-write control port of described eeprom memory by CPU.When needs carry out write operation to eeprom memory, control described on-off circuit conducting by CPU, and then make the read-write control port ground connection of eeprom memory, enter low level and can write state; Otherwise, when needs place the write-protect state with eeprom memory, control described ON-OFF control circuit by CPU and end, make the read-write control port of eeprom memory be in high level state, carry out a read states to control it, prevent the generation of mistake write operation.
Compared with prior art, advantage of the present utility model and good effect are: storage protection circuit structure of the present utility model is simple, is easy to realize, can effectively improve the write operation of storer, prevents the probability that the mistake write operation takes place.Be applied to televisor etc. and have in the electric equipment of memory circuitry, can significantly improve electric equipment reliability of operation and stability, and then help to promote product machine performance quality.
After reading the detailed description of the utility model embodiment in conjunction with the accompanying drawings, other characteristics of the present utility model and advantage will become clearer.
Description of drawings
Fig. 1 is the theory diagram of the memory write holding circuit that proposes of the utility model;
Fig. 2 is the physical circuit schematic diagram of wherein a kind of embodiment of memory write holding circuit.
Embodiment
Below in conjunction with accompanying drawing embodiment of the present utility model is described in detail.
Memory write holding circuit of the present utility model is by carrying out specialized designs to the peripheral circuit that is connected on the memory read/write control port; control the high low-potential state of this port by CPU; thereby can when circuit system is in unstable working state, make storer enter the write-protect state, reach with this and effectively avoid data in the storer by the improper rewriting or the purpose of design of wiping.
Embodiment one, and referring to shown in Figure 1, Fig. 1 shows the theory diagram of the memory write holding circuit that the utility model proposes, and wherein, storer N1 is that example is illustrated with widely used EEPROM storage chip in the present tv product.The read-write control port WR low level of eeprom memory N1 is effective, promptly just can carry out write operation to eeprom memory N1 when WR is low level.In existing TV set circuit, this pin is directly grounded, whenever can carry out read-write operation to eeprom memory N1, thereby also bring potential safety hazard.Circuit after the improvement is controlled by CPU, on the one hand connect on the read-write control port WR of eeprom memory N1 by pull-up resistor R1, R2 and+draw branch road on the voltage that the 5V direct supply is formed; By the switch ways ground connection of a gate-controlled switch circuit, the control end of described gate-controlled switch circuit receives the control signal of CPU read-write control pin output on the other hand.When needs carry out write operation to eeprom memory N1, by CPU gauge tap circuit turn-on, and then make the read-write control port WR ground connection of eeprom memory N1, enter the state of can writing thereby control it; When needs carry out write-protect to eeprom memory N1; end by CPU gauge tap circuit; at this moment; the read-write control port WR of eeprom memory N1 is changed under the effect of drawing branch road on the voltage+the 5V noble potential; thereby control it and enter a read states, stop peripheral circuit that interior data is rewritten or wiped.
Described read-write control pin can provide specially by wherein one road IO mouth of CPU, but need additionally take the road port resource of CPU, can adopt under the resourceful situation of cpu port.And complicated for those circuit systems, if the circuit that the cpu port resource is nervous again with the read-write control pin of one road IO distribution as storer, can make the original just IO mouth resource of anxiety become nervous more undoubtedly.In order to address this problem, present embodiment has proposed a kind of cpu port multiplexing scheme again, specifically can adopt the standby signal output port of CPU to be also used as the read-write control pin of storer N1.The start sequential of considering televisor is to be introduced into holding state, through entering open state again after the time-delay after a while, utilizes standby signal output port output high level when start of program setting CPU, output low level when standby.Like this; before televisor enters open state; the standby signal output port output low level of CPU; the gauge tap circuit ends; at this moment; + 5V direct supply affacts the read-write control port WR of storer N1 by resistance R 1, R2, makes it be in a noble potential read states, and storer N1 is carried out write-protect.And after televisor transferred open state to from holding state, the level of the standby signal output port of CPU was uprised by low, and then the gauge tap circuit turn-on, made the read-write control port WR ground connection of storer N1, entered electronegative potential and can write state.Like this, the data of circuit system in can normal read memory write N1 are to guarantee the circuitry operate as normal.
Experiment shows, the rewriting of data or lose usually occurs in television boot-strap moment, reason be this moment circuit working stable as yet, if the impulse disturbances bus is arranged, may make the bus mistake write data, make data in the storer by improper rewriting or wipe.As long as storer is carried out write-protect, can solve memory data by the problem of mistake write operation in the moment of starting shooting.
The technician carries out debugging operations to eeprom memory N1 on stream for convenience; also design has a debug circuit in the memory write holding circuit of present embodiment; specifically be connected between the read-write control port WR and ground of eeprom memory N1, referring to shown in Figure 1.Described debug circuit can be selected jumper wire device, the simple structure forms such as switch or wire interconnecting piece of alloting are formed manual break-make unit, is connected between the read-write control port WR and ground of storer N1.When system's operate as normal, described manual break-make unit is disconnected, come storer N1 is read and write control by CPU; And when the technician debugs, manual break-make unit is communicated with, so just becoming the available circuit structure, available this compares experiment, is convenient in time find reason after this circuit goes wrong.
Embodiment two; referring to shown in Figure 2, present embodiment has specifically been enumerated a kind of line construction of write-protect circuit, wherein; it is that example is illustrated that the gate-controlled switch circuit adopts a NPN type triode V1, and it is that example is illustrated that debug circuit adopts a form of welding 0 Ω resistance R 3 between wire interconnecting piece.
Among Fig. 2, during the system operate as normal, 0 Ω resistance R 3 is not welded, and debug circuit disconnects.The base stage of NPN type triode V1 receives the high-low level control signal of its output as the read-write control pin of the control end connection CPU of on-off circuit, grounded emitter, and collector connects the read-write control port WR of eeprom memory N1.When needs carry out write operation to storer N1, send high-level control signal by CPU, control triode V1 conducting is changed to the read-write control port WR of storer N1 low, just can carry out write operation.Otherwise, when not needing that storer N1 carried out write operation, send the low level control signal by CPU; control triode V1 ends; the read-write control port WR of storer N1 is changed to height, makes storer N1 enter the write-protect state, so just can reduce the possibility that mistake is write EEPROM effectively.
When the technician need debug, 0 Ω resistance R 3 is welded between the read-write control port WR and ground of eeprom memory N1, like this, just make storer N1 be in the state of can writing always, make things convenient for technician's exploitation debugging work.
Certainly, above-mentioned memory write holding circuit also can be widely used in other electric equipment with memory circuitry, in case locking system is to the mistake write operation of storer.
Should be noted that; the above only is a kind of preferred implementation of the present utility model; for those skilled in the art; under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (10)
1, a kind of memory write holding circuit; it is characterized in that: the read-write control port of storer connects on the one hand and draws branch road on the voltage; by the switch ways ground connection of gate-controlled switch circuit, the control end of described gate-controlled switch circuit receives the control signal of CPU output on the other hand.
2, memory write holding circuit according to claim 1; it is characterized in that: on the read-write control port of described storer, also be connected with a debug circuit; in described debug circuit, include a manual break-make unit, be connected between the read-write control port and ground of described storer.
3, memory write holding circuit according to claim 2 is characterized in that: described manual break-make unit is jumper wire device, allot switch or wire interconnecting piece.
4, according to each described memory write holding circuit in the claim 1 to 3, it is characterized in that: described CPU connects the control end of described gate-controlled switch circuit by its standby signal output pin, exports described control signal.
5, memory write holding circuit according to claim 4 is characterized in that: draw to include pull-up resistor and direct supply in the branch road on described voltage, the read-write control port of described storer connects described direct supply by pull-up resistor.
6, a kind of televisor, comprise CPU and storer, it is characterized in that: the read-write control port of described storer connects on the one hand and draws branch road on the voltage, and by the switch ways ground connection of gate-controlled switch circuit, the control end of described gate-controlled switch circuit receives the control signal of CPU output on the other hand.
7, televisor according to claim 6, it is characterized in that: on the read-write control port of described storer, also be connected with a debug circuit, in described debug circuit, include a manual break-make unit, be connected between the read-write control port and ground of described storer.
8, televisor according to claim 7 is characterized in that: described manual break-make unit is jumper wire device, allot switch or wire interconnecting piece.
9, according to each described televisor in the claim 6 to 8, it is characterized in that: described CPU connects the control end of described gate-controlled switch circuit by its standby signal output pin, exports described control signal.
10, televisor according to claim 9 is characterized in that: draw to include pull-up resistor and direct supply in the branch road on described voltage, the read-write control port of described storer connects described direct supply by pull-up resistor.
Priority Applications (1)
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CNU2007201573896U CN201117293Y (en) | 2007-11-16 | 2007-11-16 | Memory writing protection circuit and television with the same |
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CNU2007201573896U CN201117293Y (en) | 2007-11-16 | 2007-11-16 | Memory writing protection circuit and television with the same |
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Cited By (7)
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CN104751814A (en) * | 2013-12-31 | 2015-07-01 | 乐金显示有限公司 | Memory protection circuit and liquid crystal display device including same |
WO2017214897A1 (en) * | 2016-06-15 | 2017-12-21 | 深圳市锐明技术股份有限公司 | Electromagnetic interference protection circuit for memory, and vehicle-mounted electronic device |
CN107871482A (en) * | 2017-10-26 | 2018-04-03 | 惠科股份有限公司 | Display device and driving circuit and driving method thereof |
CN109272956A (en) * | 2018-11-06 | 2019-01-25 | 惠科股份有限公司 | Protection circuit of memory cell in display panel and display device |
CN109634892A (en) * | 2018-11-09 | 2019-04-16 | 惠科股份有限公司 | Data protection system and protection method of display device |
US10431173B2 (en) | 2017-10-26 | 2019-10-01 | HKC Corporation Limited | Display apparatus, and circuit and method for driving display apparatus |
WO2020052055A1 (en) * | 2018-09-14 | 2020-03-19 | 惠科股份有限公司 | Memory writing protection circuit and display device |
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2007
- 2007-11-16 CN CNU2007201573896U patent/CN201117293Y/en not_active Expired - Fee Related
Cited By (15)
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CN104751814A (en) * | 2013-12-31 | 2015-07-01 | 乐金显示有限公司 | Memory protection circuit and liquid crystal display device including same |
US20150187427A1 (en) * | 2013-12-31 | 2015-07-02 | Lg Display Co., Ltd. | Memory protection circuit and liquid crystal display including same |
US10262742B2 (en) * | 2013-12-31 | 2019-04-16 | Lg Display Co., Ltd. | Memory protection circuit and liquid crystal display including same |
CN109166539A (en) * | 2013-12-31 | 2019-01-08 | 乐金显示有限公司 | Memory protection circuit and liquid crystal display including the memory protection circuit |
WO2017214897A1 (en) * | 2016-06-15 | 2017-12-21 | 深圳市锐明技术股份有限公司 | Electromagnetic interference protection circuit for memory, and vehicle-mounted electronic device |
CN107871482B (en) * | 2017-10-26 | 2019-04-05 | 惠科股份有限公司 | Display device and driving circuit and driving method thereof |
CN107871482A (en) * | 2017-10-26 | 2018-04-03 | 惠科股份有限公司 | Display device and driving circuit and driving method thereof |
WO2019080332A1 (en) * | 2017-10-26 | 2019-05-02 | 惠科股份有限公司 | Display device, driving circuit thereof and driving method therefor |
US10431173B2 (en) | 2017-10-26 | 2019-10-01 | HKC Corporation Limited | Display apparatus, and circuit and method for driving display apparatus |
WO2020052055A1 (en) * | 2018-09-14 | 2020-03-19 | 惠科股份有限公司 | Memory writing protection circuit and display device |
US11386943B2 (en) | 2018-09-14 | 2022-07-12 | HKC Corporation Limited | Write protection circuit for memory and display apparatus |
CN109272956A (en) * | 2018-11-06 | 2019-01-25 | 惠科股份有限公司 | Protection circuit of memory cell in display panel and display device |
US11514960B2 (en) | 2018-11-06 | 2022-11-29 | HKC Corporation Limited | Protection circuit of memory in display panel and display apparatus |
CN109634892A (en) * | 2018-11-09 | 2019-04-16 | 惠科股份有限公司 | Data protection system and protection method of display device |
CN109634892B (en) * | 2018-11-09 | 2022-05-17 | 惠科股份有限公司 | Data protection system and protection method of display device |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080917 Termination date: 20111116 |