CN1992517A - Programmable interpolated filter device and realizing method therefor - Google Patents
Programmable interpolated filter device and realizing method therefor Download PDFInfo
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Abstract
This invention discloses a programmable interpolation filter device and its implementation method, the said device including: an input data generation module, a coefficient generation module, a calculation module and an output module; the said input data module is used to store the input sample data in the data RAM, and provide to the calculation module to process; the said coefficient module is used to address, and generate the coefficient to the said calculation module; the said calculation module is used to complete the multiply-add operation of the interpolation filter; the said output module is used to extract the interpolation data according to the set extraction multiple, and generate the required sampling rate output data. As the device and its implementation method of the invention, since it is based on the RAM design, and using the pipeline and TDM technologies, significant saving hardware resources, when applied to the digital front-end system of the communication system, it can improve the system performance and design flexibility.
Description
Technical field
The present invention relates to the apparatus and method in a kind of integrated circuit (IC) design field, FPGA design field and the communications field, specifically, relate to a kind of when being used for software radio digital front-end signal processing based on the VLSI of the programmable interpolated filter of RAM and the apparatus and method of FPGA design.
Background technology
Growing along with integrated circuit technique, in wireless communication technology, the scope that numeral (or software) is handled is constantly moved to radio frequency part, can only progressively realize with the function that analog circuit is realized before making with digital circuit or software, thereby software radio (Software Defined Radio, SDR) this new branch of science branch have been produced.Adopt software and radio technique, can in multiple communication standard, switch neatly under the situation that does not change hardware platform, have the incomparable superior function of analogue technique simultaneously.
Interpolation filter has a wide range of applications in the digital front-end of communication system, and its effect is according to the actual needs, and with the sample frequency raising several times of data, the mirror image that filtering simultaneously brings owing to the sample frequency that improves data disturbs.
The principle of the integral multiple interpolation filter of prior art is as follows:
If sample rate originally is f
s, the cycle is T, if sample rate is increased to L doubly, so new sample rate f
S1With sampling period T
1Be respectively:
f
s1＝Lf
s，T
1＝1/f
s1＝T/L
The sample rate of sampled signal x (n) is increased to original L doubly means and between per two sample values of x (n), to insert L-1 new sampled value, so the process that sampled value increases is exactly the process of interpolation on mathematics.
Present existing interpolation filter mainly is fixed coefficient, the fixing filter of interpolation multiple, and the method for realization mainly contains two kinds, the one, directly insert L-1 0 value in each input data back, and operate in Lf with one
sFinite impulse response FIR filter on the sample frequency realizes that this FIR filter can be direct type or transposition type, and the concrete structure prior art has had lot of documents to describe, and does not repeat them here; The 2nd, realize with multiphase filter, do not insert 0 value in each input data back, but whole interpolation filter is resolved into the L phase, whenever produce an output mutually.
When having fixed coefficient and interpolation multiple, more than two kinds of structures implement still very easily, but can take bigger hardware resource, especially more unfavorable when filter order is higher, and also the flexibility that software radio is emphasized can't embody in the prior art.
Therefore, also there is defective in prior art, and awaits improving and development.
Summary of the invention
The object of the present invention is to provide a kind of programmable interpolated filter device and its implementation, at above-mentioned the deficiencies in the prior art, be kept at separately among a certain size the RAM by coefficient sampled data and filter, thereby the coefficient numerical value of the exponent number of flexibly changing interpolation multiple, filter and adjustment filter, adopt streamline and time-division multiplex technology simultaneously, can significantly reduce shared hardware resource.
Technical scheme of the present invention comprises:
A kind of programmable interpolated filter device, wherein, described device comprises:
One input data generation unit, a coefficient generating unit, a computing unit and an output unit;
Described input data cell is used for the sampled data of input is kept at data RAM, and offers the computing unit processing;
Described coefficient elements is used for addressing, produces coefficient and gives described computing unit;
Described computing unit is used to finish the multiply-add operation of interpolation filter;
Described output unit is used for extracting according to the data of the extracting multiple that is provided with to interpolation, produces the dateout of required sample rate.
Described device, wherein, the interpolation of described interpolation filter realizes with multiphase filter, is used to realize the interpolation filtering of different interpolation multiples, different coefficient number and coefficient numerical value.
Described device, wherein, described computing unit comprises the adder and multiplier of at least two same structures, is used to improve the computing capability of this filter, handles the higher filtering of exponent number and calculates.
Described device, wherein, described input data generation unit includes two input dual port RAMs and corresponding input access control logic circuit;
Described input dual port RAM is used for the sampled data of buffer memory from the outside, and each input dual port RAM is divided into the both sides port, and the data that a side is used to receive from the outside realize only writing function, and opposite side then is used for dateout and realizes read-only function;
Described input access control logic circuit comprises a counter, when the sampled data from the outside is saved in the input dual port RAM, with this counter the sampled data number of input is counted, and be written in turn in the described two input dual port RAMs according to the numerical value branch odd even of counter;
Described input access control logic circuit also comprises a treatment circuit of having write flag bit, is used to show whether this was composed the numerical value of determining.
Described device, wherein, described coefficient generating unit includes two coefficient dual port RAMs and coefficient access control logic circuit;
Described coefficient dual port RAM is used to deposit coefficient, and two adder and multipliers of described computing unit are delivered in its output respectively; Each coefficient dual port RAM comprises the both sides port, and the outside is configured by the coefficient of a side ports to this interpolation filter; The opposite side port has only read operation by this interpolation filter inter access;
Described coefficient access control logic circuit is read and write control to the visit of two coefficient dual port RAMs.
Described device, wherein, the write sequence of described coefficient is that linearity writes, and promptly writes from small to large according to the address; The order of reading of described coefficient is a two dimension, earlier from left to right, and more from top to bottom.
Described device, wherein, described computing unit also comprises adder, streamline control logic circuit;
Described adder and multiplier comprises multiplier and accumulator, and described multiplier is used to finish multiplying each other of data and coefficient, two adder and multiplier parallel computations;
Described adder is used for the result of calculation addition with two adder and multipliers, produces an effective output valve, simultaneously will be with these two accumulator zero clearings;
Described streamline control logic circuit makes described computing unit realize pile line operation, be used in each clock cycle, with the coefficient and the data of one group of correspondence of input,, realize pile line operation by register in the control logic of streamline and relevant beat count device.
Described device, wherein, described output unit comprises extraction logical circuit and output control logic circuit;
Described extraction logical circuit is used to finish prearranged multiple and extracts, after each adder and multiplier has been finished half time computing, interpolation filter is produced a control signal, output unit responds this control signal, and, in every multiple data, get an output according to extracting multiple;
Described output control logic circuit is used for producing appropriate control signals when extracting logical circuit generation output, tells the external world that new data output is arranged.
A kind of implementation method of programmable interpolated filter device, based on RAM, it may further comprise the steps:
A, finish every coefficient number mutually of configuration interpolation multiple, extracting multiple and multiphase filter, and coefficient number is written in two coefficient dual port RAMs;
B, 1 data of input, the address initial value pointer of one of described input dual port RAM adds 1, and these data are saved in this input dual port RAM, and the content in another input dual port RAM remains unchanged, and address initial value pointer also remains unchanged;
C, from one of coefficient dual port RAM, take out coefficient, the address pointer of this coefficient dual port RAM adds the interpolation multiple, take out the computing unit that data deliver to one of adder and multiplier and carry out multiply-add operation from one of described input dual port RAM, the address pointer of described input dual port RAM subtracts one;
D, from another coefficient dual port RAM, take out coefficient, the address pointer of this another coefficient dual port RAM adds the interpolation multiple, corresponding take out another adder and multiplier that data deliver to computing unit carry out multiply-add operation from another input dual port RAM, the address pointer of this another input dual port RAM subtracts one;
E, repeating step C, D number of step are no more than half of coefficient number;
F, the accumulation result output that two adder and multipliers are calculated produce control signal notice output unit, and to this accumulator zero clearing.
Described method, wherein, in the described step F, described output unit determines whether to export this value according to the extracting multiple value, if the data number of described computing unit output does not reach the interpolation multiple, then continues repeating step C to step F.
Described method wherein, also comprises:
When if G has new data input again, then be used alternatingly two input dual port RAMs, two coefficient dual port RAMs.
A kind of programmable interpolated filter device provided by the present invention and its implementation, compared with prior art, owing to be based on the design of RAM, and streamline and time-division multiplex technology have been adopted, saved hardware resource greatly, also can make the clock frequency of chip operation surpass 100MHz, reached more than the 150MHz, in the digital front-end system that is applied to communication system, can improve the performance of system and the flexibility of design.
Description of drawings
Fig. 1 is the composition structural representation of programmable interpolated filter of the present invention;
Fig. 2 is the coefficient two-dimensional matrix schematic diagram of the inventive method;
Fig. 3 is the computing unit structural representation of apparatus of the present invention and method.
Embodiment
Below in conjunction with accompanying drawing, will carry out comparatively detailed explanation to each preferred embodiment of the present invention.
The core idea of the inventive method is that in interpolation filter, establishing L is the interpolation multiple, M is an extracting multiple, if L＞M, and mark L/M can not reduce, then this filter can conveniently be realized L/M times of interpolation, thereby realizes integral multiple and greater than 1 decimal times interpolation filtering.
The operating procedure of programmable interpolated filter device of the present invention comprises:
This programmable interpolation filter is finished L times of interpolation earlier, finishes M again and doubly extracts.L times of interpolation realizes interpolation with multiphase filter, an every output, L phase altogether of producing mutually.It is to extract data as output from M data that M doubly extracts.
This interpolation filter comprises 4 parts, is respectively input data generation unit, coefficient generating unit, computing unit and output unit, as shown in Figure 1.Wherein, described input data generation unit is kept at the sampled data of input in the data RAM, and offers the computing unit processing; Described coefficient generating unit correct addressing produces coefficient and gives described computing unit; Computing unit is finished the multiply-add operation of interpolation filter, it is made up of the adder and multiplier (MAC) of two same structures, is MAC1 and MAC2 respectively, why uses two MAC unit, mainly be for improving the computing capability of this filter, can handling the higher filtering of exponent number and calculate.If obtain bigger computing capability, only the number simple extension of MAC need be got final product; Described output unit extracts (not extracting when the M=1) according to the extracting multiple M that is provided with to the data of interpolation, produces the dateout of required sample rate.
The L of this interpolation filter times of interpolation adopts multiphase filter to realize, but can realize the interpolation filtering of different interpolation multiples, different coefficient number and coefficient numerical value.
Described input data generation unit is for computing unit provides the input data, and it includes two input dual port RAMs and input access control logic circuit.
The input dual port RAM is used for the sampled data of buffer memory from the outside, is designated as DRAM1 and DRAM2 respectively.Be divided into PORTA, PORTB both sides at each DRAM, the PORTA side joint is received the data (only writing) from the outside, PORTB side dateout (read-only).
Described input access control logic circuit comprises a counter, when the sampled data from the outside is saved in DRAM, with counter the sampled data number of input is counted.Numerical value branch odd even according to counter is written among these two DRAM DRAM2 behind the first DRAM1 in turn then.The input data of MAC1 and MAC2 are taken from the PORTB side of DRAM, and each clock cycle is got one.
Described input access control logic circuit also comprises the treatment circuit of a dirty flag bit.Because be to realize preservation to data with RAM, the initial value behind this circuit electrification reset among the RAM is uncertain, and therefore needing to give each memory cell to increase by one, to have write flag bit be dirty, shows whether this was composed the numerical value of determining.Its initial value is 0, when reading certain memory cell, also to read this dirty flag bit, if be 0, then showing in the corresponding memory cell does not have determined value, sends 0 value then for corresponding M AC, otherwise sends this memory cell numerical value, when writing this memory cell, simultaneously with corresponding dirty mark position 1.
Coefficient generating unit of the present invention is used to computing unit that coefficient is provided, and it includes two coefficient dual port RAMs and coefficient access control logic circuit.Two coefficient dual port RAMs in the described coefficient generating unit are used for depositing coefficient, are designated as CRAM1 and CRAM2 respectively, and the MAC1 and the MAC2 of computing unit delivered in its output respectively.Each CRAM is divided into PORTA, PORTB both sides, and outside PORTA by CRAM is configured the coefficient of this filter; PORTB is by the filter inter access, has only read operation.
Described coefficient access control logic circuit is controlled the visit of CRAM1 and CRAM2.Write operation to CRAM1 and CRAM2 is fairly simple, before interpolation filter brings into operation coefficient is written to CRAM1 and CRAM2 gets final product, and coefficient is relative wants complicated and will take out from CRAM1 and CRAM2.
Reading of described coefficient is based on following principle: because this interpolation filter is to realize many times of interpolations with multiphase filter, suppose that multiple is L, therefore this multiphase filter has the L phase, every have N coefficient mutually, therefore the coefficient of this multiphase filter can make up two-dimensional coefficient matrix, the line number L of this matrix promptly is the multiple of interpolation, columns can be regarded the coefficient number of every phase as, the coefficient of every phase has N, then the overall coefficient number of this multiphase filter is L * N, promptly constitute the matrix of L * N, the two-dimensional matrix of coefficient of the present invention is seen shown in Figure 2, and wherein dash area and non-shaded portion coefficient are kept at respectively among CRAM2 and the CRAM1.
When the PORTB of apparatus of the present invention and method side-draw went out coefficient, the order of going into the PORTA sidelights on was different, and the order of going at the PORTA sidelights on is that linearity writes, and promptly writes from small to large according to the address.And the order that the PORTB side is read is two-dimentional, according to shown in Figure 2, it is from left to right (to read according to the k value) earlier that coefficient is read order, (read) more from top to bottom, promptly whenever sampled data input is arranged, when starting the filter computing according to the m value, elder generation is from first element (element 0) of first row of matrix, from left to right got first row, gone to begin to be still from second of matrix again and from left to right got second row, the rest may be inferred.
According to different L and N value, can produce different two-dimensional coefficient matrix, thereby realize L times of interpolation in the programmable interpolated filter of different interpolation multiples and coefficient number.
Computing unit of the present invention is to be used for the data from DRAM and CRAM are multiplied each other, and adds up with accumulated value that the MAC of previous clock cycle calculates.This computing unit is made up of two MAC (adder and multiplier) unit, adder, streamline control logic circuit and some other control logic circuits.
Described multiplier accumulator unit MAC is made up of multiplier and accumulator, and multiplier is finished multiplying each other of data and coefficient, and data and coefficient all are signed numbers, and multiplied result also is a signed number.Each MAC structure is identical, parallel computation.As previously described, the coefficient number of every phase is N, and this illustrates that each output will pass through N MAC (take advantage of and add) computing.
Adder is used for the result of calculation addition of MAC.When each MAC is added to N/2 time, because two MAC computing is simultaneously arranged, just respectively ask for different data and coefficient, but two MAC add up and want computing N time, with the output of the accumulator of two MAC by the adder addition, to produce an effective output valve, simultaneously will be with these two accumulator zero clearings.
Described streamline control logic circuit makes the MAC computing unit realize pile line operation, in each clock cycle, coefficient and data with one group of correspondence of input by register in the control logic of streamline and relevant beat count device, thereby have realized pile line operation.
When the coefficient number N of every phase of multiphase filter is odd number, MAC2 will lack computing once than MAC1, and will will compose the coefficient value of delivering to MAC2 this moment is 0 value, and two MAC unit still calculate simultaneously, just the computing of MAC2 does not have actual use, can reduce the complexity of design like this.
Output unit of the present invention comprises extraction logical circuit and output control logic circuit.Described extraction logical circuit is used to finish M and doubly extracts, after N/2 computing finished in each MAC unit, interpolation filter is produced a control signal, output unit responds this control signal, and, in every M data, get 1 output according to extracting multiple (M value).
When extracting logical circuit generation output, produce appropriate control signals with the output control logic circuit, tell the external world that new data output is arranged.
Programmable interpolated filter implementation method of the present invention is based on RAM, and its specific implementation step comprises:
A, finish every N of coefficient number mutually of configuration interpolation multiple L, extracting multiple M and multiphase filter, and coefficient is written among CRAM1 and the CRAM2;
B, 1 data of input, the address initial value pointer of DRAM1 adds 1, and these data will be saved among the DRAM1, and the content among the DRAM2 remains unchanged, and address initial value pointer also remains unchanged;
C, take out coefficient from CRAM1, the address pointer of CRAM1 adds L.Take out data and deliver to the MAC1 computing unit and carry out multiply-add operation from DRAM1, the address pointer of DRAM1 subtracts one (cyclic addressing);
D, take out coefficient from CRAM2, the address pointer of CRAM2 adds L.Take out data and deliver to the MAC2 computing unit and carry out multiply-add operation from DRAM2, the address pointer of DRAM2 subtracts one (cyclic addressing);
If the number of times that E step C, D repeat less than N/2 time, then continues to repeat this two step, otherwise enters step F;
F, the accumulation result output that two MAC unit are calculated produce control signal notice output unit, and to this accumulator zero clearing.Described output unit determines whether to export this value according to the M value.If the data number of computing unit output does not reach L, then continue repeating step C to step F, otherwise enter step G;
If G has new data input, then the similar step B of processing procedure is to step F, different is in step B, the address pointer initial value of DRAM2 increases one, writes data among the DRAM2, and the address initial value pointer of DRAM1 still keeps initial value, simultaneously with the output of DRAM1 and the output multiplication of CRAM2, so hocket,, then wait for if there are not new data.
The time division multiplexing of the programmable interpolated filter of the inventive method shows two aspects:
The one, the time division multiplexing of every phase of multiphase filter, for L interpolation filtering doubly, realize then total L phase with multiphase filter, and when this L phase computing of specific implementation, finish with a computing unit, every calculating intact one is mutually and after exporting data, will take out new one group of coefficient and input sampling data, calculate a new phase, repeat L time altogether;
The 2nd, computing unit is finished multiply-add operation N time with 2 MAC, and wherein N is every phase coefficient number of multiphase filter, and wherein each MAC unit carries out N/2 computing.
Through top twice time division multiplexing, all L of the inventive method * N time multiply-add operation is only taken advantage of with two and is added computing unit (MAC1 and MAC2) and finish, but prerequisite be the operation clock frequency of interpolation filter be the input data sample frequency T * N/2 doubly, therefore, will use pipelining again is operated on the higher clock frequency this filter.
Realization as shown in Figure 1 a programmable interpolated filter of the inventive method, when realizing previously described programmable interpolated filter, the degree of depth of data RAM can be made as 32, because two MAC computing units are arranged, then every phase coefficient number maximum of multiphase filter can be made as 64 (32 * 2).Coefficients R AM (CRAM) reality can be made as 256 with its total depth when using, and each CRAM degree of depth is 128, according to the difference of interpolation multiple, realizes different two-dimensional coefficient matrix.Limiting L is 16, and the M value also is defined as 16, then interpolation multiple 1≤L/M≤16 of this filter.Therefore, the interpolation filter maximum number of taps is 256, promptly finishes the calculating of 255 rank interpolation filters with two MAC computing units.
In the apparatus of the present invention that describe below and the preferred embodiment of method, described programmable interpolation filter is used for cdma base station, down link baseband signal (intermediate frequency relatively) is carried out up-conversion, the signal sampling frequency of input is upconverted to 4.9152MHz by 4 times of interpolations of 1.2288MHz by this interpolation filter, every phase coefficient number N is 20, therefore total tap number of this interpolation filter is 80 (20 * 4), and the clock frequency of filter is 49.152MHz, then means:
Every phase coefficient number N=20 of described multiphase filter, interpolation multiple L=4, extracting multiple M=1;
Data of per 40 clock cycle input;
Per 10 clock cycle interpolation filters will produce an output;
Each output will be through the calculating of 20 MAC unit;
Each MAC calculates 10 times.
If think that clock frequency is too high, can increase the quantity of MAC unit, increase to 4 such as MAC, clock frequency drop by half then, the structure of this interpolation filter can be expanded easily.
According to shown in Figure 2, the coefficient matrix of the inventive method is distributed, then be 4 * 20 matrix this moment, the 1st, 3,5 ... 19 row are assigned among the CRAM1, the 2nd, 4,6 ... 20 row are assigned among the CRAM2.
When having data to be input to programmable interpolated filter at every turn, will import a data_valid index signal, the notice interpolation filter receives data; And interpolation filter output the time also will produce a similar data_valid signal, and showing has the result to export from interpolation filter.
Computing unit realizes according to structure shown in Figure 3, and the MAC of computing unit realizes with the level Four streamline, the bat of advancing of each clock cycle streamline.When input data when appearing at the input of computing unit, will postpone 4 clock cycle after, result of calculation is kept in the accumulator.When finished add up for 10 times after, the content of accumulator is delivered to addition in the adder, the result that addition obtains promptly is one of computing unit output result, the content of accumulator will be emptied simultaneously.Register as shown in Figure 3 plays the effect that beat is divided, and total level Four is handled:
The 1st grade, finish the computing that takes absolute value of coefficient and data, and extract sign bit;
The 2nd grade, finish signless multiplying;
3rd level converts the product that obtains to signed number;
The 4th grade, finish accumulating operation.
Wherein, CRAM1 is corresponding with MAC1, and CRAM2 is corresponding with MAC2, and corresponding relation is fixed.This moment, parameter N was an even number, and MAC1 is identical with the MAC2 operation times, is 10 times.Owing to M=1 this moment, what finish is the integral multiple interpolation, no extraction operation, and output unit directly will output to the outside of interpolation filter from the result of computing unit.
Programmable interpolated filter device of the present invention and its implementation, compared with prior art, owing to be based on the design of RAM, and streamline and time-division multiplex technology have been adopted, saved hardware resource greatly, also can make the clock frequency of chip operation surpass 100MHz, reached more than the 150MHz, in the digital front-end system that is applied to communication system, can improve the performance of system and the flexibility of design.
Should be understood that above-mentioned description at specific embodiment is comparatively detailed, can not therefore be interpreted as the restriction of scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (11)
1, a kind of programmable interpolated filter device is characterized in that, described device comprises:
One input data generation unit, a coefficient generating unit, a computing unit and an output unit;
Described input data cell is used for the sampled data of input is kept at data RAM, and offers the computing unit processing;
Described coefficient elements is used for addressing, produces coefficient and gives described computing unit;
Described computing unit is used to finish the multiply-add operation of interpolation filter;
Described output unit is used for extracting according to the data of the extracting multiple that is provided with to interpolation, produces the dateout of required sample rate.
2, device according to claim 1 is characterized in that, the interpolation of described interpolation filter realizes with multiphase filter, is used to realize the interpolation filtering of different interpolation multiples, different coefficient number and coefficient numerical value.
3, device according to claim 2 is characterized in that, described computing unit comprises the adder and multiplier of at least two same structures, is used to improve the computing capability of this filter, handles the higher filtering of exponent number and calculates.
4, device according to claim 3 is characterized in that, described input data generation unit includes two input dual port RAMs and corresponding input access control logic circuit;
Described input dual port RAM is used for the sampled data of buffer memory from the outside, and each input dual port RAM is divided into the both sides port, and the data that a side is used to receive from the outside realize only writing function, and opposite side then is used for dateout and realizes read-only function;
Described input access control logic circuit comprises a counter, when the sampled data from the outside is saved in the input dual port RAM, with this counter the sampled data number of input is counted, and be written in turn in the described two input dual port RAMs according to the numerical value branch odd even of counter;
Described input access control logic circuit also comprises a treatment circuit of having write flag bit, is used to show whether this was composed the numerical value of determining.
5, device according to claim 4 is characterized in that, described coefficient generating unit includes two coefficient dual port RAMs and coefficient access control logic circuit;
Described coefficient dual port RAM is used to deposit coefficient, and two adder and multipliers of described computing unit are delivered in its output respectively; Each coefficient dual port RAM comprises the both sides port, and the outside is configured by the coefficient of a side ports to this interpolation filter; The opposite side port has only read operation by this interpolation filter inter access;
Described coefficient access control logic circuit is read and write control to the visit of two coefficient dual port RAMs.
6, device according to claim 5 is characterized in that, the write sequence of described coefficient is that linearity writes, and promptly writes from small to large according to the address; The order of reading of described coefficient is a two dimension, earlier from left to right, and more from top to bottom.
7, device according to claim 6 is characterized in that, described computing unit also comprises adder, streamline control logic circuit;
Described adder and multiplier comprises multiplier and accumulator, and described multiplier is used to finish multiplying each other of data and coefficient, two adder and multiplier parallel computations;
Described adder is used for the result of calculation addition with two adder and multipliers, produces an effective output valve, simultaneously will be with these two accumulator zero clearings;
Described streamline control logic circuit makes described computing unit realize pile line operation, be used in each clock cycle, with the coefficient and the data of one group of correspondence of input,, realize pile line operation by register in the control logic of streamline and relevant beat count device.
8, device according to claim 7 is characterized in that, described output unit comprises extraction logical circuit and output control logic circuit;
Described extraction logical circuit is used to finish prearranged multiple and extracts, after each adder and multiplier has been finished half time computing, interpolation filter is produced a control signal, output unit responds this control signal, and, in every multiple data, get an output according to extracting multiple;
Described output control logic circuit is used for producing appropriate control signals when extracting logical circuit generation output, tells the external world that new data output is arranged.
9, a kind of implementation method of programmable interpolated filter device, based on RAM, it may further comprise the steps:
A, finish every coefficient number mutually of configuration interpolation multiple, extracting multiple and multiphase filter, and coefficient number is written in two coefficient dual port RAMs;
B, 1 data of input, the address initial value pointer of one of described input dual port RAM adds 1, and these data are saved in this input dual port RAM, and the content in another input dual port RAM remains unchanged, and address initial value pointer also remains unchanged;
C, from one of coefficient dual port RAM, take out coefficient, the address pointer of this coefficient dual port RAM adds the interpolation multiple, take out the computing unit that data deliver to one of adder and multiplier and carry out multiply-add operation from one of described input dual port RAM, the address pointer of described input dual port RAM subtracts one;
D, from another coefficient dual port RAM, take out coefficient, the address pointer of this another coefficient dual port RAM adds the interpolation multiple, corresponding take out another adder and multiplier that data deliver to computing unit carry out multiply-add operation from another input dual port RAM, the address pointer of this another input dual port RAM subtracts one;
E, repeating step C, D number of step are no more than half of coefficient number;
F, the accumulation result output that two adder and multipliers are calculated produce control signal notice output unit, and to this accumulator zero clearing.
10, method according to claim 9, it is characterized in that in the described step F, described output unit determines whether to export this value according to the extracting multiple value, if the data number of described computing unit output does not reach the interpolation multiple, then continue repeating step C to step F.
11, method according to claim 10 is characterized in that, also comprises:
When if G has new data input again, then be used alternatingly two input dual port RAMs, two coefficient dual port RAMs.
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| CN101958697A (en) * | 2010-09-30 | 2011-01-26 | 电子科技大学 | Realization method and device of multiphase filter structure |
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| CN111865311B (en) * | 2020-07-27 | 2024-04-09 | 中国电子科技集团公司第三十六研究所 | Variable-modulus decimal frequency conversion parallel signal processing device and method |
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