CN1967838A - A package having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuitry and methods of forming thereof - Google Patents
A package having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuitry and methods of forming thereof Download PDFInfo
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- CN1967838A CN1967838A CN 200610136568 CN200610136568A CN1967838A CN 1967838 A CN1967838 A CN 1967838A CN 200610136568 CN200610136568 CN 200610136568 CN 200610136568 A CN200610136568 A CN 200610136568A CN 1967838 A CN1967838 A CN 1967838A
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Abstract
One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.
Description
Technical field
The present invention relates to design, layout and the structure of electronic integrated circuit (IC) encapsulation, described integrated circuit encapsulation has been showed by making of embedded capacitor layer array and is used for driving the ability that energy delivery and decoupling are provided for high speed I/O (I/O).
Background technology
The present invention relates to the decoupling capacitor field.Decoupling capacitor in the IC encapsulation is moving to reducing the voltage volt, electric charge is provided and keeps the integrality of power distribution normally necessary.Surface mounting technology (SMT) decoupling capacitor since its high lead inductance at the hundreds of megahertz can not provide decoupling under the upper frequency.Capacitor on the sheet is because its low electric capacity is only effective in gigahertz frequencies.
One of main bottleneck of launching high speed signal by transmission line is the control return current.As long as there is the loop to interrupt anyplace, the noise on power supply/grounding system will be coupled on the transmission line.On the contrary, be coupled to any electric current of power supply/grounding system and all can cause power-supply fluctuation.Interrupt in loop (return path) is a main noise source, such as the functional ground bounce that influences IC, and electromagnetic interference.Take place to interrupt mainly is owing to pass the transmission line that signal path, process discrete power layer and switch I/O of power supply/ground plane drive.Decoupling capacitor is for power management and thereby to handle the coupling that return current reduces between signal transmission and the energy distribution system be necessary.They only are set near the loop interruptions and are only effectively.Therefore, surface mounting technology (SMT) decoupling capacitor on encapsulation or the plate since its high lead inductance more than the hundreds of hertz, can not drive and receiver provides decoupling for I/O.Central point of the present invention is to use embedded capacitor so that I/O decoupling and power supply to be provided in encapsulation.Array of embedded capacitors constitutes by use the thin dielectric of high dielectric constant in the layer laminate of encapsulation.
The bit rate of I/O line is improving to provide higher digital bandwidth to be used for processor and communicating by letter such as memory chip.Therefore, decoupling I/O line is just becoming a serious problem.
The invention provides the package level solution of a kind of IC of being used in electric charge supply (energy delivery) and decoupling.It has overcome some inductance problem of plate decoupling method and has saved the space on the chip by reducing required size that goes up electric capacity, thereby by reducing power supply noise and the sufficient current that satisfies semiconductor switch speed needs be provided with lower cost, especially high electric current I/O (I/O) driver has improved the performance of numeral and mixed-signal system.The invention provides can be in capacitor and encapsulation that low resistance power supply/grounding system is provided near I/O driving place under high-frequency very.
Summary of the invention
One embodiment of the present of invention provide a kind of being used for to provide the low noise power supply packaged device to integrated circuit, comprise: semiconductor element, the I/O power terminal, and the embedded ceramic capacitors array that is selected from discrete, the plane or its combination, the position that wherein said capacitor is placed is selected within the circumference of shade of semiconductor element, part is within the circumference of the shade of semiconductor element, near the circumference of the shade of semiconductor element, and combination.Another embodiment of the present invention provides a kind of being used for to provide the low noise power supply packaged device to IC, comprise and use embedded discrete ceramic capacitor array, so that the impedance of array of capacitors is arranged the curve of frequency produces low impedance value in electric current supply and current circuit mode with different resonance frequencys.
Another embodiment provides a kind of method that is used for the design optimization array of capacitors, may further comprise the steps: (a) make up integrated circuit packaging and testing structure, wherein said structure comprises the I/O power terminal and is selected from discrete, the embedded ceramic capacitors array plane or its combination, the position that wherein said capacitor is placed is selected within the circumference of shade of semiconductor element, part is within the circumference of the shade of semiconductor element, near the tube core, and combination, and wherein said structure comprises different capacitor design, size, path is interconnected and interconnected; (b) test they separately electric capacity, resistance and inductance value and resistance value with respect to the response of frequency; (c) composite impedance to various array of capacitors carries out modeling to satisfy the impedance target with respect to the response of frequency; And (d) Computer-Assisted Design, Manufacture And Test based on the structure of modeling result.
The present invention also provides optimization array of capacitors that constitutes with said method and the device that comprises this optimization array of capacitors.
Description of drawings
Fig. 1 has described the stacked of test structure.
Fig. 2 has described the test carrier stepped construction.
Fig. 3 has described the capacitor pattern on metal level (150) and (800).
Fig. 4 A, 4B and 4C have described capacitor type A.
Fig. 5 A, 5B, 5C have described capacitor type B.
Fig. 6 A, 6B, 6C have described capacitor type C.
Fig. 7 shows does not have the capacitor parameters of path table.
Fig. 8 shows aisled capacitor parameters table.
Fig. 9 A and 9B have drawn the test result that has path and do not have path.
Figure 10 A and 10B are the diagrammatic sketch of the related model of the test of capacitor 4 and 7.
Figure 11 A, 11B are the planar capacitor legends.
Figure 12 is the diagrammatic sketch to planar capacitor frequency response modeling.
Figure 13 shows the target impedance of array of capacitors.
Figure 14 shows the target impedance of different capacitors size.
Figure 15 A shows plane capacitance and the discrete electric capacity in the layer laminate that is included in the encapsulation with array of embedded capacitors.
Figure 15 B shows the layout of embedded capacitance array.
Figure 16 shows the simulation model of the transmission line that does not connect.
Figure 17 A and 17B show the contrast of the line eye pattern that is not connected of two kinds of bus plane substrate dielectric constants.
Figure 18 A and 18B show the contrast of the line eye pattern that has been connected of two kinds of bus plane substrate dielectric constants.
Figure 19 has described to illustrate the simulation model of transmission line of connection of the position of the position of decoupling capacitor and simultaneous switching noise (SSN) response.
Figure 20 shows discrete I/O decoupling capacitor, and I/O drives and the position of transmission line in simulation model.
Figure 21 A and 21B show simultaneous switching noise (SSN) response at two smooth bus plane substrate dielectric constant lower surface mounting technique (SMT) discrete capacitors and embedded capacitor.
Figure 22 shows decoupling capacitor position with respect to signal transmssion line in simulation model.
It is the response of SSN under 3.8 the situation that Figure 23 A, 23B and 23C show at a plurality of SMT discrete capacitors and flat substrate dielectric constant.
Figure 24 has carefully stated has tube core, I/O, and the plane graph of the encapsulation of core logic area.
Figure 25 represents the viewgraph of cross-section of tube core indication " die shadow ", in the encapsulation.
Embodiment
Central point of the present invention is to use the embedded capacitance array in the electronics IC encapsulating structure to supply with and clean energy delivery to drive the electric charge that provides sufficient to the high speed I/O.The embedded capacitance array constitutes by use the thin dielectric of high dielectric constant in the lamination of encapsulation.
In order to overcome aforementioned I/O decoupling problem, decoupling capacitor must drive near I/O as much as possible and place.This has guaranteed that the circulation inductance that is produced by signal code and return current thereof is lower, thereby makes less noise be injected into power supply/grounding system.SMT capacitor on the plate lost efficacy under high frequency owing to its high lead inductance.The sheet that can add powers on to hold and is limited to space on the sheet.The increase of decoupling capacitor quantity will increase the cost and the size of chip on the sheet.Therefore, the embedded capacitor in the encapsulation provides best decoupling method for I/O drives.
Except the behavior of I/O switch driven, signal path has also caused the loop interruption.Must be continuously by the return current on the reference planes of two continuous transmission lines of path.Otherwise the current circuit interruption can cause power supply/ground noise.Especially synchro switch drives and can cause the much noise that is called simultaneous switching noise (SSN).In one embodiment of the invention, embedded capacitor is placed so that the best mode of control return current to be provided near path as much as possible.
Be used for embedded capacitor in the encapsulation of I/O decoupling and both can be at least and the same big planar capacitor of encapsulation, also can form by the capacitor of the smaller szie of parallel connection.Two kinds of capacitor types all help to improve signal integrity.
The invention provides a kind of solution that is used for the High Speed I/O decoupling of package level.The inductance problem that it is learned by the plate decoupling method that provides the low impedance current loop to overcome to be used for high speed signal.
A kind of embodiment of the present invention provides a kind of being used for to provide the low noise power supply packaged device to IC, is included in the described encapsulation installation embedded ceramic capacitors array is installed.
Another embodiment of the present invention uses array of embedded capacitors so that clean energy delivery encapsulation to be provided.In one embodiment, array of embedded capacitors constitutes by use the thin dielectric of high dielectric constant in the layer laminate of encapsulation.In another embodiment, array of embedded capacitors is by being selected from thick film, and the technology in film and the combination thereof constitutes.Array of embedded capacitors can be in parallel or in the single connection in other positions, and can be made up of the capacitor with different resonance frequencys and different size and shape.
Fig. 1 shows the encapsulation cross section with embedded capacitor layer.Array of capacitors can be by discrete capacitor, planar capacitor, or the combination of discrete and planar capacitor constitutes.Fig. 2 shows the array of embedded capacitors layout in the encapsulation.The capacitor of different size has been formed this array.At this, array is defined as the grouping or the arrangement of element.In the present invention, the element of array is a capacitor, and discrete capacitor and planar capacitor all can.
The basic principle of using the capacitor of different size be with they in each capacitance that is associated, equivalent series resistance (ESR) and equivalent series inductance are different, it is converted into different resonance frequencys.In order to reach optimum performance, capacitor should be placed by as close as possible I/O power supply.Connect on-chip capacitor and the power supply/path of ground connection solder sphere and also influence the performance of array.By the appropriate collaborative design of path and capacitor, can with required impedance and frequency range as target.In one embodiment, the low target impedance requirement of the capacitor input impedance with the energy delivery network that satisfies chip-scale each other in parallel.The required number of capacitors of the use of particular type can be determined by the series resistance of each capacitor.The parallel connection combination of series resistance should be lower than the target impedance requirement.The capacitor frequency response is highstrung to its position in encapsulation.
Discrete capacitor size is generally from 0.25 millimeter to 5 millimeters.In one embodiment, this scope is 0.5 millimeter to 3 millimeters.Yet, it should be appreciated by those skilled in the art that any thinkable discrete electric capacity size range all is possible.
The position that embedded capacitor in the array is placed is selected within the circumference of shade of semiconductor element, part is within the circumference of the shade of semiconductor element, near the circumference of the shade of semiconductor element, and combination.Array of embedded capacitors can be selected from discrete capacitor, planar capacitor and combination thereof.In one embodiment, it is very important these ESL capacitors can being placed in the I/O district of " die shadow " of processor.In general, the I/O district of die shadow is on the circumference of tube core or near its circumference.In one embodiment, capacitor is as much as possible near the I/O power terminal.In one embodiment, do not recommend these capacitors are placed on the outside of die shadow,, and changes the performance that capacitor is envisioned owing to inductance and resistance increase because this can cause wiring problem.Yet in another embodiment, capacitor can be placed on the place of tube core outside near the die shadow circumference.
" die shadow " is defined herein as the packaging area that is projected under the tube core area of coverage when the top is seen.Typically, a plurality of layers are arranged between array of capacitors and tube core.In certain embodiments, array of capacitors can partly be positioned at outside " die shadow " and enough power supply and couplings still can be provided.Be accompanied by the reduction of supply voltage, the energy consumption that is used for the microprocessor of WeiLai Technology node can increase.This causes the noise margin of mains fluctuations littler.The energy delivery network provides power supply to IC.If design incorrectly, this network can become main noise source, such as influencing the functional ground bounce of IC, and produces electromagnetic interference.In order to reduce mains fluctuations, the amplitude of the input impedance of the energy delivery network of close chip must remain on a very little value.From direct current to the clock frequency and the frequency of the several times of I/O data transfer rate all must keep this Low ESR.Decoupling capacitor plays very big effect in the energy delivery network, because they also serve as the electric charge supplier of I/O switching circuit.They should provide Low ESR, high capacitance, low stray inductance, and low parasitic capacitance.No matter adopt what technology (such as SMT capacitor or the buried capacitor on the plate) on the plate, the inductance of packaging power lead can cause its decoupling to be lost efficacy.Because the installation of capacitor is subject to the space on the sheet on the sheet that can add, this problem can not solve with capacitor on the sheet.This drives and has brought restriction for adopting on the sheet capacitor coupling high-speed I/O that makes a return journey.The increase of decoupling capacitance will increase the cost and the size of chip on the sheet.The embedded capacitance array that encapsulation is inner is because its low stray inductance and resistance and high capacitance can provide sufficient decoupling.SMT capacitor on plate has lower inductance to be because their more close tube core in position or chip.
Device of the present invention (or encapsulation) can be selected from, but is not limited only to, and inserts mechanism (interposer), printed substrate, the system in the system in multichip module, area array package, the encapsulation, the encapsulation, and similar device.
Example
The structure (see figure 1) that comprises the test structure of discrete embedded ceramic capacitors.
BT (Bismaleimide Triazine) prepreg (the B b stage resin b on the glass fabric of three 100 micron thickness of Mitsubishi Gas Chemical, GHPL 830HS) [100] are laminated into two plane capacitance laminations (DuPont Imerra HK11 can buy from E.I.du Pont de Nemours and Company).HK11 is made up of the thick sandwich polyimides of 14 μ m [200] that have the thick Copper Foil [300] of 35 μ m on every side.(note: this test structure is the predecessor of complicated more test body (Fig. 2), Fig. 2 midplane capacitor layer is connected to PTH (plated-through-hole) [750], and extra built-in microporous layers [850] (unshowned metal level M1, M2, M13 and M14 among Fig. 1) is added in this test structure).Go up at two Copper Foils (metal level M4[500] and M10[600]) and to form discrete ceramic capacitor, as United States Patent (USP) the 6th, 317, described in No. 023.This paper tinsel is the thick Copper Foils of 35 μ m, dielectric composition [700,900] be the EP310 of DuPont, can buy from E.I.du Pont de Nemours andCompany (sintering thickness 20 μ m), the copper electrode of silk screen printing be sintering thickness 5 μ m copper (metal level M5[800] and M11[150], the EP320 of DuPont can buy from E.I.du Pont de Nemours and Company).Then metal forming M4 and M10 and 100 μ m BT prepregs are placed on the both sides of the structure that comprises two planar capacitor layers, and lamination.Then, the multilayer adhesive coatings is put on metal level M4 and M10.Then metal level M4 and M10 being building up to (losing lustre) prints and etching is taken a picture in the dull and stereotyped technology.The BT prepreg (100 μ m) [250,350] that will be covered with the Copper Foil [450,650] of 3 μ m then is laminated to the both sides (metal level M3 and M12) of this structure.Get out with the UV laser then and penetrate M3 and M12 and the following blind hole (micropore, diameter 150 μ ms) [550] of prepreg to be connected to metal level M4 and M10.Expand by standard then and (permanganate) etching chemistry and electroless coating copper subsequently deposit and prepares the micropore hole wall.Realize the patterning of copper built-in in metal level M3 and M12 and the micropore by false add (semi-additive) electroplating technology (applying the difference etching of anti-plating pattern, plating 12 μ m copper, antistripping, substrate copper).
The layout of the embedded capacitor on metal level M5 and the M11 as shown in Figure 3.Three different capacitor design: type A (Fig. 4) are arranged, type B (Fig. 5), and Type C (Fig. 6).Each type all has and has 1mm
2, 4mm
2, and 9mm
2The capacitor of effective capacitance size (area).The design of these capacitors is at foil electrode (1200), dielectric (1400), and different on the relevant position of silk screen printing copper electrode (1300) and the size.They are also different in the design in the slit (gap) that isolates two copper electrodes, and connect embedded capacitance and above the number of path (1100) of adjacent metal on different.For 9mm
2The capacitor of size, type A design is connected to feature with 4 paths, and type B has 28 paths, and Type C has 52 paths.
Measured electrical quantity (electric capacity, resistance, inductance) with path connection and each capacitor that does not have path to be connected.Measured of the response of the impedance phase of each capacitor for frequency.The response curve of measuring is compared with the curve that simulation model produces.This model is used to the impedance of a plurality of array of capacitors of emulation then, and described embedded capacitance array adopts conservative and advanced design rule designs.
The result:
Fig. 7 summed up do not have that path connects, be of a size of 1,4 and 9mm
2Type A, B and electric capacity, resistance and the inductance measurement result of C capacitor.Electric capacity and does not change with kind of design as the rising along with size of expection as can be seen.The all types of inductance value that do not have path to connect all are quite approximate.Fig. 8 shows the identical parameters of the capacitor with type A, B that path connects and C.Data show that capacity type and path number and their position greatly affect the resistance and the inductance of capacitor.
The path that has that Fig. 9 shows as numbering among Fig. 7 and 8 is connected example with the response curve of the impedance versus frequency of two kinds of capacitor types that do not have path to be connected.The resonance frequency curve moves with the path connection as can be seen.
Figure 10 shows good correlation between the response curve (dotted line) of the frequency response curve that records (solid line) of two kinds of capacitor types of different size and modeling.
Figure 11 shows the structure of planar capacitor layers.Through hole interconnected (through-hole interconnection) is shown in the vertical view.
Figure 12 shows the emulation of the planar capacitor impedance phase of the planar capacitor that has the contribution of through hole inductance and do not have the contribution of through hole inductance for the response curve of frequency.
Figure 13 shows and adopts minimum spacing between the capacitor is the modeling result of array of 64 discrete embedded capacitances of the conservative design of 500 μ m.Selected the capacitor of different size and different resonance frequencys, so that the array of capacitors response curve produces low impedance value quite uniformly in intermediate frequency range.Horizontal line has been indicated the resistance value that reached and its lower impedance with the 0.7m Ω that obtains from ITRS blue print in 2007 is required to compare in 100MHz to 1GHz scope.
Figure 14 show by the electrode zone of optimum overlapping to 1.15 to 2.5mm
2The array of capacitors of size adopts harsher spacing design rule, has reached target impedance requirement in 2007 in intermediate frequency range.
Figure 15 A has described that planar capacitor layers (1500), discrete capacitor (1600) are shown and has been used for and the representativeness encapsulation cross section of discrete and the microporous layers (850) that planar capacitor is interconnected.
Figure 15 B shows the example of array of capacitors, and described array of capacitors comprises with respect to IC (1700) lines up each capacitors (1800) of discrete capacitor sizes array, various with diverse location, and the guide hole path connects.
Figure 16 has described that relative dielectric constant is 3.8, thickness is 100 transmission lines that are not connected (2030) simulation model that 38 microns on-chip and bus plane (2000) separates.Transmission line 10 mils at interval separates, and 15mm is long, and (mil) is wide for 2.82 mils, and every line all is terminated to power supply and ground plane (50ohm line terminal) by the resistance of 99ohm (2040).A kind of situation is on the substrate of bus plane 14 micron thickness that are positioned at the ground plane opposite.The relative dielectric constant of substrate is 3.8, and loss factor is 0.02.Another situation be bus plane 14 micron thickness that are positioned at the ground plane opposite, dielectric constant is 11 relatively, loss factor is on 0.02 the substrate.Generation has the 80pS pulse duration, 20pS rises and the output driving (2020) of the square wave bit stream of the 5GHz of fall time is used to drive 100 transmission lines, and acquisition is positioned at the response of " eye shape " figure of transmission line central authorities.Figure 17 shows the eye pattern of first kind of situation, and bus plane substrate dielectric constant is 3.8, and wherein the eyelet height is 2.4799V.Figure 17 B shows the response that the identical and bus plane substrate dielectric constant of condition is second kind of situation of 11.The eyelet height is 2.6929V, with respect to first kind of situation very big improvement has been arranged.Interval between the line is changed to 3 mils, thereby has 50 groups of transmission line lines that connect right.Under the situation that other condition remains unchanged, obtain the eye pattern response.It is response under 3.8 situations that Figure 18 A shows bus plane substrate dielectric constant, is response under 11 situations and Figure 18 B shows bus plane substrate dielectric constant.The higher bus plane substrate of dielectric constant produces the eye pattern response that improves.
Figure 19 shows except the plane bus plane also comprises the simulation model of the structure of discrete decoupling capacitor and is used to analyze simultaneous switching noise (SSN).Simulation model separate with bus plane (2200), thickness is that 38 microns relative dielectric constants are that to have 50 groups of transmission lines (2230) that connect on 3.8 the substrate right.Transmission line 3 mils that are spaced, 15mm is long, and 2.82 mils are wide, and every line all uses the resistance (2240) of 99ohm to be terminated to power supply and ground plane (50ohm transmission-wire terminal).Bus plane is positioned on the substrate of 14 micron thickness on ground plane (2210) opposite in some cases.The substrate relative dielectric constant is 3.8, and loss factor is 0.02.In other cases, bus plane be positioned at 14 micron thickness on ground plane opposite, relatively dielectric constant is 11, loss factor is on 0.02 the substrate.Generation has that 80pS pulse duration, 20pS rise and the output of the square wave bit stream of the 5GHz of fall time drives (2020) and is used to drive simultaneously 100 transmission lines, and obtains the noise voltage that produces on bus plane.The variation of the quality of type, SMT or embedded discrete and capacitor is carried out analysis.Capacitor is positioned at the zone (2260) of driving or close transmission line.
Figure 20 has described the transmission line (2300) of 50 pairs of connections, the top view of the structure of 100 transmission lines altogether.25 SMT capacitors to being placed on the drive end of transmission line, originate in transmission line to 1 (2310) every a transmission line, and ensuing one is positioned at transmission line to 3 (2320), ends at transmission line at last to 50 (2330).The dielectric constant of plane bus plane substrate is 3.8.Each condenser capacitance is 100nF, and equivalent series inductance (ESL) is about 205pH, and equivalent series resistance (ESR) is 100 milliohms.Square wave bit stream with 80pS pulse duration, 20pS rising and 5GHz of fall time is used to drive simultaneously 100 transmission lines, and records the noise voltage on the bus plane.At each condenser capacitance is 1nF, and equivalent series inductance (ESL) is about 33pH, and equivalent series resistance (ESR) repeats this process when being 9 milliohms.Plane bus plane substrate dielectric constant in this structure is 11.It is the change in voltage of 25 SMT capacitors on the bus plane under 3.8 situations that Figure 21 A shows at plane bus plane substrate dielectric constant.It is the change in voltage of 25 discrete capacitors on the bus plane under 11 situations that Figure 21 B shows at plane bus plane substrate dielectric constant.Reducing greatly of the bus plane noise that the synchro switch that output drives produces is owing to used embedded capacitor and the plane bus plane substrate with higher dielectric constant.
Add extra SMT capacitor to determine the to provide SMT number of capacitors that reduces the noise reduction of equivalence with the noise of embedded capacitor structure to model.50,75 and 100 SMT capacitors have been carried out modeling.50 capacitor arrangements can be realized by placing capacitor at the right drive end of each transmission line.75 capacitor arrangements can be by realizing adding a secondary series capacitor every a transmission line, and 100 capacitor arrangements can produce 2 * 50 array by adding capacitor, as shown in figure 22.In the figure, transmission line all has capacitor to the 50 pair of transmission line at drive end from first to (2410) to (2400).
It is the variation of voltage on the bus plane under 3.8 situations that Figure 23 A shows at 50 SMT electric capacity and planar substrates dielectric constant.It is the variation of voltage on the bus plane under 3.8 situations that Figure 23 B shows at 75 SMT electric capacity and planar substrates dielectric constant, is the variation of voltage on the bus plane under 3.8 situations and Figure 23 C shows at 100 SMT electric capacity and planar substrates dielectric constant.All four kinds of SMT capacitor arrangements are that 11 embedded discrete capacitance structure will produce the bus plane noise that the higher synchro switch that is driven by output causes than have 25 capacitors, bus plane dielectric constant shown in Figure 21 B all.
" die shadow " is defined herein as the packaging area that is projected under the semiconductor element area of coverage when the top is seen.Figure 24 is top view or the vertical view that tube core (2910) is gone up in encapsulation (2900).The core logic of tube core part is typically shown in solid area 2920, and the input/output circuitry of tube core typically is arranged in around the circumference of shadow region (2930) tube core." die shadow " in this example is the shade of zone on bottom of 2910 definition.Figure 25 is to use solder sphere (2810) to be installed in the cross section of the tube core (2800) on the part of enclosed chip.Enclosed chip comprises that such as a plurality of layers such as 2820 and 2830 wherein these layers can be dielectric interconnection layer or capacitor layer (with seeing Fig. 1).The zone 2840 that is positioned on the capacitor layer under the tube core is " die shadow " districts, promptly is used for the capacitor of core logic or the optimum position of I/O decoupling capacitor.
Claims (10)
1. one kind is used for providing the low noise power supply packaged device to integrated circuit, comprise: semiconductor element, the I/O power terminal, and be selected from discrete, the plane and the combination the embedded ceramic capacitors array, the position that wherein said capacitor is placed is selected within the circumference of shade of semiconductor element, part is within the circumference of the shade of semiconductor element, near the circumference of the shade of semiconductor element, and combination.
2. device as claimed in claim 1 is characterized in that, the as close as possible described I/O power terminal of described capacitor.
3. as any one the described device in claim 1 or 2, it is characterized in that described array of capacitors is in parallel, and form by capacitor with different resonance frequencys.
4. device as claimed in claim 3 is characterized in that, described size, shape with capacitor of different resonance frequencys, position and interconnected difference.
5. one kind is used for providing the low noise power supply packaged device to integrated circuit, comprise: use be the embedded ceramic capacitors array that is selected from discrete, the plane or its combination, the position that wherein said capacitor is placed is selected within the circumference of shade of semiconductor element, part within the circumference of the shade of semiconductor element, near the tube core, and combination; And wherein said capacitor has different resonance frequencys, and arranges so that the resistance value that the curve of the impedance versus frequency of array of capacitors produces is equal to or less than the mode of target impedance value.
6. method that is used for the design optimization array of capacitors may further comprise the steps:
A. make up integrated circuit packaging and testing structure, the embedded ceramic capacitors array that wherein said structure comprises the I/O power terminal and is selected from discrete, the plane or its combination, the position that wherein said capacitor is placed is selected within the circumference of shade of semiconductor element, part is within the circumference of the shade of semiconductor element, near the tube core, and combination, and wherein said structure comprises different capacitor design, size, path is interconnected and interconnected;
B. test their electric capacity, resistance and the inductance value separately and the response of resistance value relative frequency; And
C. the response of the composite impedance relative frequency of various array of capacitors is carried out modeling to satisfy the impedance target; And
D. based on modeling result Computer-Assisted Design, Manufacture And Test structure.
7. a kind of optimized array of capacitors that forms by method as claimed in claim 6.
8. the device that comprises optimization array of capacitors as claimed in claim 7.
9. method as claimed in claim 6 is characterized in that described array of capacitors comprises one or more planar capacitors.
10. device as claimed in claim 1 is characterized in that, described capacitor is to adopt the technology that is selected from thick film, film and combination thereof to make.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US72942505P | 2005-10-21 | 2005-10-21 | |
| US60/729,425 | 2005-10-21 | ||
| US11/523,270 | 2006-09-19 |
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| CN1967838A true CN1967838A (en) | 2007-05-23 |
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| CN 200610136568 Pending CN1967838A (en) | 2005-10-21 | 2006-10-20 | A package having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuitry and methods of forming thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109413839A (en) * | 2018-10-10 | 2019-03-01 | 郑州云海信息技术有限公司 | A kind of method and system reducing EMI by putting capacitance positions |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109413839A (en) * | 2018-10-10 | 2019-03-01 | 郑州云海信息技术有限公司 | A kind of method and system reducing EMI by putting capacitance positions |
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