CN1964035A

CN1964035A - ESD protection circuit for high voltage of power supply by electrostatic elimination with low voltage component

Info

Publication number: CN1964035A
Application number: CN 200510125017
Authority: CN
Inventors: 柯明道; 李健铭
Original assignee: Silicon Integrated Systems Corp
Current assignee: Silicon Integrated Systems Corp
Priority date: 2005-11-11
Filing date: 2005-11-11
Publication date: 2007-05-16
Anticipated expiration: 2025-11-11
Also published as: CN100428464C

Abstract

The disclosed protective circuit for static discharging comprises: a static MOS circuit as the discharging path, and a trigger current generation circuit to generate trigger signal for conducting the MOS circuit.

Description

Utilize the ESD protection circuit for high voltage of power supply of electrostatic elimination with low voltage component

Technical field

The protective circuit of the relevant a kind of Electrostatic Discharge of the present invention, particularly relevant a kind of low voltage component ESD protection circuit with its eliminating when generation of static electricity that utilizes.

Background technology

In the electronic installation of precision; because the microminiaturization of circuit element; and accurate degree significantly promotes; so this class precision electronic device; particularly Nei Bu small electric sub-element is for from being produced in the operational environment; or the static of being introduced when contacting this electronic installation, all very responsive and need being protected from the user.

Therefore; in the precision electronic device of majority; all need additional designs one ESD protection circuit suitably to get rid of contingent static, with the circuit of protection in electronic installation, electronic component wherein can not be damaged because of high pressure that static brought.

As shown in Fig. 1, be the I-V curve chart of the electrostatic discharge circuit of a traditional stack NMOS.In Fig. 1, lateral seat is designated as the voltage difference that drains to source electrode, and vertically coordinate is the drain current value.Represent among the figure that when draining when the accumulation progressively of the voltage difference of source electrode is risen, the drain current value also can correspondingly rise; And after having exceeded a trigger voltage (trigger voltage) value up to draining to the voltage difference of source electrode, then can penetrate (punch through) effect thereby begin to such an extent that drain to the electric value difference value of source electrode and begin to rebound (snap-back), up to drop to keep voltage (holding voltage) value till.Then be called the district of rebounding (snap-back region) from trigger voltage to the magnitude of voltage gap of keeping the voltage.In addition, get back to the voltage difference of source electrode when draining keep voltage after, voltage difference afterwards then is to present gently to increase, and this moment, drain current also can rise on correspondence ground.

By the above as can be known; when the electrostatic potential value if greatly too during trigger voltage value; then can make the NMOS that piles up as electrostatic discharge protective circuit be switched on because of the cause of meeting penetration effect; so electrostatic induced current can be grounded release by piling up NMOS, reach the not purpose of destruction by electrostatic field of protection internal electronic element.But traditional shortcoming of piling up the NMOS electrostatic discharge protective circuit is; if the electrostatic potential value is not greater than trigger voltage value; then this electrostatic discharge protective circuit can't be switched on; that is can't get rid of electrostatic induced current thereby this electrostatic induced current and become factors of instability among can continuing to be retained in electronic installation, make the user to expect and when can cause great destruction electronic installation.

Fig. 2 show an integrated circuit in traditional stack NMOS electrostatic discharge protective circuit.The purpose of this integrated circuit is that so inside has mixed-voltage, magnitude of voltage is respectively Vdd and Vcc as the semiconductor chip that links different operating voltage or the interface of subsystem.Be attached to outside the internal circuit at one of them I/O weld pad of integrated circuit as can see from Figure 2, also be attached to the drain electrode (drain) of first NMOS (being NMOS1), the grid of NMOS1 (gate) then is linked to power supply Vdd, the source electrode of NMOS1 (source) is connected with the drain electrode of second NMOS (being NMOS2), the grid of NMOS2 (gate) then is linked to power Vcc, at last, the source electrode of NMOS2 is attached to earth terminal.

NMOS1 in Fig. 2 and NMOS2 do to pile up with cascaded structure (cascade configuration), node that both link to each other forms diffusion region altogether, has a parasitic two-carrier junction transistor (lateral bipolar junction transistor) so can be considered in the inside of piling up NMOS.When electrostatic potential value greatly too during trigger voltage, then this parasitic two-carrier junction transistor can be switched on and make static can be discharged from internal circuit.But it is as shown in Figure 1, when if the electrostatic potential value does not surpass trigger voltage, then parasitic two-carrier junction transistor can't be switched on and cause static to continue to be retained in the integrated circuit at this moment, can cause the mos gate utmost point oxide layer (gate oxide) of the I/O buffer of I/O weld pad inside to damage at last.Because in a mixed-voltage I/O circuit, the breakdown voltage of mos gate utmost point oxide layer (breakdown voltage) can diminish, so can be stacked on the electrostatic breakdown of IC interior.

In view of above-mentioned in the conventional electrostatic discharge protection circuit; when electrostatic induced current is present in the circuit but is not more than trigger voltage; the situation that can cause this protective circuit to be activated; therefore need badly and will propose a sensitiveer electrostatic discharge protective circuit of eliminating, can avoid being damaged for the electronic component that the static that does not reach trigger voltage value is done to get rid of with the protection IC interior for static existence and static.

Summary of the invention

In above-mentioned prior art, many shortcomings of conventional electrostatic discharge protection circuit, main purpose of the present invention is to propose a kind of ESD protection circuit, and it is higher for the sensitivity that static is got rid of, and can less electrostatic potential be reacted immediately.

Another object of the present invention is to propose a kind of ESD protection circuit, circuit is made of low withstand voltage electronic component, but the static of the high-voltage value of can loading passes through, to reach the effect of release electrostatic.

According to above-described purpose, the invention provides a kind of ESD protection circuit, wherein comprise: one first electrostatic detection circuit, it exports one first electrostatic detection signal; One second electrostatic detection circuit, it exports one second electrostatic detection signal; One trigger current produces circuit, and it receives the first electrostatic detection signal and the second electrostatic detection signal, exports a triggering signal then; One side two-carrier junction transistor, its base stage receives triggering signal; And one pile up the MOS circuit, when an electrostatic potential is higher than a preset value, trigger current produces circuit and can export triggering signal so, sees through side two-carrier junction transistor and makes and pile up the MOS circuit and be switched on, and become an electrostatic discharging path to get rid of electrostatic potential.

Description of drawings

Fig. 1 is the I-V curve chart that shows the traditional stack nmos circuit;

Fig. 2 is the circuit diagram that shows a traditional stack NMOS;

Fig. 3 is the ESD protection circuit figure that shows a preferred embodiment of the present invention;

Fig. 4 is the ESD protection circuit figure that shows another preferred embodiment of the present invention;

Fig. 5 is the ESD protection circuit figure that shows another preferred embodiment of the present invention;

Fig. 6 is the ESD protection circuit figure that shows another preferred embodiment of the present invention; And

Fig. 7 is the ESD protection circuit figure that shows another preferred embodiment of the present invention.

Embodiment

Some embodiments of the present invention can be described in detail as follows.Yet except describing in detail, the present invention can also implement in other embodiment widely, and scope of the present invention do not limited, its with after the claim scope be as the criterion.

The present invention discloses a kind of Electrostatic Discharge protective circuit, the IC interior that can be applied to have AC-battery power source.In the integrated circuit of this class; usually the input that has different voltages more than two; disclosed ESD protection circuit; its purpose is as each voltage input end of integrated circuit and the interface circuit between the earth terminal; when generation of static electricity; can make static before the inner member that destroys integrated circuit, just static be discharged by earth terminal.

Show the ESD protection circuit that meets one embodiment of the invention among Fig. 3; wherein comprise: one first electrostatic detection circuit 10, one second electrostatic detection circuit 20, a trigger current produce circuit 30, a side two-carrier junction transistor LBJT (Lateral Bipolar Junction Transistor), and one piles up MOS circuit 40.Wherein side two-carrier junction transistor LBJT piles up two NMOS in the MOS circuit 40, because the node that both link to each other forms diffusion region altogether, thereby a parasitic two-carrier junction transistor that causes.Pile up MOS circuit 40 and comprise one the one NMOS (this paper is to call N1 in the following text), one the 2nd NMOS (this paper is to call N2 in the following text) and one first resistance R 1.Wherein the drain electrode of N1 links the collector electrode of the first voltage input end Vdd and side two-carrier junction transistor LBJT, the grid of N1 links first end of first resistance R 1, the source electrode of N1 links the drain electrode of N2, the source electrode of N2 links the emitter of earth terminal Vss and side two-carrier junction transistor LBJT, the grid of N2 links earth terminal Vss, the substrate of N1 and N2 also is linked to earth terminal Vss jointly, and second end of first resistance R 1 links the second voltage input end Vcc.

The first electrostatic detection circuit 10 comprises one second resistance R 2, one first capacitor C 1, and one second capacitor C 2.Second resistance R 2 wherein, its first end is linked to the first voltage input end Vdd, and its second end can be exported the first electrostatic detection signal; First capacitor C 1, its first end is linked to second end of second resistance R 2; Second capacitor C 2, its first end is linked to second end of first capacitor C 1, and its second end is linked to earth terminal Vss.And the second electrostatic detection circuit 20 comprises one the 3rd resistance R 3 and one the 3rd capacitor C 3.The 3rd resistance R 3 its first ends are linked to the second voltage input end Vcc, and its second end can be exported the second electrostatic detection signal; The 3rd capacitor C 3 its first ends are linked to second end of the 3rd resistance R 3, and its second end is linked to earth terminal Vss.

Trigger current produces circuit 30 and comprises one the one PMOS (this paper is to call P1 in the following text), one the 2nd PMOS (this paper is to call P2 in the following text), and one the 3rd NMOS (this paper is to call N3 in the following text).The drain electrode of P1 is linked to the first voltage input end Vdd, and the grid of P1 receives the first electrostatic detection signal; The drain electrode of P2 is linked to the source electrode of P1, and the substrate of P2 and P1 is linked to the first voltage input end Vdd jointly; The grid of N3 and P2 links jointly and receives the second electrostatic detection signal, and the drain electrode of N3 and the source electrode of P2 are connected and export triggering signal, and the substrate of N3 and source electrode are linked to earth terminal Vss jointly.

When an electrostatic potential betides the first voltage input end Vdd, then this moment, node A and Node B were sent the first electrostatic detection signal and the second electrostatic detection signal with low-voltage position standard respectively, and make the grid of P1 and P2 receive this low-voltage position standard, therefore P1 and P2 all become conducting state, a trigger current outputs to the base stage (being node C) of side two-carrier junction transistor LBJT via the path that P1 and P2 constituted as a triggering signal then.Therefore make side two-carrier junction transistor LBJT be switched on; just be equal to N1 and N2 all conductings simultaneously; so between the first voltage input end Vdd and earth terminal Vss; at this moment N1 and N2 have constituted an electrostatic discharging path; make aforesaid electrostatic potential to get rid of, thereby reach the purpose of protection IC interior element by this electrostatic discharging path.

Fig. 4 shows another embodiment according to the invention.Wherein Fig. 4 is the circuit embodiments similar in appearance to Fig. 3, and the trigger current generation circuit 50 of Fig. 4 is the difference part between two figure, below will produce circuit 50 at trigger current and do detailed explanation.

Trigger current produces circuit 50 and comprises one the 3rd PMOS (this paper is to call P3 in the following text), one the 4th PMOS (this paper is to call P4 in the following text), one the 5th PMOS (this paper is to call P5 in the following text), one the 4th NMOS (this paper is to call N4 in the following text), one the 5th NMOS (this paper is to call N5 in the following text), and one the 6th NMOS (this paper is to call N6 in the following text).The wherein drain electrode of the substrate of the drain electrode of P3 and substrate, P4 and P5 and substrate all is linked to the first voltage input end Vdd; The grid of P3 and P5 links jointly, and receives the first electrostatic detection signal; The source electrode of P3 and the drain electrode of P4 link jointly; The source electrode of P5 and the drain electrode of N5 link P4, N4 jointly, and the grid of N6 links and receive the source electrode of the second electrostatic detection signal P4, the drain electrode of N4 jointly, and the grid of N5 links jointly; The source electrode of N5 and the drain electrode of N6 are common to be linked and the output triggering signal; The substrate of the substrate of N5 and N6, the source electrode of N6, N4 and source electrode then are linked to earth terminal Vcc jointly.

When an electrostatic potential betided the first voltage input end Vdd, then this moment, node A and Node B were sent the first electrostatic detection signal and the second electrostatic detection signal with low-voltage position standard respectively, and made P3, P4 and P5 all become conducting state.The conducting of P3 and P4 has constituted a path, makes the voltage input end Vdd that wins transmit an electric current to node D by this path, and causes N5 to be switched on.At this moment, P5 and N5 are all conducting state, and therefore a trigger current outputs to the base stage (being node E) of side two-carrier junction transistor LBJT via the path that P5 and N5 constituted as a triggering signal.Make side two-carrier junction transistor LBJT be switched on; just be equal to N1 and N2 all conductings simultaneously; so between the first voltage input end Vdd and earth terminal Vss; at this moment N1 and N2 have constituted an electrostatic discharging path; aforesaid electrostatic potential can be got rid of by this electrostatic discharging path, thereby reach the purpose of protection IC interior element.

Fig. 5 shows the ESD protection circuit meet another embodiment of the present invention, wherein comprises: one first electrostatic detection circuit 60, one second electrostatic detection circuit 70, a gate driver circuit 90, and one pile up MOS circuit 80.Wherein pile up MOS circuit 80, comprise one the 7th NMOS (this paper is to call N7 in the following text) and one the 8th NMOS (this paper is to call N8 in the following text), wherein the drain electrode of N7 links the first voltage input end Vdd, the grid of N7 receives the first grid drive signal, the source electrode of N7 links the drain electrode of N8, the source electrode of N8 links earth terminal Vss, and the grid of N8 receives the second grid drive signal, and the substrate of N7 and N8 also is linked to earth terminal Vss jointly.

The first electrostatic detection circuit 60 comprises one the 4th resistance R 4, one the 4th capacitor C 4 and one the 5th capacitor C 5.The 4th resistance R 4 its first ends are linked to the first voltage input end Vdd, and its second end can be exported the first electrostatic detection signal; The 4th capacitor C 4 its first ends are linked to second end of the 4th resistance R 4; The 5th capacitor C 5 its first ends are linked to second end of the 4th capacitor C 4, and its second end is linked to earth terminal Vss.The second electrostatic detection circuit 70 comprises one the 5th resistance R 5 and one the 6th capacitor C 6.Wherein first end of the 5th resistance R 5 is linked to the second voltage input end Vcc, and its second end can be exported the second electrostatic detection signal; The 6th capacitor C 6, its first end is linked to second end of the 5th resistance R 5, and its second end is linked to earth terminal Vss.

Gate driver circuit 90 comprises one the 6th PMOS (this paper is to call P6 in the following text), a PMOS (this paper is to call P7 in the following text), one the 8th PMOS (this paper is to call P8 in the following text), one the 6th resistance R 6 and one the 9th NMOS (this paper is to call N9 in the following text).The wherein drain electrode of the drain electrode of P6 and substrate, P8 and substrate, and the substrate of P7 is linked to the first voltage input end Vdd jointly; The grid of P6 and P8 links jointly and receives the first electrostatic detection signal; The source electrode of P6 and the drain electrode of P7 link jointly; The grid of P7 and N9, and first end of the 6th resistance R 6 links jointly, and receive the second electrostatic detection signal; Second end of the 6th resistance R 6 and the source electrode of P8 link jointly, and substrate and the source electrode of the common binding of drain electrode of the source electrode of output first grid drive signal P7 and N9 and output second grid drive signal N9 then are linked to earth terminal Vss jointly.

When an electrostatic potential betided the first voltage input end Vdd, then this moment, node F and node G sent the first electrostatic detection signal and the second electrostatic detection signal with low-voltage position standard respectively, and made P6, P8 and P7 all become conducting state.The conducting of P6 and P7 has constituted a path, makes the voltage input end Vdd that wins transmit an electric current to node I by this path, causes N8 to be switched on as the second grid drive signal.In addition, the conducting of P8 has constituted a path, makes the voltage input end Vdd that wins transmit an electric current to node H by this path, causes N7 to be switched on as the first grid drive signal.At this moment; N7 and N8 are all conducting state, so between the first voltage input end Vdd and earth terminal Vss, at this moment N7 and N8 have constituted an electrostatic discharging path; aforesaid electrostatic potential can be got rid of by this electrostatic discharging path, thereby reach the purpose of protection IC interior element.

Fig. 6 shows another embodiment according to the invention.Wherein Fig. 6 is the circuit embodiments similar in appearance to Fig. 5, and the gate driver circuit 100 of Fig. 6 is the difference part between two figure, below will do detailed explanation at this gate driver circuit 100.

Gate driver circuit 100 comprises one the 9th PMOS (this paper is to call P9 in the following text), 1 the tenth PMOS (this paper is to call P10 in the following text), 1 the 11 PMOS (this paper is to call P11 in the following text), 1 the 12 PMOS (this paper is to call P12 in the following text), one the 7th resistance R 7,1 the tenth NMOS (this paper is to call N10 in the following text), 1 the 11 NMOS (this paper is to call N11 in the following text), and 1 the 12 NMOS (this paper is to call N12 in the following text); The wherein drain electrode of the substrate of the drain electrode of P9 and substrate, P10, P11 and P12 and substrate all is linked to the first voltage input end Vdd jointly; P9, P11, and all bindings jointly of the grid of P12, and receive the first electrostatic detection signal; Second end of the source electrode of P12 and the 7th resistance R 7 is common to be linked and output first grid drive signal; First end of the 7th resistance R 7, the grid of P10, the grid of N10, and the grid of N12 links jointly, and receive the second electrostatic detection signal; The source electrode of P10, the drain electrode of N10, and the grid of N11 links jointly; The source electrode of N11 and the drain electrode of N12 are common to be linked and output second grid drive signal; The source electrode of the source electrode of N10 and substrate, N12 and substrate, and the substrate of N11 all are linked to earth terminal Vss jointly; The source electrode of P9 and the drain electrode of P10 link jointly; The source electrode of P11 and the drain electrode of N11 link jointly.

When an electrostatic potential betided the first voltage input end Vdd, then this moment, node F and node G sent the first electrostatic detection signal and the second electrostatic detection signal with low-voltage position standard respectively, and made P9, P10, P11 and P12 all become conducting state.The conducting of P12 has constituted a path, makes the voltage input end Vdd that wins transmit an electric current to node J by this path, causes N7 to be switched on as the first grid drive signal.The conducting of P9 and P10 has constituted a path, makes the voltage input end Vdd that wins transmit an electric current to node K by this path, and causes N11 to be switched on.This moment P11 and N11 all conducting make the voltage input end Vdd that wins transmit an electric current to node L so constituted a path by this path, cause N8 to be switched on as the second grid drive signal.So last N7 and N8 are all conducting state; so between the first voltage input end Vdd and earth terminal Vss; at this moment N7 and N8 have constituted an electrostatic discharging path, and aforesaid electrostatic potential can be got rid of by this electrostatic discharging path, thereby reach the purpose of protection IC interior element.

Fig. 7 shows another embodiment according to the invention.Wherein Fig. 7 is similarly the circuit embodiments similar in appearance to Fig. 5, and the gate driver circuit 110 of Fig. 7 is the difference part between two figure, below will do detailed explanation at this gate driver circuit 110.

Gate driver circuit 110 comprises 1 the 13 PMOS (this paper is to call P13 in the following text), 1 the 14 PMOS (this paper is to call P14 in the following text), 1 the 15 PMOS (this paper is to call P15 in the following text), one the 8th resistance R 8,1 the 13 NMOS (this paper is to call N13 in the following text), 1 the 14 NMOS (this paper is to call N14 in the following text), and one the 7th capacitor C 7.The wherein drain electrode of the substrate of the drain electrode of P13 and substrate, P14, P15 and substrate, and first end of the 8th resistance R 8 all are linked to the first voltage input end Vdd jointly; The grid of P13 receives the first electrostatic detection signal; The grid of P14 and N13 links jointly and receives the second electrostatic detection signal; The substrate of N13 and source electrode are linked to earth terminal Vss jointly; The source electrode of P14 and the drain electrode of N13 are common to be linked and output second grid drive signal; The source electrode of P13 and the drain electrode of P14 link jointly; The grid of second end, P15 and the N14 of the 8th resistance R 8, and first end of the 7th capacitor C 7 links jointly; The substrate of N14 and source electrode, and second end of the 7th capacitor C 7 is linked to the second voltage input end Vcc jointly; The source electrode of P15 and the drain electrode of N14 are common to be linked and output first grid drive signal.

When an electrostatic potential betided the first voltage input end Vdd, then this moment, node F and node G sent the first electrostatic detection signal and the second electrostatic detection signal with low-voltage position standard respectively, and made P13 and P14 all become conducting state.In addition, on node M, also make P15 be switched on because having low-voltage position standard.The conducting of P15 has constituted a path, makes the voltage input end Vdd that wins transmit an electric current to node N by this path, allows N7 be switched on as the first grid drive signal.The conducting of P13 and P14 has constituted a path, makes the voltage input end Vdd that wins transmit an electric current to node 0 by this path, causes N8 to be switched on as the second grid drive signal.So last N7 and N8 are all conducting state; so between the first voltage input end Vdd and earth terminal Vss; at this moment N7 and N8 have constituted an electrostatic discharging path, and aforesaid electrostatic potential can be got rid of by this electrostatic discharging path, thereby reach the purpose of protection IC interior element.

Wherein be positioned at the N14 of gate driver circuit 110, it is the NMOS element that adopts deep layer N type well (deep N well), its objective is to make the substrate of N14 to be linked to the second voltage input end Vcc jointly, and needn't allow the substrate of N14 be linked to earth terminal Vss with source electrode.Therefore can avoid the grid oxic horizon (gate oxide) of N14 to cause possible damage because grid and substrate both end voltage difference are excessive.

The above is preferred embodiment of the present invention only, is not in order to limit the application's claim scope; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in following the application's claim scope.

Claims

1. ESD protection circuit wherein comprises:

One first electrostatic detection circuit, its first end is linked to a first input end, and its second end is linked to an earth terminal, and its 3rd end is exported one first electrostatic detection signal;

One second electrostatic detection circuit, its first end is linked to one second input, and its second end is linked to this earth terminal, and its 3rd end is exported one second electrostatic detection signal;

One trigger current produces circuit, and its first end is linked to this first input end, and its second end is linked to this earth terminal, and its 3rd termination is received this first electrostatic detection signal, and its 4th termination is received this second electrostatic detection signal, and its five terminal is exported a triggering signal;

One side two-carrier junction transistor, its base stage receives this triggering signal; And

One piles up the MOS circuit, comprise one the one NMOS, one the 2nd NMOS and one first resistance, wherein the drain electrode of a NMOS links the collector electrode of this first input end and this side two-carrier junction transistor, the grid of the one NMOS links first end of this first resistance, the source electrode of the one NMOS links the drain electrode of the 2nd NMOS, the source electrode of the 2nd NMOS links the emitter of this earth terminal and this side two-carrier junction transistor, the grid of the 2nd NMOS also links this earth terminal, the substrate of the one NMOS and the 2nd NMOS also is linked to this earth terminal jointly, and second end of this first resistance links this second input;

Wherein when an electrostatic potential of this first input end was higher than a preset value, this trigger current produces circuit can export this triggering signal, and making this pile up the MOS circuit becomes an electrostatic discharging path to get rid of this electrostatic potential.

2. ESD protection circuit as claimed in claim 1 is characterized in that described trigger current produces circuit and comprises:

One the one PMOS, the drain electrode of a PMOS is linked to this first input end, and the grid of a PMOS receives this first electrostatic detection signal;

One the 2nd PMOS, the drain electrode of the 2nd PMOS is linked to the source electrode of a PMOS, and the substrate of the 2nd PMOS and a PMOS is linked to this first input end jointly; And

One the 3rd NMOS, the grid of the 3rd NMOS and the 2nd PMOS links jointly and receives this second electrostatic detection signal, the source electrode of the drain electrode of the 3rd NMOS and the 2nd PMOS is connected and exports this triggering signal, and the substrate of the 3rd NMOS and source electrode are linked to this earth terminal jointly.

3. ESD protection circuit as claimed in claim 2 is characterized in that the described first electrostatic detection circuit comprises:

One second resistance, its first end is linked to this first input end, and its second end is exported this first electrostatic detection signal;

One first electric capacity, its first end are linked to this second end of this second resistance; And

One second electric capacity, its first end is linked to second end of this first electric capacity, and its second end is linked to this earth terminal.

4. ESD protection circuit as claimed in claim 3 is characterized in that the described second electrostatic detection circuit comprises:

One the 3rd resistance, its first end is linked to this second input, and its second end can be exported this second electrostatic detection signal; And

One the 3rd electric capacity, its first end are linked to this second end of the 3rd resistance, and its second end is linked to this earth terminal.

5. ESD protection circuit as claimed in claim 4 is characterized in that described first electric capacity, second electric capacity, and the 3rd electric capacity is the electric capacity that utilizes mos field effect transistor (MOSFET) to be constituted.

6. ESD protection circuit as claimed in claim 5 is characterized in that described side two-carrier junction transistor is parasitic two-carrier junction transistor.

7. ESD protection circuit as claimed in claim 1 is characterized in that described trigger current produces circuit and comprises one the one PMOS, one the 2nd PMOS, one the 3rd PMOS, one the 3rd NMOS, one the 4th NMOS, and one the 5th NMOS; Among its spy, the substrate of the drain electrode of a PMOS and substrate, the 2nd PMOS and drain electrode and the substrate of the 3rd PMOS all are linked to this first input end; The grid of the one PMOS and the 3rd PMOS links jointly, and receives this first electrostatic detection signal; The drain electrode of the source electrode of the one PMOS and the 2nd PMOS links jointly; The drain electrode of the source electrode of the 3rd PMOS and the 4th NMOS links jointly; The 2nd PMOS, the 3rd NMOS, and the grid of the 5th NMOS links jointly and receives this second electrostatic detection signal; The drain electrode of the source electrode of the 2nd PMOS, the 3rd NMOS, and the grid of the 4th NMOS links jointly; The drain electrode of the source electrode of the 4th NMOS and the 5th NMOS links jointly and exports this triggering signal; The substrate of the source electrode of the substrate of the 4th NMOS and the 5th NMOS, the 5th NMOS, the 3rd NMOS and source electrode then are linked to this earth terminal jointly.

8. ESD protection circuit as claimed in claim 7 is characterized in that the described first electrostatic detection circuit comprises:

One second resistance, its first end is linked to this first input end, and its second end can be exported this first electrostatic detection signal;

9. ESD protection circuit as claimed in claim 8 is characterized in that the described second electrostatic detection circuit comprises:

10. ESD protection circuit as claimed in claim 9 is characterized in that described first electric capacity, second electric capacity, and the 3rd electric capacity is the electric capacity that utilizes mos field effect transistor (MOSFET) to be constituted.

11. ESD protection circuit as claimed in claim 10 is characterized in that described side two-carrier junction transistor is parasitic two-carrier junction transistor.

12. an ESD protection circuit is characterized in that comprising:

One gate driver circuit, its first end is linked to this first input end, its second end is linked to this earth terminal, its the 3rd termination is received this first electrostatic detection signal, its the 4th termination is received this second electrostatic detection signal, its five terminal is exported a first grid drive signal, and its 6th end is exported a second grid drive signal; And

One piles up the MOS circuit, comprise one the one NMOS and one the 2nd NMOS, wherein the drain electrode of a NMOS links this first input end, the grid of the one NMOS receives this first grid drive signal, the source electrode of the one NMOS links the drain electrode of the 2nd NMOS, the source electrode of the 2nd NMOS links this earth terminal, and the grid of the 2nd NMOS receives this second grid drive signal, and the substrate of a NMOS and the 2nd NMOS also is linked to this earth terminal jointly;

Wherein when an electrostatic potential of this first input end was higher than a preset value, this gate driver circuit can be exported this first grid drive signal and this second grid drive signal, and making this pile up the MOS circuit becomes an electrostatic discharging path to get rid of this electrostatic potential.

13. ESD protection circuit as claimed in claim 12 is characterized in that described gate driver circuit comprises one the one PMOS, one the 2nd PMOS, one the 3rd PMOS, one first resistance and one the 3rd NMOS; Drain electrode and the substrate of the wherein drain electrode of a PMOS and substrate, the 3rd PMOS, and the substrate of the 2nd PMOS is linked to this first input end jointly; The grid of the one PMOS and the 3rd PMOS links jointly and receives this first electrostatic detection signal; The drain electrode of the source electrode of the one PMOS and the 2nd PMOS links jointly; The grid of the 2nd PMOS and the 3rd NMOS, and first end of this first resistance links jointly, and receive this second electrostatic detection signal; Second end of this first resistance and the source electrode of the 3rd PMOS link jointly, and export this first grid drive signal; The drain electrode of the source electrode of the 2nd PMOS and the 3rd NMOS links jointly and exports this second grid drive signal; The substrate of the 3rd NMOS and source electrode then are linked to this earth terminal jointly.

14. ESD protection circuit as claimed in claim 13 is characterized in that the described first electrostatic detection circuit comprises:

15. ESD protection circuit as claimed in claim 14 is characterized in that the described second electrostatic detection circuit comprises:

16. ESD protection circuit as claimed in claim 15 is characterized in that described first electric capacity, second electric capacity, and the 3rd electric capacity is the electric capacity that utilizes mos field effect transistor (MOSFET) to be constituted.

17. ESD protection circuit as claimed in claim 12, it is characterized in that described gate driver circuit comprises one the one PMOS, one the 2nd PMOS, one the 3rd PMOS, one the 4th PMOS, one first resistance, one the 3rd NMOS, one the 4th NMOS, and one the 5th NMOS; Drain electrode and the substrate of the substrate of the wherein drain electrode of a PMOS and substrate, the 2nd PMOS, the 3rd PMOS and the 4th PMOS all are linked to this first input end jointly; The one PMOS, the 3rd PMOS, and all bindings jointly of the grid of the 4th PMOS, and receive this first electrostatic detection signal; Second end of the source electrode of the 4th PMOS and this first resistance links jointly and exports this first grid drive signal; The grid of first end of this first resistance, the grid of the 2nd PMOS, the 3rd NMOS, and the grid of the 5th NMOS links jointly, and receive this second electrostatic detection signal; The drain electrode of the source electrode of the 2nd PMOS, the 3rd NMOS, and the grid of the 4th NMOS links jointly; The drain electrode of the source electrode of the 4th NMOS and the 5th NMOS links jointly and exports this second grid drive signal; The source electrode of the source electrode of the 3rd NMOS and substrate, the 5th NMOS and substrate, and the substrate of the 4th NMOS all are linked to this earth terminal jointly; The drain electrode of the source electrode of the one PMOS and the 2nd PMOS links jointly; The drain electrode of the source electrode of the 3rd PMOS and the 4th NMOS links jointly.

18. ESD protection circuit as claimed in claim 17 is characterized in that the described first electrostatic detection circuit comprises:

19. ESD protection circuit as claimed in claim 18 is characterized in that the described second electrostatic detection circuit comprises:

20. ESD protection circuit as claimed in claim 19 is characterized in that described first electric capacity, second electric capacity, and the 3rd electric capacity is the electric capacity that utilizes mos field effect transistor (MOSFET) to be constituted.

21. ESD protection circuit as claimed in claim 12 is characterized in that described gate driver circuit comprises one the one PMOS, one the 2nd PMOS, one the 3rd PMOS, one first resistance, one the 3rd NMOS, one the 4th NMOS, and one the 4th electric capacity; The substrate of the wherein drain electrode of a PMOS and substrate, the 2nd PMOS, drain electrode and the substrate of the 3rd PMOS, and first end of this first resistance all are linked to this first input end jointly; The grid of the one PMOS receives this first electrostatic detection signal; The grid of the 2nd PMOS and the 3rd NMOS links jointly and receives this second electrostatic detection signal; The substrate of the 3rd NMOS and source electrode are linked to this earth terminal jointly; The drain electrode of the source electrode of the 2nd PMOS and the 3rd NMOS links jointly and exports this second grid drive signal; The drain electrode of the source electrode of the one PMOS and the 2nd PMOS links jointly; The grid of second end of this first resistance, the 3rd PMOS and the 4th NMOS, and first end of the 4th electric capacity links jointly; The substrate of the 4th NMOS and source electrode, and second end of the 4th electric capacity is linked to this second input jointly; The drain electrode of the source electrode of the 3rd PMOS and the 4th NMOS links jointly and exports this first grid drive signal.

22. ESD protection circuit as claimed in claim 21 is characterized in that the described first electrostatic detection circuit comprises:

23. ESD protection circuit as claimed in claim 22 is characterized in that the described second electrostatic detection circuit comprises:

24. ESD protection circuit as claimed in claim 23 is characterized in that described first electric capacity, second electric capacity, and the 3rd electric capacity is the electric capacity that utilizes mos field effect transistor (MOSFET) to be constituted.