CN1961417A - 半导体器件中作为低k膜的多孔陶瓷材料 - Google Patents

半导体器件中作为低k膜的多孔陶瓷材料 Download PDF

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CN1961417A
CN1961417A CNA2005800174568A CN200580017456A CN1961417A CN 1961417 A CN1961417 A CN 1961417A CN A2005800174568 A CNA2005800174568 A CN A2005800174568A CN 200580017456 A CN200580017456 A CN 200580017456A CN 1961417 A CN1961417 A CN 1961417A
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ild
layer
bigger
littler
integrated circuit
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格兰特·M·克洛斯特
吉鹏·莱乌
迈克尔·D·古德内尔
迈克尔·G·哈弗蒂
萨达希旺·尚卡尔
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Abstract

介绍了一种在半导体器件中的低k、较高E的多孔陶瓷膜的选择和形成方法。选择具有较高杨氏模量和较低介电常数的陶瓷材料。通过使该膜多孔化来减小k。

Description

半导体器件中作为低K膜的多孔陶瓷材料
技术领域
本发明涉及用于例如集成电路等半导体器件的电介质膜领域。
背景技术
在集成电路中通常使用几层电介质材料。例如，在形成于衬底中的晶体管之间形成互连，其中上方导体嵌入在层间电介质(ILD)中。通常使用几个这样的层，每一层都包括导线和用于与下层中的导体形成接触的通孔。在许多情况下，利用镶嵌(damascene)工艺将导体和通孔嵌入在ILD中。
电介质材料的介电常数(k)在很大程度上决定了集成电路中各个导体和通孔之间的电容。希望具有一种低k电介质，以减小RC延迟和导体之间的串扰。
使用并且建议使用几种电介质来减小该电容。这些低k电介质的一个问题是它们的机械性能差。由于经常需要进行化学机械抛光以便为多层互连结构提供足够的平坦度，因此这尤其是一个问题。这种和其他应力可能在机械性能差的层中引起故障。
附图说明
图1是几种材料的杨氏模量和介电常数(k)之间关系的示图；
图2是包括几种陶瓷材料的几种材料的杨氏模量和密度之间关系的示图；
图3示出了用于本发明实施例的方法；
图4A是层间电介质(ILD)和下方导体的截面正视图；
图4B示出了蚀刻通孔开口和沟槽之后的图4A的层；
图4C示出了形成阻挡层之后的图4B的结构；
图4D示出了金属化和平坦化工艺之后的图4C的结构；
图4E示出了减小ILD密度的工艺之后的图4D的结构。
具体实施方式
在以下说明中，介绍了在例如集成电路等半导体器件中多孔陶瓷材料的使用和形成。为了完整理解本发明，阐述了许多具体细节，例如具体化合物。对于本领域技术人员来说显而易见的是这些具体细节对于实施本发明来说不是必需的。此外，为了不会不必要地模糊本发明，没有具体描述公知的处理步骤，例如沉积步骤。
如上所述，半导体器件中电介质层的机械强度是很重要的，在如镶嵌工艺中经常进行的对层施加化学机械抛光(CMP)的情况下尤其如此。封装的应力甚至可能会比CMP应力更高，因此在ILD必须抗裂或抗变形的情形中也是非常重要的一点。
通常，在镶嵌工艺中在ILD中形成用于通路和导体这两者的开口。然后将金属沉积或电镀到开口中。金属覆盖ILD的整个暴露表面。使用平坦化步骤除去电介质表面的金属，最有效的是采用抛光的方法。除非ILD的强度足以承受这种抛光和其他应力，否则可能会在器件中产生缺陷。其他应力包括与封装和通常使用时的热循环相关的应力。
通常，电介质材料的机械强度包括其弹性模量、硬度和粘结强度，但不限于此。很大程度上，机械强度很好地遵循弹性模量，因此为了该专利的目的，使用弹性模量(其也被称作杨氏模量)来评估机械强度。杨氏模量被定义为给定材料的应力/应变，并通常以千兆-帕斯卡(GPa)为单位进行测量。该模量从橡胶的小于0.1、聚酰亚胺的3-5、柔软材料的100或以下、许多陶瓷的几百、变化到金刚石的1000。
如上所述，在集成电路中使用的、尤其是如大多数现代电路那样高频操作的集成电路中使用的包括ILD的电介质层应当具有低k。对于以大约32nm的最小间距制造的这种电路而言，可接受的介电常数k为大约2.2或更低。(介电常数可以高至2.4，并且仍然被认为是可接受的，因此本专利中使用的“大约2.2”是旨在覆盖k＝2.4的上限)。认为在集成电路处理中以杨氏模量测量的可接受的机械强度为6GPa或更高，优选大约10GPa或更高。
如以下详述，在致密基体(dense matrix)状态(无孔)中k大于2.2的陶瓷材料用作多孔基体中的ILD。通过减小陶瓷材料的密度来降低k。这通过在保持充分的机械强度的同时使陶瓷材料多孔化来实现。这些材料在多孔基体中具有大于6GPa的E值，如下所述。
通常，陶瓷被认为是坚硬的和易碎的非金属材料。它们通常是电绝缘体、耐热并通常不易被化学物质侵蚀。如下面将要介绍的，通过包括使用商业上可获得的前体的几种工艺可以形成陶瓷膜，包括具有氮化物的那些陶瓷膜。
随着电介质材料的密度降低(孔隙率增大)，其k成比例地降低。在其密度降低时，该材料的强度由以下公式来表达：E＝E0(ρm)，其中E＝预计的杨氏模量，E0＝致密基体(使材料多孔化之前的初始材料)的杨氏模量，ρ＝密度(与孔隙率和k成比例)，并且m＝实验确定的指数。
作为一个实例，k＝2.2(碳15％，孔隙率30％)的CDO所计算出的杨氏模量为4.1GPa。与之相比，k＝2.2(孔隙率47％)的多孔SiO2所计算出的杨氏模量为8.2GPa。
图1是三种二氧化硅(非陶瓷)基材料的k值和杨氏模量之间关系的示图。从k为2.2时能够看出，这些材料的E下降到低于或临近6GPa或更大，即所寻求的最小E。
图2是几种陶瓷材料的杨氏模量作为该材料密度的函数的示图。为了进行对比，该曲线还示出二氧化硅和金刚石。注意k还与密度成正比，可以看出这些陶瓷材料中的几种材料在较低的密度下具有比二氧化硅更大的强度。事实上，存在几种在k＝2.2所需的孔隙率下具有比SiO2更高的杨氏模量的陶瓷材料。
假定电介质膜所需的k为2.2。下表给出几种陶瓷材料的原始k、E0(致密膜)、以及在k为2.2时的孔隙率和E。为了进行对比，在该表中还给出了二氧化硅。
                   表1(k＝2.2)
  陶瓷   致密膜   多孔膜计算值
  k   E0(GPa)   孔隙率(％)   E(GPa)
  SiO2   4.5   75   47   8.2
  BeO   7.4   357   56   19.7
  MgO   9.7   290   62   10.2
  Al2O3   9.7   400   62   14.1
  Yb2O3   5.0   139   50   12.3
  SiC   5.5   430   52   32.0
  Si3N4   7.5   310   58   14.6
  AIN   8.8   345   60   13.4
因此，多孔BeO、MgO、Al2O3、Yb2O3、SiC、Si3N4和AlN提供了一种比SiO2性能更佳的膜，因为它们在提供k为2.2的孔隙率下都比SiO2更坚固。
为了提供用于半导体器件的陶瓷膜，首先选择E0大于或等于100GPa的陶瓷材料。该膜的k应当为15或更小。这在图3中显示为30。然后，确定理想的k(例如大约为2.2或更小的k)所需的孔隙率。这产生6GPa或更大的E，如图3中31所示。现在，如32所示，以确定的孔隙率形成多孔陶瓷膜，由此提供理想的k。这就是在表1中为所示的陶瓷材料示出的内容。
陶瓷膜的等离子体增强化学气相沉积(PECVD)是公知的。例如，使用叔丁氧化锆来沉积k＝16的二氧化锆膜(参见Byeong-OkCho，B.-O.，等，Appl.Phys.Lett.，80(16)，2002，1052-1054)。可以使用前体通过PECVD、旋涂、或其它常规沉积技术来沉积该膜，例如使用Al(OC(CH3)4)4来沉积Al2O3膜。其它用来沉积陶瓷材料的商业上可获得的前体可以选自金属醇盐(OR)、乙酸盐(OAc)、丙酮乙酸盐、和六氟丙酮乙酸盐。如果在等离子体中添加例如O2或N2O的氧化剂，则还可以使用烷基金属或烯烃。通常通过在等离子体中添加氨或胺来形成氮化物。
通过在膜中加入碳基聚合物、例如在等离子体中增加乙烯，能够增加孔隙的产生。在后续的下游工艺步骤中可以除去碳基成孔剂(porogen)。例如，如将要结合图4A-4E进行说明的，可以在沉积之后使成孔剂立即热分解，或者甚至在CMP处理之后使成孔剂热分解，以避免在镶嵌工艺中蚀刻多孔材料。可以以其它几种方式来分解成孔剂，例如通过适用于特定成孔剂的等离子体曝光、电子束处理、湿法蚀刻、使用超临界CO2、紫外或红外线辐射、微波或其它后沉积处理。
通过在沉积等离子体中添加第二可聚合成分，可以在该膜中加入成孔剂。或者，可以使用连接至前体的支链来继续等离子体沉积，并能在沉积之后分解。
还可以通过增大沉积速度，例如通过在等离子体中增加更多氧化剂来获得沉积膜的孔隙率，以产生低的膜密度。然而，这导致低密度多孔膜立即形成。
在2004年2月12号公布的题为“Low-k Dielectric Film withGood Mechanical Strength”的U.S.专利公开号20040026783 A1中、2003年2月28号申请的题为“Forming a Dielectric Layer UsingA Hydrocarbon-Containing Precursor”的U.S.专利申请号10/377061中、2003年3月21号申请的题为“Forming a DielectricLayer Using Porogens”的U.S.专利申请号10/394104中、以及2003年12月23号申请的题为“Method and Materials for Self-AlignedDual Damascene Interconnect Structure”的U.S.专利申请号10/746485中介绍了几种形成低密度膜的工艺。
现在参见图4A，示出在下层上形成的包括陶瓷材料和成孔剂的ILD 40，其中仅示出了该下层中的单个导体41和环绕的阻挡层。ILD40可以是混合有成孔剂的表1中示出的任意材料，使得ILD 40的最终孔隙率为如表1中对应的陶瓷材料所示的孔隙率。注意在图4A中，沉积了具有成孔剂的膜，因此它将具有比例如以更高沉积速度沉积的膜更大的强度，从而在初始沉积时多孔化。
现在，如图4B所示，在层40中蚀刻开口，例如在导体41上蚀刻通孔开口46和沟槽45。可以使用在某些时候用来防止过蚀刻的蚀刻剂停止层或硬掩模层，但在附图中未示出。
形成开口之后，如通常在镶嵌工艺中完成的那样，沿着开口形成阻挡金属48。如图4C所示，通常使用钽或钽合金作为该阻挡金属。如果后来形成的金属不会扩散到所选择的陶瓷材料中，则可以不需要这一层。
然后，通过普通电镀工艺将例如铜或铜合金的导体电镀在阻挡层48上。电镀金属还覆盖层40的上表面，并使用CMP将所述电镀金属从该表面除去。得到的结构在图4D中示出，例如，铜50填充沟槽和通孔开口，并通过阻挡材料48与层40隔开。通过这种方式，导体50与导体41接触(in contract with)。
现在如图4E所示，除去成孔剂从而使ILD 40多孔化。得到的层40将具有大约2.2的k、选自该表的陶瓷材料的表1所示的孔隙率和E值。以上述任一方式除去成孔剂。
因此，描述了一种用于低k、较高E层的陶瓷材料。

Claims (20)

1、一种方法，包括：
选择一种陶瓷材料，其具有100Gpa或更大的杨氏模量(E)和15或更小的介电常数(k)；
确定对于6Gpa或更大的E、大约2.2或更小的k，该材料所需的孔隙率；以及
在半导体器件中形成该材料层，其具有所述确定的孔隙率。
2、如权利要求1所述的方法，其中该材料选自BeO、MgO、Al2O3、Yb2O3、SiC、Si3N4和AIN构成的组。
3、如权利要求1所述的方法，其中形成该层包括：
在集成电路中沉积该材料作为层间电介质层(ILD)；
使用镶嵌工艺在该ILD中镶嵌导体；并且
除去成孔剂以提供所述确定的孔隙率。
4、如权利要求2所述的方法，其中形成该层包括：
在集成电路中沉积该材料作为层间电介质层(ILD)；
使用镶嵌工艺在该ILD中镶嵌导体；并且
除去成孔剂以提供所述确定的孔隙率。
5、如权利要求1所述的方法，其中形成该层包括以足够高的沉积速度沉积该材料，以产生所述确定孔隙率的膜。
6、如权利要求5所述的方法，其中在等离子体增强化学气相沉积工艺中进行所述沉积，并且通过向等离子体中添加更多氧化剂来实现增大沉积速度。
7、如权利要求1所述的方法，其中形成该层包括在集成电路中形成具有所述确定孔隙率的ILD，接着利用镶嵌工艺在该层中镶嵌导体。
8、如权利要求7所述的方法，其中形成该层包括形成具有成孔剂的该层并除去该成孔剂。
9、如权利要求7所述的方法，其中形成该层包括以足够高的沉积速度沉积该层，以产生具有所述确定孔隙率的膜。
10、一种方法，包括：
在半导体器件中由陶瓷材料形成层间电介质(ILD)；
在该ILD中镶嵌导体；
减小该ILD的密度，使得其k大约为2.2或更大、且其E为6GPa或更高。
11、如权利要求10所述的方法，其中形成的ILD具有15或更小的k和100或更高的E。
12、如权利要求11所述的方法，其中该材料选自BeO、MgO、Al2O3、Yb2O3、SiC、Si3N4和AlN构成的组。
13、如权利要求10所述的方法，其中形成的ILD包括成孔剂。
14、如权利要求13所述的方法，其中该材料选自BeO、MgO、Al2O3、Yb2O3、SiC、Si3N4和AlN构成的组。
15、一种集成电路，包括：
多孔陶瓷层，该陶瓷材料在非多孔态具有100GPa或更大的杨氏模量(E)和15或更小的介电常数，该多孔陶瓷层具有6GPa或更大的E和大约2.2或更小的介电常数。
16、如权利要求15所述的集成电路，其中该材料选自BeO、MgO、Al2O3、Yb2O3、SiC、Si3N4和AlN构成的组。
17、如权利要求16所述的集成电路，其中该层是层间电介质(ILD)，并且包括利用镶嵌工艺形成的导体。
18、半导体器件中的层间电介质(ILD)，包括：
选自BeO、MgO、Al2O3、Yb2O3、SiC、Si3N4和AlN构成的组中的多孔陶瓷材料，其具有大约2.2或更小的介电常数和6GPa或更大的杨氏模量。
19、如权利要求18所述的ILD，其中该陶瓷材料在非多孔态时具有100GPa或更大的E和15或更小的k。
20、如权利要求19所述的ILD，其中在该ILD中镶嵌导体。
CNA2005800174568A 2004-06-29 2005-06-15 半导体器件中作为低k膜的多孔陶瓷材料 Pending CN1961417A (zh)

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