CN1955882A - Computer system reset circuit - Google Patents
Computer system reset circuit Download PDFInfo
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- CN1955882A CN1955882A CN 200510128444 CN200510128444A CN1955882A CN 1955882 A CN1955882 A CN 1955882A CN 200510128444 CN200510128444 CN 200510128444 CN 200510128444 A CN200510128444 A CN 200510128444A CN 1955882 A CN1955882 A CN 1955882A
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- reset
- computer system
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Abstract
A reset circuit of computer system consists of power supply, reset signal generating circuit with the first output end for outputting the first reset signal and control circuit including a reset signal input end and a control signal input end as well as the second output end. It is featured as inputting the first reset signal to reset signal input end, providing a control signal by control signal input end, generating the second reset signal being outputted through the second output end and being used to control reset of computer system by the first reset signal and said control signal.
Description
[technical field]
The present invention relates to a kind of computer system reset circuit.
[background technology]
Usually computer system has a reset circuit and is used for computer system is carried out reset operation, and common a kind of computer system reset circuit is by the reset signal receiving end that a signal that becomes electronegative potential from noble potential is outputed to computer system computer system to be resetted.
As shown in Figure 1; be an existing computer system reset circuit; power Vcc provides positive voltage; when reset button S ' does not press; reset signal output terminals A ' be always noble potential; it is connected in the reset signal receiving end of computer system; computer system normal operation this moment; when pressing reset button S ' time; reset signal output terminals A ' with ground connection, i.e. reset signal output terminals A ' change electronegative potential into resets computer system thereby produce a reset signal receiving end that becomes the signal of electronegative potential and output to computer system from noble potential; resistance R among Fig. 1 ' the play effect of current limliting, diode D ' and capacitor C ' the play effect of circuit protection.
But, for some reason, probably can press reset button S ' because of carelessness, mistake resets computer system, thereby cause inconvenience to computer system operation, serious also can cause losing of data, if press reset button S ' accidentally when computer system is upgraded to hardware or software, may cause whole computer system damage in addition.
[summary of the invention]
In view of above content, be necessary to provide a kind of computer system reset circuit, in order to avoid causing resetting of computer system because of maloperation with protection mechanism.
A kind of computer system reset circuit, it comprises that a power supply and is used for producing the reset signal generating circuit of one first reset signal, described reset signal generating circuit has one first output terminal, be used for exporting first reset signal, described computer system reset circuit further comprises a control circuit, described control circuit has a reset signal input end, one signal input end and one second output terminal, described first reset signal is input to described reset signal input end, described signal input end is used to provide a control signal, described first reset signal and described control signal are used for producing one second reset signal, and through the output of described second output terminal, described second reset signal is used for resetting of control computer system.
With described reset signal generating circuit with after described control circuit is connected, by setting to described signal input end potential state, can be effective the resetting of control computer system, can avoid again resetting owing to the computer system that maloperation causes.
[description of drawings]
The present invention is further illustrated in conjunction with embodiment below with reference to accompanying drawing.
Fig. 1 is the circuit theory diagrams of existing a kind of computer system reset circuit.
Fig. 2 is the circuit theory diagrams of computer system reset circuit better embodiment of the present invention.
[embodiment]
Please refer to Fig. 2, computer system reset circuit 100 of the present invention is used for a computer system is carried out reset operation, and its better embodiment comprises that a power Vcc, is used for producing the reset signal generating circuit 110 and a control circuit 120 of one first reset signal.Described reset signal generating circuit 110 comprises a resistance R, a diode D, a capacitor C, a reset button S and one first output terminal M, and the described first output terminal M is used for exporting first reset signal.Described control circuit 120 has a reset signal input end N, a signal input end E and one second output terminals A, described first reset signal is input to described reset signal input end N, described signal input end E is used to provide a control signal, described first reset signal and described control signal are used for producing one second reset signal, and through the output of described second output terminals A, described second reset signal is used for resetting of control computer system.In the present embodiment, described control circuit 120 comprises a first transistor Q1, a transistor seconds Q2 and one the 3rd transistor Q3.
Wherein, described power Vcc provides positive voltage to described reset signal generating circuit 110 and described control circuit 120, and the negative electrode of described diode D links to each other with described power Vcc, and anode is connected in an end of described capacitor C, the other end ground connection of described capacitor C; One end of described resistance R links to each other with described power Vcc, and the other end is connected in the end of described reset button S, the other end ground connection of described reset button S; The described first output terminal M is connected in the anode of described diode D, and it also is connected between described resistance R and the described reset button S.
The base stage of described the first transistor Q1 connects described reset signal input end N, and its emitter and collector be ground connection and power Vcc respectively; The collector of described transistor seconds Q2 connects described second output terminal and connects described power Vcc, and its base stage connects the collector of described the first transistor Q1; The base stage of described the 3rd transistor Q3 connects described signal input end E, and its collector and emitter connect emitter and the ground of described transistor seconds Q2 respectively.In the present embodiment, be provided with one first resistance R 1 between the collector of described the first transistor Q 1 and described power Vcc, be provided with one second resistance R 2 between the collector of described transistor seconds Q2 and described power Vcc, the inter-collector of the base stage of described transistor seconds Q2 and the first transistor Q1 is provided with one the 3rd resistance R 3, is provided with one the 4th resistance R 4 between the base stage of described the 3rd transistor Q3 and described signal input end E.
During work, first reset signal of described first output terminal M output is input to described reset signal input end N, described signal input end E is used to provide a control signal (can be with central processing unit process I/O (Process Input Output, PIO) control signal of pattern is as the control signal of described signal input end E, change the potential state of described signal input end E by the control signal of setting described PIO pattern), described second output terminals A is connected in the reset signal receiving end of computer system, second reset signal of its output is used for resetting of control computer system, when described signal input end E is set at electronegative potential, then described the 3rd transistor Q3 will be in cut-off region, thereby described transistor seconds Q2 also is in cut-off region, described second output terminals A will be always noble potential, this moment, no matter which kind of state reset button S was in, computer system is resetted, guaranteed the normal operation of computer system.
When described signal input end E is set at noble potential, then described the 3rd transistor Q3 will be in the saturation region, if this moment, reset button S did not press, first reset signal that is described first output terminal output is a noble potential, the base stage of described the first transistor Q1 will be in noble potential, the first transistor Q1 will be in the saturation region, thereby the base stage that causes described transistor seconds Q2 is an electronegative potential, described transistor seconds Q2 will be in cut-off region, second reset signal of described second output terminals A output will be high potential signal, at this moment the computer system operate as normal.After pressing described reset button S, first reset signal that is described first output terminal output is an electronegative potential, the base stage of described the first transistor Q1 will be in electronegative potential, described the first transistor Q1 will be in cut-off region, the collector of described the first transistor Q1 will be in noble potential, the base stage of described transistor seconds Q2 also will be in noble potential, again because the 3rd transistor Q3 is in the saturation region, and then cause described transistor seconds Q2 to be in the saturation region, second reset signal of described like this second output terminals A output will become low-potential signal from noble potential, thereby produce a reset signal receiving end that becomes the signal of electronegative potential and output to computer system from noble potential computer system be resetted.
When not needing that computer system carried out reset operation, described signal input end E can be set at electronegative potential, and can guarantee by the control of described control circuit 120 no matter which kind of state reset button S is in, second reset signal of described second output terminals A output will be always noble potential, and this moment, computer system can not reset.When needs carry out reset operation to computer system, described signal input end E is set at noble potential, and the control by described control circuit 120 can make first reset signal of described first output terminal M output identical with second reset signal of described second output terminals A output, can computer system be resetted by pressing described reset button S at this moment.
Claims (10)
1. computer system reset circuit, it comprises that a power supply and is used for producing the reset signal generating circuit of one first reset signal, described reset signal generating circuit has one first output terminal, be used for exporting first reset signal, it is characterized in that: described computer system reset circuit further comprises a control circuit, described control circuit has a reset signal input end, one signal input end and one second output terminal, described first reset signal is input to described reset signal input end, described signal input end is used to provide a control signal, described first reset signal and described control signal are used for producing one second reset signal, and through the output of described second output terminal, described second reset signal is used for resetting of control computer system.
2. computer system reset circuit as claimed in claim 1, it is characterized in that: described second reset signal is a voltage signal, and when described second reset signal was noble potential, computer system did not reset, when described second reset signal was electronegative potential, computer system resetted.
3. computer system reset circuit as claimed in claim 2, it is characterized in that: described signal input end is a voltage signal input end, when the voltage signal of described signal input end was electronegative potential, second reset signal of described second output terminal output was always noble potential.
4. computer system reset circuit as claimed in claim 3, it is characterized in that: it is voltage signal that described reset signal generating circuit produces first reset signal, when the input voltage of described signal input end is a noble potential, and when described first reset signal is noble potential, second reset signal of described second output terminal output is a noble potential, and computer system does not reset.
5. computer system reset circuit as claimed in claim 4, it is characterized in that: when the input voltage of described signal input end is a noble potential, and when described first reset signal was electronegative potential, second reset signal of described second output terminal output was an electronegative potential, and computer system resets.
6. computer system reset circuit as claimed in claim 5, it is characterized in that: described reset signal generating circuit has a reset button, when described reset button is not pressed, described first reset signal is a noble potential, when described reset button was pressed, described first reset signal was an electronegative potential.
7. computer system reset circuit as claimed in claim 6 is characterized in that: described reset signal generating circuit also comprises a resistance, a diode and an electric capacity; The negative electrode of described diode links to each other with described power supply, and anode is connected in an end of described electric capacity, the other end ground connection of described electric capacity; One end of described resistance links to each other with described power supply, and the other end is connected in an end of described reset button, the other end ground connection of described reset button; Described first output terminal is connected in the anode of described diode, and it also is connected between described resistance and the described reset button.
8. as any described computer system reset circuit in the claim 1 to 5, it is characterized in that: described control circuit comprises a first transistor, a transistor seconds and one the 3rd transistor; The base stage of described the first transistor connects described reset signal input end, and its emitter and collector be ground connection and described power supply respectively; The collector of described transistor seconds connects described second output terminal and connects described power supply, and its base stage connects the collector of described the first transistor; The described the 3rd transistorized base stage connects described signal input end, and its collector and emitter connect the emitter and the ground of described transistor seconds respectively.
9. computer system reset circuit as claimed in claim 8 is characterized in that: be provided with one first resistance between the collector of described the first transistor and described power supply, be provided with one second resistance between the collector of described transistor seconds and described power supply.
10. computer system reset circuit as claimed in claim 9, it is characterized in that: the base stage of described transistor seconds and the inter-collector of the first transistor are provided with one the 3rd resistance, are provided with one the 4th resistance between the described the 3rd transistorized base stage and described signal input end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101284444A CN100454215C (en) | 2005-10-28 | 2005-12-03 | Computer system reset circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200510100807.3 | 2005-10-28 | ||
| CN200510100807 | 2005-10-28 | ||
| CNB2005101284444A CN100454215C (en) | 2005-10-28 | 2005-12-03 | Computer system reset circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1955882A true CN1955882A (en) | 2007-05-02 |
| CN100454215C CN100454215C (en) | 2009-01-21 |
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ID=38063251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101284444A Expired - Fee Related CN100454215C (en) | 2005-10-28 | 2005-12-03 | Computer system reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100454215C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103391076A (en) * | 2013-07-05 | 2013-11-13 | 曙光信息产业股份有限公司 | Secondary reset circuit and reset method |
| CN102047198B (en) * | 2008-04-02 | 2014-03-26 | S.C.约翰逊父子公司 | Method and system for identifying reset conditions |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06202762A (en) * | 1992-10-30 | 1994-07-22 | Nippon Motorola Ltd | Reset signal generating circuit with write data protecting function |
| CN1159859C (en) * | 2000-12-19 | 2004-07-28 | 中兴通讯股份有限公司 | Reset bus and interface apparatus |
| CN2733830Y (en) * | 2004-08-25 | 2005-10-12 | 英华达(上海)电子有限公司 | Reset circuit capable of preventing radio frequency interference |
-
2005
- 2005-12-03 CN CNB2005101284444A patent/CN100454215C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102047198B (en) * | 2008-04-02 | 2014-03-26 | S.C.约翰逊父子公司 | Method and system for identifying reset conditions |
| CN103391076A (en) * | 2013-07-05 | 2013-11-13 | 曙光信息产业股份有限公司 | Secondary reset circuit and reset method |
| CN103391076B (en) * | 2013-07-05 | 2016-02-10 | 曙光信息产业股份有限公司 | Secondary reset circuit and repositioning method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100454215C (en) | 2009-01-21 |
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| C06 | Publication | ||
| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
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Granted publication date: 20090121 Termination date: 20131203 |