CN1949487A - Packaging structure of flip-chip on film capable of preventing sealing material from overflow - Google Patents
Packaging structure of flip-chip on film capable of preventing sealing material from overflow Download PDFInfo
- Publication number
- CN1949487A CN1949487A CN 200510108619 CN200510108619A CN1949487A CN 1949487 A CN1949487 A CN 1949487A CN 200510108619 CN200510108619 CN 200510108619 CN 200510108619 A CN200510108619 A CN 200510108619A CN 1949487 A CN1949487 A CN 1949487A
- Authority
- CN
- China
- Prior art keywords
- flip
- chip
- film
- encapsulating structure
- encapsulant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title abstract description 7
- 239000003566 sealing material Substances 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000008393 encapsulating agent Substances 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 12
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 229920001187 thermosetting polymer Polymers 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 3
- 230000005496 eutectics Effects 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 2
- 238000004078 waterproofing Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract 2
- 239000000084 colloidal system Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses an on-film flip chip packaging structure, comprising substrate, flip chip, plural raised blocks, first sealing material and barrier, where the substrate has a top surface and plural pins formed on the top surface; the flip chip has an active surface and plural pads formed on the active surface, each pad corresponding to a pin; each raised block is jointed with a pad and a corresponding pin; the first sealing material is coated to cover the periphery of the chip; the barrier is formed on the top surface of the substrate and circles the flip chip to prevent overflow of the first sealing material.
Description
Technical field
The present invention relates to flip-chip encapsulating structure on a kind of film (Flip-chip-on-film packagestructure), particularly relate to flip-chip encapsulating structure on a kind of film that prevents the encapsulant overflow.
Background technology
See also Fig. 1, Fig. 1 is the schematic diagram of the chip-packaging structure 10 of prior art.The chip-packaging structure 10 of prior art comprises substrate 12, chip 14 and spot printing colloid 16.Substrate 12 has upper surface 120 and is formed at trace layer 122 on the upper surface 120.Chip 14 has active face (Activesurface) 140.At least one projection (Bump) 18 is formed on the active face 140 of chip 14.When chip 14 was fixed to substrate 12, these projections 18 formed with the trace layer 122 of substrate 12 and are electrically connected.Application point is coated with colloid 16 to seal these projections 18.
Along with the development of integrated circuit toward microminiaturization, the product area must dwindle to produce minimum finished product area because of the microminiaturization relation, therefore, must control the overflow of gluing.In addition, a plurality of chips 14 can be set usually on the substrate 12, to improve the usefulness of chip-packaging structure 10.Yet when the number of chip 14 increased, the distance of chip and chip chamber just can be reduced, and made when application point is coated with colloid 16, and overflow takes place in regular meeting, and pollutes contiguous chip.
Therefore, main purpose of the present invention is to provide flip-chip encapsulating structure on a kind of film, to address the above problem.
Summary of the invention
One object of the present invention is to provide flip-chip encapsulating structure on a kind of film, flip-chip encapsulating structure utilizes a barricade (Barricade) that is formed on the upper surface of substrate on this film, and around flip-chip (Flip Chip), in order to prevent the overflow of encapsulant.
According to a preferred specific embodiment, flip-chip encapsulating structure comprises substrate, flip-chip chip, a plurality of projection, one first encapsulant and a barricade on the film of the present invention.Substrate has a upper surface and many pins (Lead) that are formed on the upper surface.The flip-chip chip has an active face and is formed at a plurality of weld pads (Pad) on the active face, wherein, and a pin in corresponding these pins of each weld pad in these weld pads.Weld pad in these weld pads of each bump bond and to pin that should weld pad.Be coated with first encapsulant with around the covering flip-chip.Barricade is formed on the upper surface of substrate, and around the flip-chip chip, in order to prevent the overflow of first encapsulant.
Therefore, by flip-chip encapsulating structure on the film of the present invention, the coating encapsulant to be to cover around the flip-chip, because of the restriction of the barricade around flip-chip, and do not have the situation generation of encapsulant overflow.
Can be further understood by the following detailed description and accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 is the schematic diagram of the chip-packaging structure of prior art.
Fig. 2 is the schematic diagram of flip-chip encapsulating structure on the film of the first preferred specific embodiment according to the present invention.
Fig. 3 is the top view of flip-chip encapsulating structure on the film among Fig. 2.
Description of reference numerals
10: chip-packaging structure 12,32: substrate
120,320: upper surface 122: trace layer
14: chip 140,340: active face
16: spot printing colloid 18,36: projection
30: flip-chip encapsulating structure 322 on the film: pin
34: 38: the first encapsulants of flip-chip
40: barricade
Embodiment
See also Fig. 2 and Fig. 3, Fig. 2 is the schematic diagram of flip-chip encapsulating structure 30 on the film of the first preferred specific embodiment according to the present invention.Fig. 3 is the top view of flip-chip encapsulating structure 30 on the film among Fig. 2.Flip-chip encapsulating structure 30 comprises substrate 32, flip-chip 34, a plurality of projection 36, first encapsulant 38 and barricade 40 on the film.Substrate 32 has upper surface 320 and many pins 322 that are formed on the upper surface 320.In this embodiment, substrate 32 can be flexible PCB (Flexible circuit board).Flip-chip 34 has active face 340 and is formed at a plurality of weld pads (not being shown among the figure) on the active face 340, wherein, and a pin 322 in corresponding these pins 322 of each weld pad in these weld pads.Each projection 36 is formed on the active face 340 of flip-chip 34 or is formed on these pins 322, in order to engage in these weld pads weld pad and to pin 322 that should weld pad.In this embodiment, these projections 36 engage with these pins 322 on the substrate 32 in interatomic bond (Interatomic bonding) mode of closing.In another preferred specific embodiment, these projections 36 engage with these pins 322 on the substrate 32 by an eutectic joint technology (Eutectic bonding process) or a ultrasonic heat combined process (Ultrasonic-thermobonding process).These projections 36 can be golden projection (Gold bump) or other like.
As shown in Figure 2, be coated with first encapsulant 38 with cover flip-chip 34 around and these projections 36.In the above-described embodiment, first encapsulant 38 can be underfill (Under-filling material), and first encapsulant 38 has water proofing property.
As Fig. 2 and shown in Figure 3, barricade 40 is formed on the upper surface 320 of substrate 32, and around flip-chip 34, in order to prevent the overflow of first encapsulant 38.In this embodiment, barricade 40 by be selected from resin (Resin) material, non-conductive adhesive (Non-conductive paste, NCP), a kind of material of underfill (Under-filling material) and a weldering resistance material (Solder resistance material) forms.In this embodiment, barricade 40 is formed on the upper surface 320 of substrate 32 by a typography.By this, be coated with first encapsulant 38,, and do not have the situation generation of first encapsulant, 38 overflows because of the restriction of the barricade 40 around flip-chip chip 34 to cover around the flip-chip chip 34.
In another preferred specific embodiment, flip-chip encapsulating structure 30 can further comprise second encapsulant (not being shown among the figure) on the film of the present invention.Second encapsulant is coated between flip-chip 34 and the substrate 32, causes flip-chip 34 to be bonded on the substrate 32.Second encapsulant can be thermosetting (Thermosetting) material, and tool shrinkage when thermosetting, perhaps, second encapsulant is by being selected from non-conductive adhesive, anisotropy conductiving glue (Anisotropic conductive paste, ACP) and an anisotropic conductive film (Anisotropic conductive film, a kind of material ACF) forms.
Compared with the prior art, flip-chip encapsulating structure utilizes a barricade to be formed on the upper surface of substrate on the film of the present invention, and around flip-chip, in order to prevent the overflow of encapsulant, with the size of control encapsulating structure finished product, and avoid adjacent flip-chip to suffer the pollution of encapsulant.
By the detailed description of above preferred specific embodiment, hope can be known description feature of the present invention and spirit more, and is not to come category of the present invention is limited with above-mentioned disclosed preferred specific embodiment.On the contrary, its objective is that hope can contain in the category that is arranged in claims of the present invention of various changes and tool identity property.
Claims (13)
1, flip-chip encapsulating structure on a kind of film comprises:
Substrate, described substrate have a upper surface and many pins that are formed on the described upper surface;
Flip-chip, described flip-chip have active face and are formed at a plurality of weld pads on the described active face, a pin in the corresponding described pin of each weld pad in the described weld pad;
A plurality of projections, a weld pad in the described weld pad of each bump bond in the described projection and the pin of corresponding described weld pad;
First encapsulant, be coated with described first encapsulant with cover described flip-chip around; And
Barricade, described barricade are formed on the described upper surface of described substrate and around described flip-chip, in order to prevent the overflow of described first encapsulant.
2, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described barricade is formed by a kind of material that is selected from resin material, non-conductive adhesive, bottom filling material and weldering resistance material.
3, flip-chip encapsulating structure on the film as claimed in claim 1, wherein said barricade is formed on the upper surface of described substrate by a typography.
4, flip-chip encapsulating structure on the film as claimed in claim 1 further comprises:
Second encapsulant, described second encapsulant is coated between described flip-chip and the described substrate, causes described flip-chip to be bonded on the described substrate.
5, flip-chip encapsulating structure on the film as claimed in claim 4, wherein, described second encapsulant is a kind of thermosets.
6, flip-chip encapsulating structure on the film as claimed in claim 4, wherein said second encapsulant is selected from non-conductive adhesive, anisotropy conductiving glue and anisotropic conductive film.
7, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described first encapsulant is a kind of underfill.
8, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described first encapsulant has water proofing property.
9, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described projection engages with described pin on the described substrate in the interatomic bond mode of closing.
10, flip-chip encapsulating structure on the film as claimed in claim 9, wherein, described projection engages with described pin on the described substrate by an eutectic joint technology or ultrasonic heat combined process.
11, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described projection is formed on the active face of described flip-chip or is formed on the described pin.
12, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described substrate is a kind of flexible PCB.
13, flip-chip encapsulating structure on the film as claimed in claim 1 wherein, is coated with described first encapsulant to cover described projection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510108619 CN1949487A (en) | 2005-10-10 | 2005-10-10 | Packaging structure of flip-chip on film capable of preventing sealing material from overflow |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510108619 CN1949487A (en) | 2005-10-10 | 2005-10-10 | Packaging structure of flip-chip on film capable of preventing sealing material from overflow |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1949487A true CN1949487A (en) | 2007-04-18 |
Family
ID=38018940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510108619 Pending CN1949487A (en) | 2005-10-10 | 2005-10-10 | Packaging structure of flip-chip on film capable of preventing sealing material from overflow |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1949487A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254837A (en) * | 2011-04-29 | 2011-11-23 | 永道无线射频标签(扬州)有限公司 | Packaging process of electronic tag inversely stuck sheet packaging production line |
| CN101335253B (en) * | 2007-06-27 | 2012-06-13 | 新光电气工业株式会社 | Semiconductor package and semiconductor device using the same |
| CN102637612A (en) * | 2012-05-03 | 2012-08-15 | 福建华映显示科技有限公司 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
| CN103098190A (en) * | 2010-09-09 | 2013-05-08 | 超威半导体公司 | Semiconductor chip device with underfill |
| CN103985807A (en) * | 2013-02-07 | 2014-08-13 | 罗容 | Inorganic substrate and manufacturing method thereof |
| CN104733402A (en) * | 2013-12-19 | 2015-06-24 | 矽品精密工业股份有限公司 | Semiconductor package structure and method for fabricating the same |
| CN108281409A (en) * | 2018-01-11 | 2018-07-13 | 苏州通富超威半导体有限公司 | One kind can reduce encapsulation chip size packages substrate and the preparation method and application thereof |
| CN109729746A (en) * | 2016-09-01 | 2019-05-07 | 奥斯兰姆奥普托半导体股份有限两合公司 | Device with carrier and optoelectronic components |
| CN112638025A (en) * | 2019-10-08 | 2021-04-09 | 南茂科技股份有限公司 | Flexible circuit substrate and chip-on-film package structure |
-
2005
- 2005-10-10 CN CN 200510108619 patent/CN1949487A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101335253B (en) * | 2007-06-27 | 2012-06-13 | 新光电气工业株式会社 | Semiconductor package and semiconductor device using the same |
| CN103098190A (en) * | 2010-09-09 | 2013-05-08 | 超威半导体公司 | Semiconductor chip device with underfill |
| CN102254837A (en) * | 2011-04-29 | 2011-11-23 | 永道无线射频标签(扬州)有限公司 | Packaging process of electronic tag inversely stuck sheet packaging production line |
| CN102637612A (en) * | 2012-05-03 | 2012-08-15 | 福建华映显示科技有限公司 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
| CN102637612B (en) * | 2012-05-03 | 2014-07-30 | 福建华映显示科技有限公司 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
| CN103985807B (en) * | 2013-02-07 | 2016-12-28 | 深圳大道半导体有限公司 | Inorganic substrate and manufacture method thereof |
| CN103985807A (en) * | 2013-02-07 | 2014-08-13 | 罗容 | Inorganic substrate and manufacturing method thereof |
| CN104733402A (en) * | 2013-12-19 | 2015-06-24 | 矽品精密工业股份有限公司 | Semiconductor package structure and method for fabricating the same |
| CN109729746A (en) * | 2016-09-01 | 2019-05-07 | 奥斯兰姆奥普托半导体股份有限两合公司 | Device with carrier and optoelectronic components |
| US10629578B2 (en) | 2016-09-01 | 2020-04-21 | Osram Oled Gmbh | Arrangement having a carrier and an optoelectronic component |
| CN109729746B (en) * | 2016-09-01 | 2020-07-10 | 奥斯兰姆奥普托半导体股份有限两合公司 | Device with carrier and optoelectronic component |
| CN108281409A (en) * | 2018-01-11 | 2018-07-13 | 苏州通富超威半导体有限公司 | One kind can reduce encapsulation chip size packages substrate and the preparation method and application thereof |
| CN112638025A (en) * | 2019-10-08 | 2021-04-09 | 南茂科技股份有限公司 | Flexible circuit substrate and chip-on-film package structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1949487A (en) | Packaging structure of flip-chip on film capable of preventing sealing material from overflow | |
| US6214642B1 (en) | Area array stud bump flip chip device and assembly process | |
| US7838334B2 (en) | Package-on-package device, semiconductor package and method for manufacturing the same | |
| CN101221946B (en) | Manufacture method of semiconductor package, system package module | |
| JP2541487B2 (en) | Semiconductor device package | |
| US7148560B2 (en) | IC chip package structure and underfill process | |
| JP3822040B2 (en) | Electronic device and manufacturing method thereof | |
| CN102903691B (en) | Semiconductor device, method for packing and structure | |
| KR20050119414A (en) | Stacked package comprising two edge pad-type semiconductor chips and method of manufacturing the same | |
| KR20090039411A (en) | Semiconductor package, module, system having a solder ball being coupled to a chip pad and manufacturing method thereof | |
| JP2003078105A (en) | Stacked chip module | |
| JP2013038106A (en) | Semiconductor device and manufacturing method of semiconductor device | |
| CN100431143C (en) | Semiconductor encapsulation structure | |
| KR20080005735A (en) | Package on package and method for a manufacturing the same | |
| JP2003243605A (en) | Semiconductor device and manufacturing method thereof, circuit board and electronic instrument | |
| CN1355568A (en) | Chip stack package structure | |
| CN1885528A (en) | Flip-chip packaging structure | |
| CN201229937Y (en) | Flip chip encapsulation construction having non-array projection | |
| KR20020015214A (en) | Semiconductor package | |
| JP2010147225A (en) | Semiconductor device and its manufacturing method | |
| JP2003158215A (en) | Semiconductor device and its manufacturing method | |
| JP4324773B2 (en) | Manufacturing method of semiconductor device | |
| CN102556938B (en) | Stacked die package structure and manufacturing method thereof | |
| JP2007173655A (en) | Semiconductor device | |
| CN101303985B (en) | Stack type chip packaging structure production method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |