CN1938858A - 具有横向调制栅极功函数的半导体器件和制备方法 - Google Patents
具有横向调制栅极功函数的半导体器件和制备方法 Download PDFInfo
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- CN1938858A CN1938858A CNA2005800108566A CN200580010856A CN1938858A CN 1938858 A CN1938858 A CN 1938858A CN A2005800108566 A CNA2005800108566 A CN A2005800108566A CN 200580010856 A CN200580010856 A CN 200580010856A CN 1938858 A CN1938858 A CN 1938858A
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- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims description 66
- 239000002184 metal Substances 0.000 claims description 66
- 239000010410 layer Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 34
- 239000004020 conductor Substances 0.000 claims description 25
- 238000005516 engineering process Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 17
- 239000002245 particle Substances 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 5
- 239000011777 magnesium Substances 0.000 claims description 4
- 238000004062 sedimentation Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052706 scandium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052749 magnesium Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- 229910052726 zirconium Inorganic materials 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 description 13
- 239000007772 electrode material Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 230000004913 activation Effects 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- -1 phosphorus atoms ion Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Thin Film Transistor (AREA)
Abstract
一种晶体管包括在形成于衬底上的栅电介质层上形成的栅电极。在栅电极的横向相对侧壁的相对侧上的衬底中形成一对源/漏区。栅电极具有形成于栅电介质层上和源区与漏区之间的衬底区上方的中心部分,以及与一部分源/漏区重叠的一对侧壁部分,其中中心部分具有第一功函数,并且所述侧壁部分对具有第二功函数,其中第二功函数与第一功函数不同。
Description
技术领域
本发明涉及半导体制造领域,更尤其涉及一种具有横向调制栅极功函数的金属绝缘半导体场效应晶体管。
背景技术
图1示出了一种金属绝缘的绝缘半导体场效应晶体管(MISFET)100。MISFET 100包括形成于栅电介质层120上的栅电极150,其又形成于硅衬底102上。晶体管100包括沿着栅电极150的横向相对的侧壁形成于衬底102上的一对源/漏区。一般源/漏区均包括浅的源/漏延伸或尖端区140和相对深的源/漏接触区110,如图1所示。沿着栅电极140的横向相对的侧壁形成一对侧壁间隔物130。使用侧壁间隔物130来掩蔽源/漏尖端注入不受重源/漏注入的影响。位于栅电极的下面和源/漏延伸140之间的硅衬底102的部分限定了器件的沟道区114。栅电极150一般略微延伸超过源/漏延伸或尖端区140,如图1所示。栅电极150一般由掺杂的多晶硅形成。可替换地,栅电极可以由金属膜形成。由于多耗尽效应的消除和沟道上方栅极控制的随后改善,金属栅电极150在下一代很可能成为主流技术。栅电极可以由单膜或复合叠置膜形成。然而,栅电极150跨越器件具有恒定或均匀的功函数。也就是说,栅电极的功函数跨越沟道区从一个源/漏区到另一个源/漏区是恒定的。
附图说明
图1示出了一种常规的晶体管。
图2示出了根据本发明的实施例具有调制栅极功函数的金属绝缘半导体场效应晶体管(MISFET)的截面图。
图3A-3K示出了根据本发明的实施例形成具有调制栅极功函数的晶体管的方法。
图4A-4D示出了根据本发明的实施例形成具有调制栅极功函数的晶体管的方法。
具体实施方式
本发明是一种具有横向调制栅极功函数的金属绝缘半导体场效应晶体管(MISFET)及制备方法。在以下描述中,已列出许多具体细节,以提供对本发明的彻底理解。在其它情况下,没有特别详细地列出公知的半导体制备工艺和技术,以避免不必要地模糊本发明。
本发明的实施例是具有横向调制栅极功函数的金属绝缘体半导体场效应晶体管(MISFET)及其制备方法。通过提供尖端或源/漏延伸区中减小的串联电阻和通过提供器件的源极端附近的阈值电压的更大控制来增强源注入效率,横向调制栅极功函数改善了MISFET的性能。
本发明实施例中的MISFET器件200的例子示于图2中。可以在半导体衬底例如硅衬底202上形成晶体管200。晶体管200具有形成于半导体衬底202中的一对源/漏区204。源/漏区204均包括浅的尖端或源/漏延伸区206和深的源/漏接触区208。晶体管200包括栅电介质层210,其形成在半导体衬底202上。在本发明的实施例中,栅电介质层是高K电介质,例如、但不限于金属氧化物电介质,例如氧化钽、氧化钛、氧化锆和氧化铪。在栅电介质层210上形成栅电极220,如图2所示。位于栅电极/栅电介质层下面和源/漏区204之间的半导体衬底202是器件的沟道区214,其中导电反型层形成以使电流在源/漏区204之间行进。沿着栅电极220的横向相对的侧壁形成一对侧壁间隔物216。
栅电极220具有一对侧壁或重叠部分222和中心部分224。重叠或侧壁部分222由具有第一功函数的第一导电材料形成,中心部分224由具有第二功函数的第二导电材料形成,其中第二功函数不同于第一功函数。栅电极220可以被说成是具有调制的功函数,因为外部的侧壁部分222具有一个功函数,以及中心部分作为第二个不同的功函数。另外,栅电极220可以被说成是双金属的栅电极,因为侧壁或重叠部分222可以由第一金属形成,且中心部分224可以由第二个不同的金属形成。
在本发明的实施例中,在源/漏区204的一部分上方形成重叠部分222,其在栅电极220下面延伸。在本发明的实施例中,在下面的源/漏延伸区206的上方形成侧壁或重叠部分222。在本发明的实施例中,重叠部分基本上覆盖或形成与下面的源/漏延伸或尖端区206基本对准,如图2所示。在本发明的实施例中,大部分的沟道区214由栅电极220的中心部分224覆盖和控制。在本发明的实施例中,中心部分222与晶体管沟道区214近似对准,如图2所示。在本发明的实施例中,中心部分224包括至少50%的栅电极长度且理想地至少70%的栅电极长度220。在本发明的实施例中,栅电极的中心部分224的功函数支配该器件的截止状态特性。
在本发明的实施例中,晶体管200是n型晶体管,其中多数载流子是电子。当晶体管200是n型晶体管时,将源/漏区204掺杂成一般在.001-.011/μΩ-cm之间的n型电导率,以及将衬底202的沟道区214掺杂成在1-1001/Ω-cm之间的p型电导率。在本发明的实施例中,当晶体管200是n型晶体管时,中心部分224由具有适合于n型器件的功函数的导电材料形成。在本发明的实施例中,当晶体管200是n型晶体管时,栅电极220的中心部分224由具有在3.9至4.3eV之间的功函数的导电材料形成。在本发明的实施例中,晶体管200是n型晶体管,且栅电极的中心部分224由选自包括多晶硅、钛(Ti)、锆(Zr)、铪(Hf)、钽(Ta)和铝(Al)的组的材料形成。在本发明的实施例中,晶体管200是n型晶体管,其中外部部分222由具有在1.5至3.8eV之间的功函数的材料形成。在本发明的实施例中,晶体管200是n型晶体管,并且栅电极220的重叠部分222由选自包括钪(Sc)、镁(Mg)和钇(Y)的组的材料形成。在本发明的实施例中,当晶体管200是n型晶体管时,栅电极220的重叠部分222由具有小于形成栅电极220的中心部分224的材料的功函数至少0.1eV且理想地0.5eV的功函数的材料形成。
在n型晶体管中,通过保持尖端区上方的重叠部分222的功函数低于中心部分224的功函数,在固定的栅电压下增加了多数载流子密度,由此通过减小的Rexternal来减小尖端电阻,其转换成器件性能。另外,降低器件的源极端附近的栅电极的功函数获得了较高的载流子总数(通过较低的源极和阈值电压),同时使器件200的截止状态特性由栅电极的中心部分224的功函数支配。以这种方式,可以改善晶体管200的电特性和性能。
在本发明的实施例中,晶体管200是p型晶体管,其中多数载流子是空穴。当晶体管200是p型晶体管时,源/漏区204可以掺杂成一般在.001-.011/μΩ-cm之间的p型电导率,同时将衬底202的沟道区214掺杂成在1-2001/Ω-cm之间的n型电导率。在本发明的实施例中,当晶体管200是p型晶体管时,中心部分224由具有适合于p型器件的功函数的材料形成。在本发明的实施例中,晶体管200是p型晶体管,其中中心部分224由具有在4.9至5.3电子伏特之间的功函数的材料形成。在本发明的实施例中,晶体管200是p型晶体管,其中栅电极220的中心部分224由选自包括钌(Ru)和钯(Pd)的组的材料形成。在本发明的实施例中,晶体管200是p型晶体管,且栅电极220的外部部分222由具有在5.4至6.0电子伏特之间的功函数的材料形成。在本发明的实施例中,当晶体管200是P型晶体管时,其中栅电极220的外部部分222由选自包括多晶硅、铂(Pt)和氮化钌(RuN)的组的材料形成。在本发明的实施例中,当晶体管200是p型晶体管时,栅电极220的外部部分222具有比中心部分224的功函数大至少0.1eV且理想地大0.5eV电子伏特的功函数。
图3A-3J示出了根据本发明的实施例利用取代栅极工艺形成具有横向调制功函数的栅电极的晶体管的方法。
制备工艺开始于半导体衬底300。在本发明的实施例中,半导体衬底300是单晶硅衬底或晶片。然而,半导体衬底300可以是其它类型的衬底,例如,绝缘体上硅衬底、锗衬底、砷化镓衬底、InSb衬底、GaP衬底、GaSb衬底、和碳纳米管。当制备n型晶体管或NMOS晶体管时,可以将衬底掺杂成p型电导率。当制备p型晶体管或PMOS晶体管时,可以将衬底掺杂成n型电导率。在本发明的实施例中,当制备n型晶体管时,用硼原子将硅单晶衬底掺杂到在1015-1017cm-3之间的浓度。在本发明的实施例中,当形成p型晶体管时,用砷或磷原子将硅单晶衬底掺杂到在1015-1017cm-3之间的浓度。
接下来,在衬底300的上方形成牺牲栅电介质层302。牺牲栅电介质层302可以是任何公知的电介质层,例如、但不限于生长的或沉积的氧化硅层或沉积的氮化硅层。接下来,如图3A所示,在牺牲栅电介质层302的上方形成牺牲栅电极材料304。将牺牲栅电极材料304形成为大约器件的栅电极所希望的厚度。牺牲栅电极材料304由可以选择性地去除或刻蚀掉的材料形成,而在取代栅极工艺期间没有刻蚀掉相邻的层间电介质,例如氧化硅膜或氮化硅膜。另外,牺牲栅电极材料理想上是可以在用于形成器件的源极和漏极的离子注入步骤期间掩蔽沟道区的材料。在本发明的实施例中,牺牲栅电极材料是多晶硅。在本发明的实施例中,将牺牲栅电极材料形成为随后形成的栅电极的厚度所希望的厚度。在本发明的实施例中,牺牲栅电极材料304形成为在400和2000之间的厚度。
接下来,如图3B所示,将栅电极材料304图案化成牺牲栅电极306。将牺牲栅电极306基本上图案化成器件的栅电极所希望的长度和宽度。可以利用公知的光刻和刻蚀技术图案化栅电极材料。
接下来,在衬底300中形成一对源/漏延伸或尖端区308,如图3B所示。当形成n型器件时,尖端区由n型电导率形成,以及当形成p型器件时,尖端区由p型电导率形成。在本发明的实施例中,尖端或源/漏延伸308形成为在1019-1021cm-3之间的浓度。可以通过将硼原子离子注入到衬底308中形成P型源/漏延伸308,以及可以通过将砷或磷原子离子注入到衬底308中形成n型源/漏延伸308。牺牲栅电极306掩蔽沟道区不受离子注入工艺的影响,以使沟道区309对于n型器件保持p型以及对于p型器件保持n型。离子注入将掺杂剂置于与牺牲栅电极306的外边缘基本对准。如果需要,此时能激活源/漏延伸,或者可以在深的源/漏接触形成步骤期间或其它随后的工艺、例如硅化物形成步骤期间激活它们。激活工艺将导致掺杂剂原子在牺牲栅电极的外边缘的下方略微扩散,如图3B所示。可利用任何公知的激活退火例如快速热退火或炉退火来激活掺杂剂以形成源/漏延伸308。
接下来,沿着牺牲栅电极306的横向相对的侧壁形成一对侧壁间隔物310,如图3C所示。侧壁间隔物310可以是任何公知的电介质,例如氧化硅或氮化硅或其组合。侧壁间隔物310可以通过下述形成,即在衬底300的上方,包括牺牲栅电介质层302、牺牲栅电极306的侧壁和牺牲栅电极306的顶表面,毯式(blanket)沉积共形的电介质或复合电介质,然后各向异性地回刻蚀(etch back),以便侧壁间隔物材料从水平表面被去除,但保持与垂直表面例如牺牲栅电极306的侧壁邻近以形成侧壁间隔物310。侧壁间隔物310的宽度大约等于沉积在衬底上方的侧壁间隔物膜的厚度。通常将侧壁间隔物310形成为源/漏延伸的长度所希望的宽度。
在形成侧壁间隔物310之后,可以形成源/漏接触区312。当形成n型器件时,重的源/漏接触区312是n型电导率,以及当形成p型器件时,重的源/漏接触区是p型电导率。在本发明的实施例中,将重的源/漏接触区形成为在1020-1021cm-3之间的浓度。应当理解,重的源/漏接触区312比相对浅的源/漏延伸308更深地形成到衬底中,如图3C所示。可以通过公知的离子注入技术形成重的源/漏接触区312。侧壁间隔物310掩蔽源/漏延伸区308不受重且深的源/漏接触区注入步骤的影响并防止它们被重的源/漏注入埋没。重的源/漏注入步骤将掺杂剂置于与侧壁间隔物310的外边缘基本对准。随后用于激活掺杂剂的退火将导致掺杂剂在侧壁间隔物310的下方略微扩散,如图3C所示。可以利用任何公知的激活退火例如高温快速热工艺或炉退火,来激活掺杂剂并形成重掺杂的源/漏接触区312,如图3C所示。应当理解,源/漏接触区312和源/漏延伸308一起形成器件的源/漏区。
接下来,将层间电介质(ILD)毯式沉积在衬底300的上方,包括牺牲栅电极层302、牺牲栅电极306和侧壁间隔物310。层间电介质层314由可以相对于牺牲栅电极材料306被选择性刻蚀的材料形成。也就是说,电介质层314由没有被用于刻蚀掉牺牲栅电极306的刻蚀剂显著刻蚀的材料形成。在本发明的实施例中,ILD314是二氧化硅膜。将ILD314沉积到比牺牲栅电极306的厚度大的厚度,以便可以将层间电介质层314随后回抛光到牺牲栅电极306的高度。在沉积ILD314之后,回平坦化ILD314以便暴露牺牲栅电极306的顶表面并且使层间电介质314的顶表面与牺牲栅电极306的顶表面在同一平面上,如图3D所示。可以用公知的化学机械平坦化或等离子体回刻蚀工艺来完成层间电介质314的平坦化。
接下来,如图3E所示,去除牺牲栅电极306以形成开口或沟槽316。用刻蚀剂去除牺牲栅电极306,该刻蚀剂刻蚀掉牺牲栅电极306,而没有显著地刻蚀掉ILD314和间隔物310。当ILD314是氧化膜,间隔物310是氧化物或氮化硅或其组合,且牺牲栅电极306是多晶硅时,可以使用包括NH4OH或TMAH的湿法刻蚀剂。栅极去除刻蚀剂优选具有对ILD和间隔物的至少20∶1的选择性。另外,如图3E所示,此时可以去除开口316中的牺牲栅电介质层302,以便可以在衬底300上形成新的栅电介质层。可替换地,在本发明的实施例中,代替形成如图3A所示的牺牲栅电介质层302,可以在图3A的处理期间形成器件的永久的栅电介质层。这样,如果需要,则可以利用高温工艺来形成栅电介质层。在这种情况下,如图3A形成的栅电介质层将保持在开口316中的衬底300上,并且将在其上形成栅电极。
接下来,如图3F所示,在衬底300上形成栅电介质层318。在本发明的实施例中,栅电介质层318是高介电常数(高K)电介质膜,例如、但不限于金属氧化物,例如氧化钛、氧化钽、氧化锆、氧化铪,或其它高K型膜,例如PZT和BST。可以使用任何公知的技术来沉积高K电介质膜,例如化学汽相沉积。在本发明的实施例中,将具有比10大的介电常数的高K电介质膜沉积到在10和50之间的厚度。可替换地,利用公知的工艺例如湿法/干法氧化工艺,可以在沟槽316中的衬底300的暴露表面上生长电介质膜,例如二氧化硅或氮氧化硅膜。当沉积栅电介质时,其不仅形成在衬底300上,而且形成在开口316的侧壁上以及ILD314和间隔物310的顶表面上,如图3F所示。当生长栅电介质层时,其将仅形成在衬底300的暴露表面上。
接下来,如图3G和3H所示,在栅极开口316的外边缘或侧壁上形成具有第一功函数材料的第一金属或导电材料,如图3G和3H所示。在本发明的实施例中,采用两部分式工艺溅射沉积第一金属或导电材料320。在沟槽316的一个侧壁上溅射沉积第一金属膜的第一部分,如图3G所示。在本发明的实施例中,以角度Φ1溅射沉积第一金属320。选择角度Φ1使得溅射的金属膜仅形成在开口316的侧壁之一上,如图3G所示。第一沉积工艺使用该溅射角度(Φ1),其致使第一金属仅沉积在一个侧壁上。选择该角度使得栅极开口316的中心和第二侧壁被电介质层314沟槽掩蔽。接下来,使用第二溅射沉积工艺将第一金属320的第二部分沉积到开口316的第二侧壁或面上。与第一溅射沉积工艺类似,第二溅射沉积工艺以角度Φ2溅射金属320,其致使第一金属仅沉积在栅极开口316的第二面或侧壁上。也就是说,在第二溅射沉积工艺期间,选择角度Φ2使得第一面或侧壁被沟槽掩蔽。要注意,由于第一溅射沉积工艺在ILD314(和栅电介质318)的顶表面315上形成金属膜,所以必需调节第二沉积工艺的角度(Φ2),以负责在第一沉积工艺期间形成在ILD314上的增加的厚度。在本发明的实施例中,第一金属膜的第一部分以第一溅射角度Φ1沉积,其小于用于沉积第一金属膜的第二部分的第二溅射角度Φ2。在本发明的实施例中,第一溅射角度Φ1在45°和80°之间,以及第二溅射角度Φ2在45°-80°之间。
ILD的溅射角度厚度和沟槽316的宽度都决定了第一金属膜320将从侧壁朝着沟槽316的中心延伸多远。在本发明的实施例中,沉积第一金属膜320以便其形成重叠或侧壁部分322,其覆盖或叠置于至少一部分尖端或源/漏延伸上。在本发明的实施例中,沉积第一金属膜以使它形成重叠或侧壁部分322,其覆盖并且与下面的尖端区308基本对准,如图3H所示。在本发明的又一实施例中,沉积第一金属膜以使它覆盖栅电极下面的整个尖端区并且略微延伸到器件的沟道区309中。
在本发明的实施例中,如图3I所示,可以通过将第一金属膜暴露于活性粒子来改变第一金属膜320的功函数。可以通过例如等离子体工艺、远程等离子体工艺、有角度的离子注入、化学处理或热退火来产生或提供活性粒子。在本发明的实施例中,活性粒子与第一金属膜反应以增加沉积的第一金属膜的功函数。在本发明的替换实施例中,活性粒子与第一金属膜反应以降低第一金属膜320的功函数。可以用于改变金属膜的功函数的活性粒子的例子包括但不限于强的Al、Sc、Y、Pt、N、O、Cl、F。
接下来,如图3J所示,沉积具有第二功函数的第二金属或导电材料324以填充沟槽316,如图3J所示。将第二金属膜沉积到沟槽316的中心部分中的栅电介质层318上。将第二金属膜324沉积到一厚度并且通过足以完全填充侧壁或重叠部分322之间的沟槽316的方法沉积,如图3J所示。在本发明的实施例中,第二金属膜324具有比第一金属膜或暴露第一金属膜的活性粒子高的功函数。在本发明的实施例中,第二金属膜322由具有比第一金属膜或暴露第一金属膜的活性粒子低的功函数的金属膜形成。要注意,在本发明的实施例中,用于形成重叠或侧壁部分322的第一导电材料320可以是与用于形成中心部分的相同的导电材料,但然后在图3I所示的处理期间暴露到活性粒子以改变功函数,使得重叠部分322具有与中心部分324不同的功函数。沟槽316的中心部分可以用任一适合的技术来填充,包括共形的沉积工艺,例如但不限于化学汽相沉积(CVD)、等离子体增强化学汽相沉积(PECVD)和原子层沉积(ALD)。这些共形的工艺还将第二金属膜324形成在形成于ILD314上(或者是在栅电介质层318上,当其形成于ILD314上时)的第一金属膜320的顶表面上。接下来,从ILD314去除第二金属膜324和第一金属膜320(以及栅电介质层318,当其形成于ILD314上时),以形成具有横向调制栅极功函数的栅电极326,如图3K所示。第二金属膜324和第一金属膜320可以通过任何公知的工艺来去除,例如化学机械平坦化或等离子体回刻蚀。回平坦化该衬底直至沟槽324中的金属膜的顶表面与ILD314基本在同一平面上为止。这完成了包括具有横向调制栅极功函数的金属栅电极的MISFET器件的制备。
可以使用随后的公知工艺来形成层间电介质和金属互连,以在功能集成电路中将制备的形成于衬底300上的MISFET晶体管电耦接在一起。
图4A-4D示出了根据本发明的实施例形成具有横向调制栅电极的MISFET的替换方法。图4A示出了在先前已经通过如所示获得图3F的衬底的技术处理之后的衬底300。
接下来,具有第一功函数的第一金属膜410沉积在ILD314上方并且邻近沟槽316的侧壁以及沉积在沟槽316中的沟道区309上方的栅电介质层318上,如图4A所示。在本发明的实施例中,具有第一功函数的第一金属膜410通过共形的工艺形成,使得金属膜在垂直表面例如沟槽316的侧壁上形成为与在水平表面例如ILD314(或栅电介质318)的顶表面上和沟槽309的底部中基本相同的厚度。可以使用可以沉积共形膜的任何公知的技术,例如但不限于化学汽相沉积(CVD)、等离子体增强化学汽相沉积(PECVD)、和原子层沉积(ALD),来沉积第一金属膜410。接下来,如图4B所示,对第一金属膜410进行各向异性回刻蚀工艺。各向异性回刻蚀工艺从水平表面例如ILD314(和电介质层318)的顶部以及从沟槽316中的沟道区309上方的电介质层318去除金属410,如图4B所示。第一金属层410的各向异性回刻蚀工艺留下邻近垂直表面例如沟槽316的侧壁的金属膜410,以形成栅电极的重叠或侧壁部分420。栅电极420的重叠部分或侧壁部分420的宽度基本上等于沉积在图4A中的衬底上方的第一金属膜410的厚度。共形沉积工艺之后的各向异性回刻蚀提供了一种简单方法来控制源/漏尖端区308上方的侧壁或重叠部分420的重叠量。可利用任何公知的各向异性回刻蚀技术,例如等离子体刻蚀或反应性离子刻蚀。
接下来,如果需要,可将栅电极的重叠部分420暴露于活性粒子421以改变重叠或侧壁部分420的功函数。可利用任何公知的技术,例如离子注入、快速热退火、等离子体处理和远程等离子体处理,来在第一金属部分420中引入或制造活性粒子,以降低或增加重叠栅电极部分420的功函数。接下来,如图4D所示,具有第二功函数的第二金属膜422可以毯式沉积在图4C中所示的衬底上方,然后通过例如化学机械平坦化或等离子体回刻蚀进行回平坦化,以形成横向调制的栅电极424的中心部分422。在本发明的实施例中,用于形成栅电极422的中心部分的金属膜422具有第二功函数,其比用于形成外部部分420的金属的第一功函数高。在本发明的替换实施例中,中心部分422用具有第二功函数的第二金属膜形成,其小于用于形成栅电极424的外部部分420的金属的功函数。另外,在本发明的实施例中,重叠部分420最初可以由用于形成中心部分422的相同的导电材料形成,但通过在图4C中列出的工艺期间曝光和与活性粒子相互作用,可以具有其改变或调制到不同值的功函数。
Claims (28)
1.一种晶体管,包括:
栅电极,其形成在形成于衬底上的栅电介质层上;
一对源/漏区,其形成在所述栅电极的所述横向相对侧壁的相对侧上的所述衬底中;以及
其中所述栅电极具有形成于所述源/漏区之间的衬底区上方的栅电介质层上的中心部分和与一部分所述源/漏区重叠的一对侧壁部分,其中所述中心部分具有第一功函数,并且所述侧壁部分对具有第二功函数,其中所述的第二功函数与所述的第一功函数不同。
2.如权利要求1的晶体管,其中所述的源/漏区是n型电导率,并且其中所述的中心部分具有在3.9至4.3eV之间的第二功函数。
3.如权利要求2的晶体管,其中所述栅电极的所述侧壁部分具有在1.5至3.8eV之间的功函数。
4.如权利要求1的晶体管,其中所述的源/漏区由n型电导率形成,并且所述的外部部分具有第一功函数,其比所述中心部分低至少0.1eV。
5.如权利要求1的晶体管,其中所述的源/漏区由p型电导率形成,并且其中所述的中心部分具有在4.9至5.3eV之间的功函数。
6.如权利要求5的晶体管,其中所述的侧壁部分具有在5.4至6.0eV之间的功函数。
7.如权利要求1的晶体管,其中源/漏区是p型电导率,并且所述的侧壁部分具有比所述中心部分的功函数高至少0.1eV的功函数。
8.如权利要求1的晶体管,其中源/漏区是n型电导率,并且其中所述栅电极的所述侧壁部分由选自包括钪(Sc)、镁(Mg)和钇(Y)的组的材料形成。
9.如权利要求1的晶体管,其中源/漏区是n型电导率,并且所述栅电极的中心部分包括选自包括多晶硅、钛、锆、铪、钽、和铝的组的导电材料。
10.如权利要求1的晶体管,其中所述源/漏区是p型电导率,并且其中所述栅电极的所述侧壁部分包括选自包括多晶硅、铂和氮化钌(RuN)的组的导电材料。
11.如权利要求1的晶体管,其中所述源/漏区是p型电导率,并且所述中心部分由选自包括钌和钯的组的材料形成。
12.一种形成晶体管的方法,包括:
在半导体衬底上方的电介质膜中形成开口,所述开口具有在形成于所述衬底中的一对源/漏区上方形成的第一和第二横向相对的侧壁,所述开口具有形成在所述源/漏区之间的所述衬底上方的中心部分;
在所述开口中的所述衬底上方形成栅电介质层;
邻近所述栅电介质上面和所述开口的所述第一侧壁以第一角度沉积具有第一功函数的第一导电材料;
在所述栅电介质层上面并邻近所述第二横向相对的侧壁以第二角度溅射沉积所述第一导电材料;以及
在所述沟道区上方的所述栅电介质层上的所述开口的所述中心部分中沉积具有第二功函数的第二导电材料。
13.如权利要求12的方法,其中所述第一角度不同于所述第二角度。
14.如权利要求13的方法,其中所述第二角度大于所述第一角度。
15.如权利要求12的方法,其中在所述第一和第二侧壁上沉积所述第一导电膜之后,将所述第一导电材料暴露于活性粒子以改变所述第一功函数。
16.如权利要求15的方法,其中通过选自包括等离子体产生、离子注入、和热激活的组的工艺产生或提供所述活性粒子。
17.如权利要求15的方法,其中所述活性粒子增加了所述第一导电材料的功函数。
18.如权利要求15的方法,其中所述活性粒子降低了所述第一导电材料的功函数。
19.一种形成晶体管的方法,包括:
在半导体衬底上方的电介质膜中形成开口,所述开口具有在形成于所述衬底中的一对源/漏区上方形成的第一和第二横向相对的侧壁和形成于所述源/漏区之间的沟道区上方的中心部分;
在所述开口中的所述半导体衬底上方形成栅电介质层;
在所述电介质膜的所述顶表面上方、邻近所述的第一和第二侧壁以及在所述开口中的所述栅电介质层上,沉积具有第一功函数的第一导电材料;
各向异性刻蚀所述第一导电材料,以从所述层间电介质的顶表面和从所述开口的中心部分去除所述第一导电材料,以形成邻近所述第一和第二侧壁的一对侧壁部分;以及
在所述栅电介质层上方的所述开口的所述中心部分中的所述栅电介质层上,沉积具有第二功函数的第二导电材料,其中所述第二功函数不同于所述第一功函数。
20.如权利要求19的方法,其中共形地沉积所述第一金属膜。
21.如权利要求20的方法,其中通过选自包括化学汽相沉积和原子层沉积的组的方法沉积所述第一金属膜。
22.如权利要求19的方法,其中将所述第一导电材料暴露于活性粒子,以改变所述第一导电材料的功函数。
23.如权利要求19的方法,其中所述第一功函数低于所述第二功函数。
24.如权利要求19的方法,其中所述第一功函数大于所述第二功函数。
25.一种晶体管,包括在形成于衬底上的栅电介质层上形成的栅电极。
26.一种形成晶体管的方法,包括:
在衬底上的栅电介质层上形成栅电极,其中所述栅电极具有一对横向相对的侧壁和中心部分,其中横向相对的侧壁具有第一功函数,并且中心部分具有第二功函数,其中第一功函数不同于第二功函数;以及
在所述栅电极的所述横向相对的侧壁的相对侧上的所述衬底中形成一对源/漏区,其中在所述横向相对的侧壁下方形成所述源/漏区的一部分。
27.如权利要求26的方法,其中所述源/漏区由n型电导率形成,并且其中所述第一功函数小于所述第二功函数。
28.如权利要求26的方法,其中所述源/漏区是p型电导率,并且其中所述第一功函数大于所述第二功函数。
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Also Published As
Publication number | Publication date |
---|---|
TWI261923B (en) | 2006-09-11 |
US7285829B2 (en) | 2007-10-23 |
DE112005000729B4 (de) | 2009-10-22 |
WO2005096387A3 (en) | 2006-02-02 |
KR20070003991A (ko) | 2007-01-05 |
WO2005096387A2 (en) | 2005-10-13 |
US7666727B2 (en) | 2010-02-23 |
US20050224886A1 (en) | 2005-10-13 |
KR100847866B1 (ko) | 2008-07-23 |
DE112005000729T5 (de) | 2007-03-22 |
CN100527437C (zh) | 2009-08-12 |
TW200536121A (en) | 2005-11-01 |
US20050221548A1 (en) | 2005-10-06 |
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