CN1933181A - 半导体器件及其制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 28
- 125000006850 spacer group Chemical group 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 26
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- 238000000576 coating method Methods 0.000 claims description 14
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- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
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- 239000010941 cobalt Substances 0.000 claims description 5
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- 229910052760 oxygen Inorganic materials 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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Abstract
提供一种半导体器件。半导体器件包括衬底、栅极、隔离物以及源极和漏极。栅极由衬底上的硅化物形成。隔离物形成在栅极侧壁上。源极和漏极形成在衬底上。栅极比隔离物更为突出。
Description
技术领域
本发明涉及一种半导体器件及其制造方法。
背景技术
构成半导体器件的晶体管性能与晶体管的速度、驱动电流和漏电流密切相关。为了使速度更高和漏电流更小,应该降低晶体管源极和漏极的电阻、晶体管栅极电阻和接触部分的电阻。
为了降低这些区域的电阻,在漏极和源极的界面和栅极界面上形成硅化物层。硅化物层通常由金属和硅的化合物形成,如硅化钛(TiSi2)、硅化铅(PbSi2)、硅化钴(CoSi2)和硅化镍(NiSi2)。
在包括这种硅化物层的半导体器件中,在衬底上形成栅极,并形成覆盖栅极的牺牲层。接着,通过化学机械抛光(CMP)过程移除牺牲层以暴露栅极表面。在栅极上形成金属层并对其热处理形成硅化物。
然而,CMP过程在栅极上表面上导致划伤、残留物等。而且,在抛光过程中,多晶硅层和栅极氧化物层之间的应力增加,由此降低半导体器件的特性,如界面特性。
发明内容
因此,本发明涉及半导体器件及其制造方法,基本上避免由于现有技术的局限和缺点引起的一个或多个问题。
本发明的一个目的是提供一种半导体器件,其能够通过使栅极表面上的划伤和残留物最小化和降低抛光中的应力以稳定形成硅化物来防止半导体器件的电特性下降。
本发明的其它优点、目的和特征将在以下说明书中部分说明,并且当本领域普通技术人员检验以下内容时其在一定程度上将显而易见,或者可从本发明的实施中得到教导。本发明的目的和其它优点可通过在说明书及其权利要求以及附图中具体指出的结构来实现和获得。
为了实现这些目的和其它优点并根据本发明的目的,如本文所示例和广泛描述的那样,提供一种半导体器件,包括:衬底;在衬底上由硅化物形成的栅极;形成在栅极侧壁上的隔离物;和形成在衬底上的源极和漏极。栅极比隔离物更为突出。
在本发明的另一方面,提供一种制造半导体器件的方法,该方法包括:在衬底上堆叠栅极氧化物层、多晶硅层和硬掩模;在多晶硅层的侧壁上形成隔离物;利用外延法在衬底上形成源极和漏极;将高浓度导电型杂质离子植入源极和漏极;在源极和漏极上形成硅化物层;在衬底上形成牺牲层;利用CMP(化学机械抛光)抛光牺牲层和硬掩模以使硬掩模保留预定厚度;以及利用湿蚀刻移除残留部分的硬掩模以暴露多晶硅层的上表面。
应该理解本发明的前述一般性说明和以下具体说明均为示例性和说明性的,用来对所要求的本发明提供进一步的说明。
附图说明
所包括的附图提供对本发明的进一步理解,其被引入并构成本申请的一部分,用来图示本发明的实施方案并与说明书一起用来说明本发明的原理。在附图中:
图1是根据本发明实施方案的半导体器件的截面图;和
图2-7是顺序示出制造根据本发明实施方案的半导体器件的方法的截面图。
具体实施方式
现在具体参考本发明的优选实施方案,其实施例示于附图中。无论何处,全部附图中使用相同的附图标记指示相同或类似的部分。
在附图中,为了清楚说明而将层和区域的尺寸放大。相同的附图标记始终指示相同元件。还应该理解当元件例如层、膜、区域、板等被指出处于另一元件“之上”时,其可以是直接位于另一元件上或也可以存在中间元件。另一方面,应该理解当元件被指出是直接在其它元件之上时,则不存在中间元件。
下文中,将结合附图描述本发明的实施方案。
图1是根据本发明实施方案的半导体器件的截面图。
参考图1,在半导体衬底10中形成器件隔离区12以限定有源区域。在部分有源区域上形成栅极氧化物层14,并且在栅极氧化物层14上形成栅极30。栅极30由硅化镍(NiSi2)和硅化钴(CoSi2)形成。
在栅极30的侧壁上形成缓冲层20a和隔离物20b。缓冲层20a由氧化物材料形成,隔离物20b由氮化物材料形成。缓冲层20a减低栅极30和隔离物20b之间的应力。
在部分半导体衬底10中形成掺杂有高浓度n型或p型杂质的源极和漏极22,其位于栅极30和隔离物20b的两侧。
分别在源极和漏极22上形成硅化物层24。硅化物层24可以由NiSi2和CoSi2形成。
下文中,将参考附图详细描述制造半导体器件的方法。
图2-7是顺序示出制造根据本发明实施方案的半导体器件的方法的截面图。
参考图2,通过局部硅氧化法(LOCOS)或浅沟槽隔离法(STI),在半导体衬底10中形成由绝缘材料形成的器件隔离区12。在LOCOS法中,是通过在衬底的预定区域中部分生长氧化物层来形成器件隔离区,而在STI法中,则是通过在预定区域中形成沟槽并随后用绝缘材料填充沟槽来形成器件隔离区。
参考图3,氧化衬底10以在衬底10上形成氧化物层。通过化学气相沉积法(CVD)等在氧化物层上堆叠多晶硅(Poly-Si)层和氧化物层。多晶硅层形成为1000-2000的厚度。
接着,通过选择性蚀刻依次使氧化物层、多晶硅层和氧化物层图案化,以形成硬掩模18、多晶硅图案16、栅极氧化物层14。硬掩模18用来形成更微细的线并且根据用于选择性蚀刻中的光刻胶的性质而可以省略。
参考图4,在衬底10的整个表面上形成氧化物层和氮化物层,以通过回蚀刻形成隔离物20b和缓冲层20a。虽然没有示出,但是haLo离子、用于形成低浓度掺杂区的离子等可在形成隔离物20b之前植入。
参考图5,通过选择性外延方法在衬底10的暴露部分上形成硅层21。硅层21出掺杂有高浓度导电杂质离子并经热处理以形成源极和漏极22。
所植入的离子是n型或p型杂质,例如砷(As)、磷(P)、硼(B)等。
参考图6,利用稀的氟化氢(HF)从衬底10上移除本生氧化物层。在衬底10上沉积钴(Co),随后在衬底10上实施第一热处理以在源极和漏极22上形成硅化物层24。
硅化物层24可以形成为厚度低于20,并且第一热处理可以于400-600℃下、在氮气氛室中进行不超过2分钟。
利用硫过氧化物混合物(SPM)或标准清洗剂1(SC1)通过湿清洗来移除未形成硅化物的钴。SC1是氢氧化铵或三甲基-氧乙基氢氧化铵(TMH)、过氧化氢(H2O2)和氧化氢(H2O)的混合物。清洗进行5-25分钟。为了稳定硅化物层,可以在氮气氛下于720-920℃进行不超过2分钟的第二热处理。
参考图7,形成覆盖多晶硅图案16的第一和第二牺牲层26和28。第一和第二牺牲层26和28可分别由氧化物材料和氮化物材料形成。
利用CMP抛光第二牺牲层28、第一牺牲层26和硬掩模18,以保留厚度为50或更低的硬掩模18。
通过湿蚀刻移除硬掩模18以暴露多晶硅图案16。在湿蚀刻中,可以使用稀HF、磷酸(H3PO4)、SC1或SPM。在此,以100∶1-200∶1(H2O∶HF)的比例稀释HF,并且H3PO4的浓度为80-90%。SPM是硫酸:H2O2为1∶1的混合物。
如上所述,通过湿蚀刻而不是抛光来暴露多晶硅图案16的上表面,从而减少了多晶硅图案16表面上的损伤。而且,由于硬掩模18被移除,因而多晶硅图案16具有相对于第一和第二牺牲层26和28的预定高度差。当多晶硅图案16形成为栅极时,由于体积膨胀导致栅极突出至第二牺牲层28。在此,多晶硅图案16的高度差可以降低可能产生的应方。
再次参考图1,在衬底10的整个表面上沉积镍以形成镍金属层,并随后在衬底10上实施第一热处理以形成由硅化物形成的栅极30。
由于在热处理过程中镍金属层的体积膨胀2-3倍,因此形成的多晶硅层的厚度足以使多晶硅层充分形成硅化物。例如,如果多晶硅层形成的厚度为1500,则镍金属层可以形成的厚度为600-800。栅极30可以比隔离物20a更为突出,并且突出部分的厚度为约350-1350。
接着,移除未硅化的部分镍金属层,并热处理栅极30以稳定包括栅极30的硅化物。形成硅化镍层的方法与形成图6所示的硅化钴层的方法相同。
本生氧化物层可以在形成栅极30之前形成在多晶硅图案16上,但是其可以在由于移除残留部分的硬掩模18的湿蚀刻中被移除,因而可以省略单独清洗。
如上所述,部分硬掩模保留在栅极上并被湿蚀刻,由此减少由于抛光导致的栅极表面的损伤。而且,由于抛光时间缩短,栅极和栅极氧化物层之间的应力可得以降低,从而防止其间的界面特性下降。
因此,可以制造电特性不下降的高质量半导体器件。
在本发明中可以进行各种修正和变化对于本领域技术人员而言是显而易见的。因此,本发明意图覆盖在所附权利要求及其等同物范围内提供的本发明的各种修正和变化。
Claims (15)
1.一种半导体器件,包括:
衬底;
在衬底上由硅化物形成的栅极;
形成在栅极侧壁上的隔离物;和
形成在衬底上的源极和漏极,
其中栅极比隔离物更为突出。
2.权利要求1的半导体器件,还包括形成在源极和漏极上的硅化物层。
3.权利要求1的半导体器件,其中源极和漏极是通过外延法形成的硅化物层。
4.权利要求1的半导体器件,其中硅化物是硅化镍。
5.权利要求2的半导体器件,其中形成在源极和漏极上的硅化物层是硅化钴层。
6.权利要求1的半导体器件,其中栅极比隔离物还要突出350-1350。
7.权利要求1的半导体器件,还包括形成在除栅极以外的区域中的第一和第二牺牲层。
8.权利要求1的半导体器件,其中第一和第二牺牲层分别由氧化物材料和氮化物材料形成。
9.一种制造半导体器件的方法,该方法包括:
在衬底上堆叠栅极氧化物层、多晶硅层和硬掩模;
在多晶硅层侧壁上形成隔离物;
利用外延法在衬底上形成源极和漏极;
将高浓度导电型杂质离子植入源极和漏极;
在源极和漏极上形成硅化物层;
在衬底上形成牺牲层;
利用CMP(化学机械抛光)抛光牺牲层和硬掩模,以保留预定厚度的硬掩模;和
利用湿蚀刻移除残留部分的硬掩模,以暴露多晶硅层的上表面。
10.权利要求9的方法,还包括在暴露的多晶硅层上表面上形成金属层并硅化该金属层。
11.权利要求9的方法,其中抛光包括将硬掩模抛光至厚度为50或更低。
12.根据权利要求9的方法,其中形成硅化物层包括:
沉积镍和钴之一以形成金属层;和
硅化该金属层。
13.权利要求9的方法,其中牺牲层由氧化物材料和氮化物材料之一形成。
14.权利要求9的方法,其中在湿蚀刻过程中使用以100∶1-200∶1(H2O∶HF)的比例稀释的HF和浓度为80-90%的H3PO4。
15.权利要求9的方法,其中在移除残留部分的硬掩模的过程中,蚀刻多晶硅层以使其具有相对于牺牲层的预定高度差。
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Cited By (2)
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CN101165917B (zh) * | 2006-10-18 | 2010-07-21 | 台湾积体电路制造股份有限公司 | 具有连续接触蚀刻停止层的金属氧化物半导体元件及其制造方法 |
CN103594364A (zh) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
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JP4008860B2 (ja) * | 2003-07-11 | 2007-11-14 | 株式会社東芝 | 半導体装置の製造方法 |
US7067379B2 (en) * | 2004-01-08 | 2006-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Silicide gate transistors and method of manufacture |
TWI252539B (en) * | 2004-03-12 | 2006-04-01 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
US7176537B2 (en) * | 2005-05-23 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance CMOS with metal-gate and Schottky source/drain |
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Cited By (3)
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CN101165917B (zh) * | 2006-10-18 | 2010-07-21 | 台湾积体电路制造股份有限公司 | 具有连续接触蚀刻停止层的金属氧化物半导体元件及其制造方法 |
CN103594364A (zh) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
CN103594364B (zh) * | 2012-08-14 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
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